JPH08106383A - Arithmetic processor - Google Patents

Abstract

PURPOSE: To select the optimum programming and processing modes and an optimum processing speed in response to the contents of processing to be executed. CONSTITUTION: A fast processing program described in a reduction instruction set and a slow processing program described in a fast function instruction set are stored in a main memory 1 centering on a speed switching instruction. When the speed switching instruction is carried out, the execution clocks ϕ' are switched and also the decoders 7 and 11 to which the instruction sets are supplied are switched. A multiplier 16 carries out an operation based on the pipeline processing while a fast program is carried out. Furthermore the multiplier 16 carries out an operation to directly fetch the data from the memory 1 while a slow program is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit in which a reduced instruction set computer (RISC) and a high function instruction set computer (CISC) coexist.

[0002]

2. Description of the Related Art Conventionally, RISC type and CISC type are known as arithmetic processing devices such as a microprocessor and a digital signal processor (DSP).
The RISC type arithmetic processing unit uses a small number of simple instruction sets to execute processing by subdivided execution steps, and improves execution speed by shortening individual execution cycles and high-speed pipeline processing. It is a thing. With the development of VLSI technology, the speed of this type of device is further increased. On the other hand, the CISC type arithmetic processing device has the advantages of using a high-performance instruction set, having high execution efficiency even at a low speed clock, and having good performance with respect to electric power.

[0003]

However, in the RISC type system among the conventional arithmetic processing devices described above, the semantic gap between the high-level language and the machine language is large, and complicated programming by the assembler is required. There's a problem. Further, in order to improve the efficiency of programming, it is necessary to rely on an optimizing compiler, and it is difficult to bring out desired performance. Furthermore, RI
Since the SC type system is premised on the pipeline processing, there is a problem that the execution efficiency is lowered when the program includes many branches. On the other hand, conventional CISC
Type system has a problem that the hardware load for generating micro-instructions from macro-instructions increases and the execution clock cannot be made too fast because the programming burden is reduced by using the high-performance instruction set. is there.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an arithmetic processing unit capable of selecting optimum programming, processing and processing speed according to the contents of processing to be executed. To aim.

[0005]

In the arithmetic processing unit according to the present invention, a high-speed processing program written in a reduced instruction set and a low-speed processing program written in a high-performance instruction set coexist at a speed switching instruction. Storage means for storing the program and data processed by the program, execution clock switching means for switching the frequency of the execution clock according to the speed switching instruction read from the storage means, and sequentially from the storage means according to the execution clock Instruction set reading means for reading an instruction set, first instruction decoding means for decoding the reduced instruction set of the instruction set read by the instruction set reading means and outputting a first control signal, and the instruction The high-performance instruction set among the instruction sets read by the set reading means Second instruction decoding means for decoding and outputting a second control signal, and instruction decoding switching means for switching the first and second instruction decoding means in accordance with the speed switching instruction read from the storage means, Arithmetic processing means for executing arithmetic processing based on pipeline processing according to the first control signal, and for executing arithmetic processing for directly fetching data from the storage means according to the second control signal. To do.

[0006]

According to the present invention, when the high speed processing program written in the reduced instruction set and the low speed processing program written in the high function instruction set are stored in the storage means at the speed switching instruction, The execution clock is switched from the time when the switching instruction is read and executed, and the first and second instruction decoding means are switched. As a result,
During execution of the high-speed program, the reduced instruction set is read in accordance with the high-speed execution clock, and the arithmetic means executes arithmetic processing based on pipeline processing in accordance with the first control signal from the first instruction decoding means. Further, when the program is switched from the high speed program to the low speed program by the speed switching instruction, the high function instruction set is read according to the low speed execution clock, and the arithmetic means is operated by the second control signal from the second instruction decoding means. An arithmetic process for directly fetching data from the storage means is executed.

The speed of the execution clock can be switched so that the most efficient processing can be performed at the time of execution of the reduced instruction set and at the time of execution of the high-performance instruction set. Will be fully enhanced. Further, since the clock and the instruction set can be switched in the program, the programmer can easily switch the instruction set at any timing.

Therefore, according to the present invention, for example, for processing with few branches and high speed, a high-speed program is described in a reduced instruction set, and for processing with many branches and high speed is not required. The efficient programming and the efficient processing can be selected according to the contents of the processing, such as writing the low speed program in the high function instruction set.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention. The main memory 1 stores a program in which a high speed program written in a reduced instruction set and a low speed program written in a high function instruction set coexist at a speed switching instruction, and data processed by the program. There is. The read address of the instruction set read from the main memory 1 is read from the program counter (PC) 2 via the address bus 3 to the main memory 1.
Given to. The instruction set read from the main memory 1 is fetched into the instruction register (IR) 5 via the data bus 4. The instruction set fetched in the instruction register 5 is supplied to either one of the RISC decoder 7 and the mapping unit 8 by the selection circuit 6. Which is supplied to the R / C stored in the R / C register 9
Although it is determined by the value of the flag, the reduced instruction set is RI
The SC decoder 7 and the high-performance instruction set are supplied to the mapping unit 8.

When the reduced instruction set is supplied to the RISC decoder 7, the decoder 7 decodes the instruction set to perform the first decoding.
The control signal C1 is output. On the other hand, when the high function instruction set is supplied to the mapping unit 8, the mapping unit 8 outputs the head address of the corresponding micro instruction from the supplied high function instruction set which is the macro instruction. This head address is supplied to the address selection unit 10, where the addresses for designating microinstructions are sequentially generated. This address is supplied to the CISC decoder 11, and the second control signal C2 is generated. When the low speed switching instruction is supplied to the RISC decoder 7, the RISC decoder 7 rewrites the R / C flag of the R / C register 9 to the low speed mode. Further, when the high speed switching command is supplied to the CISC decoder 11, the CISC decoder 11 causes the R / C register 9 to read the R / C register 9.
Rewrite the C flag to high speed mode.

On the other hand, the data read from the main memory 1 is transferred to the registers (REGA, REG) via the data bus 4.
B) The signal is supplied to one input terminal of each of 12, 13 and the selection circuits 14, 15. The outputs of the registers 12 and 13 are supplied to the other input terminals of the selection circuits 14 and 15, respectively. The selection circuits 14 and 15 select the direct output from the main memory 1 when the R / C flag is set to the low speed mode, and when the R / C flag is set to the high speed mode, The output of the registers 12 and 13 is selected. Selection circuit 1
The outputs of 4 and 15 are input to, for example, a multiplier 16 as a calculation means. The output of the multiplier 16 is a register (REG
C) is stored in 17 and is further written in the main memory 1 via the data bus 4.

The master clock φ, which serves as a reference for the execution cycle of this system, is supplied to one input terminal of the selection circuit 18 and, at the same time, is supplied to the selection circuit 18 via the frequency dividing circuit 19.
Is supplied to the other input end of the. The selection circuit 18 is R
When the / C flag is set to the low speed mode, the output of the frequency dividing circuit 19 is selected, and when the R / C flag is set to the high speed mode, the master clock φ is selected as it is. The output of the selection circuit 18 becomes the execution clock φ'which determines the execution cycle and is supplied to each unit.

Next, the operation of this system will be described. FIG. 2 is a diagram schematically showing an example of a program stored in the main memory 1. In this program, a low speed program 21, a high speed program 22, and a low speed program 23 are arranged in this order. The low speed programs 21 and 23 are described by a high function instruction set, and the high speed program 22 is described by a reduced instruction set. In the last line of the low speed program 21, a high speed switching instruction is described with a high function instruction set. Further, in the last line of the high speed program 22, a low speed switching instruction is described in a reduced instruction set.

FIG. 3 shows a more specific description example of these instruction sets, in which a multiplication program of memory data is described by a reduced instruction set and a high function instruction set, respectively. As shown in FIG. 3A, when a memory data multiplication program is written in a reduced instruction set, the data at the address AD1 in the main memory 1 is stored in a register (REG).
A) MOV instruction stored in 12; MOV instruction storing data at address AD2 of main memory 1 in register (REGB) 13; MULT instruction stored in register (REGC) 17 after multiplication by REGA 12 and REGB 13 It is necessary to describe one instruction set. On the other hand, as shown in FIG. 2B, when a multiplication program of memory data is described with a high-performance instruction set, data of address AD1 of main memory 1 and address AD of main memory 1 are written.
MUL which multiplies with the data of 2 and stores in REGC17
One of the T commands is enough.

Now, assuming that the system is set to the low speed mode, the execution clock φ'is a low speed clock obtained by dividing the master clock φ by n. The division ratio 1 /
The value n is set to a value capable of increasing the maximum processing efficiency in the low speed mode, for example, 1/2. Each instruction set is fetched from the main memory 1 into the instruction register 5 according to the low-speed clock. The instruction set fetched in the instruction register 5 is decoded by the CISC decoder 11. In the low speed mode, since the data on the data bus 4 can be directly supplied to the input of the multiplier 16, the selection circuits 14 and 15 select the data bus 4 side. In this case, the data in the main memory 1 is set in the multiplier 16 twice. When a high speed switching command is given during execution of the low speed program, the CISC decoder 11
The R / C flag of the R / C register 9 is switched to the high speed mode.

When the R / C flag is switched to the high speed mode, the execution clock φ'becomes a high speed clock having the same speed as the master clock, and the selection circuit 6 activates the RISC decoder 7. Therefore, the instruction set is fetched into the instruction register 5 at high speed and decoded by the RISC decoder 7. In this mode, the stages for fetching, decoding, computing, memory access, etc. of the instruction set are pipelined to increase the speed. Further, in this mode, it is not possible to directly supply the data from the main memory 1 to the multiplier 16 in terms of speed, so the selection circuits 14 and 15 select the registers 12 and 13 side, respectively. The data from 1) is once stored in the registers 12 and 13. The registers 12 and 13 and the multiplier 16 are also pipelined, so that one multiplication cycle is sufficient.

In the above system, the present invention has been described by taking the multiplication processing in the multiplier as an example.
It goes without saying that the same switching operation is performed in other arithmetic processing units such as (arithmetic logic unit).

[0018]

As described above, according to the present invention,
A high-speed program and a low-speed program coexist with a speed switching instruction as a boundary. During high-speed program execution, arithmetic processing based on pipeline processing is executed according to a high-speed execution clock, and the program changes from a high-speed program to a low-speed program according to the speed switching instruction. When it is switched to, the arithmetic processing for directly fetching the data from the storage means is executed according to the low-speed execution clock, so that efficient programming and efficient processing and processing time can be easily selected according to the content of the processing. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processing unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a program stored in a main memory in the same system.

FIG. 3 is a diagram illustrating a description example of a memory multiplication process using a reduced instruction set and a high-performance instruction set.

[Explanation of symbols]

1 ... Main memory, 2 ... Program counter, 3 ... Address bus, 4 ... Data bus, 5 ... Instruction register, 6, 14,
15, 18 ... Selection circuit, 7 ... RISC decoder, 8 ...
Mapping section, 9 ... R / C register, 10 ... Address selection section, 11 ... CISC decoder, 12, 13, 17 ...
Register, 19 ... Divider circuit.

Claims (1)

[Claims] 1. A program in which a high-speed processing program written in a reduced instruction set and a low-speed processing program written in a high-performance instruction set coexist with a speed switching instruction as a boundary, and a memory for storing data processed by the program. Means, execution clock switching means for switching the frequency of the execution clock according to the speed switching instruction read from the storage means, instruction set reading means for sequentially reading out the instruction set from the storage means according to the execution clock, and the instruction set A first instruction decoding unit that decodes the reduced instruction set of the instruction set read by the reading unit and outputs a first control signal; and the first instruction decoding unit of the instruction set read by the instruction set reading unit, The second instruction that decodes the high-performance instruction set and outputs the second control signal Decoding means, instruction decoding switching means for switching the first and second instruction decoding means in accordance with the speed switching instruction read from the storage means, and arithmetic processing based on pipeline processing in accordance with the first control signal. An arithmetic processing unit for executing the arithmetic processing and executing arithmetic processing for directly fetching data from the storage means according to the second control signal.