JPH03147131A - Microcomputer - Google Patents

Abstract

PURPOSE:To decrease the number of elements and to reduce a chip area by generating all control signals except a leading first machine cycle with a dynamic decoder. CONSTITUTION:A dynamic decoder 2 decodes an encoding signal 9 and a machine cycle signal 8 similarly to a static decoder 1, generates a control signal 6, and controls an ALU 4. A dynamic decoder 3 executes the same operation as that of the dynamic decoder 2. In this case, a pre-charge timing of the dynamic decoder 2 is different from the pre-charge timing of the dynamic decoder 3, and by the dynamic decoder 2, a necessary control signal can be generated at the timing of other machine cycle than the leading machine cycle. In such a manner, a part of the static decoder can be converted to a dynamic decoder, and the chip area at the time of converting to an LSI can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to an instruction code that decodes an instruction code, encodes the decoded signal, and further decodes the encoded signal to generate a control signal. Regarding decoding circuits.

[Conventional technology]

A typical microcomputer has a configuration shown in the block diagram of FIG. 3. The instruction code output to the data bus 12 is latched by the instruction register 13 and input to the instruction decoder 14. Instruction decoder 1
In step 4, it is determined what kind of instruction the input instruction code is and a decode signal is generated.

-m, in a microcomputer, each instruction is executed in an integral multiple of a predetermined number of clocks as a basic unit time (hereinafter referred to as a machine cycle). That is, the execution time differs depending on the instruction, such as an instruction whose instruction processing is completed in one machine cycle or an instruction whose instruction processing is completed in three machine cycles. Therefore, we must detect whether the instruction we are about to execute requires several machine cycles to execute.

Instruction decoder 14 detects whether an instruction to be executed requires several machine cycles, and sets machine cycle counter 16 to the number of machine cycles required for that instruction. The machine cycle counter 16 counts the number of instructions being executed every time one machine cycle elapses, and in order to notify which machine cycle is being executed, the machine cycle counter 16 uses an arithmetic logic operation circuit (hereinafter referred to as ALU) 22. Register 23. Machine cycle signal 1 is sent to each functional block such as the address generation unit 24.
Output as 8.

The number of decoded output signals from the instruction decoder 14 is the same as the number of instructions that the microcomputer has. If this decoded output signal is directly wired to each functional block such as an ALU, the number of wires will be enormous. In order to avoid this, the decoded signal of the instruction decoder 14 is encoded, the encoded signal 17 is wired to each functional block such as the ALU using fewer wires, and the encoded signal 17 is decoded in each functional block. This decoded signal becomes the control signals 25 to 27 of the functional blocks. Therefore, the instruction code and the encode signal 17 have a one-to-one correspondence. Further, during the instruction execution period, the encode signal 17 remains unchanged.

However, in the case of an instruction that requires multiple machine cycles to execute, various controls must be performed for each machine cycle, so when decoding the encoded signal 17 in each functional block, the machine cycle signal
It is necessary to generate control signals 25 to 27 every 8 seconds.

FIG. 4 is a block diagram of the decoder 19 that generates control signals for each functional block (ALU in this example). The encode signal 9 and machine cycle signal 8 described above are decoded using the static decoder 1 and the dynamic decoder 3 to generate control signals 5.7 for the ALU 4. The reason why this decoder is divided into static decoder 1 and dynamic decoder 3 is that the encoded signal 9
The control signal that must be generated immediately after the ALU is determined, that is, the control signal 5 that must immediately control the ALU, must be decoded and generated by the static decoder 1, which has a high decoding speed. , after a while after the encode signal 9 is confirmed, A
This is because the control signal 7 that requires control of the LU can have a smaller layout area when converted into an LSI by using the dynamic decoder 3.

FIG. 5 is a circuit diagram of an example of the static decoder 1, which is an example of a circuit that activates the decode output when the encode signal 9 (E3 to EO) has a logic level of 0.1 and 0.1, respectively. In this case, after the values of the encode signals E3 to EO are determined, the decode output is for two stages of gates (
It becomes active after the delay time of the NOR gate 31 and AND gate 32) has elapsed. Usually, the delay time of one stage of LSI gate is about several n5ec or less.

FIG. 6 is a circuit diagram in which the static decoder 1 of FIG. 5 is configured with a dynamic decoder.

It is composed of inverters 33-36 and transistors Q1-Q6. A dynamic decoder can have a smaller number of transistors than a static decoder, so it has the advantage of reducing the layout area when integrated into an LSI.

FIG. 7 is a timing diagram illustrating the operation of the dynamic decoder of FIG. 6. When the precharge signal φPRE is active "1", the P channel transistor RO 1 is in the on state and the N channel transistor RO 6 is in the off state. Therefore, the potential at point A is charged up to the power supply voltage level DD. When the precharge signal φPRE becomes inactive "0", the P-channel transistor Ql is turned off and the N-channel transistor Q1 is turned on. At this time, when the encode signals E3 to EO are 0, 1, and 0.1, respectively, the N-channel transistors 2 to Q5 are turned on, and the potential at point a is gradually discharged to the ground level. When the potential at point A reaches the threshold potential of the inverter 35,
The decode output becomes active "1" level.

On the other hand, encoded signals E3 to EO are 0.1.0
．． For combinations other than 1, any one of the N-channel transistors Q2 to Q5 is necessarily in the off state, and even after the precharge signal φPRt level becomes inactive "0", the potential at point A is The power supply VDD level is maintained, and the decode output remains inactive "0".

As explained above, in the dynamic decoder 2, after the precharge signal φpat becomes inactive "0", the decode output becomes active "1" after a discharge time. Normally, this discharge time is several tens of nanoseconds. It is.

Furthermore, the change in E3 to EO must be completed during the period in which φPRP is "1", and the discharge timing will be delayed here as well.

FIG. 8 is a timing diagram of instruction decoding of the microcomputer shown in FIGS. 3 and 4. FIG. Microcomputer system clocks φ0 to φ3 are generated from the basic operating clock. Here, the system clocks φ0 to φ3 are clocks for the basic timing of the operation of the microcomputer. Furthermore, the system clock φ
One period of 0 is one machine cycle, and all instructions of the microcomputer are executed in a time that is an integral multiple of the machine cycle. In addition, system clocks φ0 to φ3 each serve as a unit of basic operation for executing an instruction. For example, when the system clock φO is active "1", the instruction code is sampled and an encode signal is generated. and system clock φ
2 performs operations such as outputting the contents of the register to the data bus.

Next, the operation shown in FIG. 3 will be explained with reference to the operation timing chart shown in FIG. In the case of an instruction executed in one machine cycle (referred to as one machine instruction), the instruction code is sampled during the active period of the system clock φO, and at the same time the encode signal 17 is generated, the machine cycle counter 16 is set to "0". . A value of "0" in the machine cycle counter 16 means that the relevant machine cycle is the final machine cycle for that instruction. A control signal 5 for performing a basic operation using a system clock φ1 is generated by a static decoder 1 that statically decodes an encode signal 9. Once the encode signal is determined, the static decoder 1 determines the control signal several n5ec later. When performing basic operations using system clock φ2 or φ3, the control signal is
It is determined after a discharge period (several tens of nanoseconds).

In the case of an instruction executed in three machine cycles (three machine instructions), the instruction code is sampled only during the first active period of the system clock φO, and at the same time, the machine cycle counter 16 is set to r2J. Thereafter, the machine cycle counter 16 is decremented by "1" every machine cycle. When the machine cycle counter 16 is "2", the method of generating the control signal is the same as in the case of one machine instruction described above.

Further, control signals are generated in the same manner from the second machine cycle of three machine instructions onwards. However, since the encode signal 17 remains unchanged over three machine cycles, it is necessary to distinguish machine cycles in the decoders 19, 20, 21 which generate the control signals.

[Problem to be solved by the invention]

The conventional microcomputer instruction decoding circuit described above uses a static decoder to generate the necessary control signals at system clock 1 of each machine cycle, even for instructions that require multiple machine cycles to execute. , the number of control signals generated by the static decoder increases, and therefore the number of static decoders increases, resulting in an increase in the number of transistor elements and the chip area.

An object of the present invention is to reduce the number of elements and chip area by generating all control signals other than the first machine cycle using a dynamic decoder for instructions that require multiple machine cycles to execute. Our goal is to provide microcomputers.

[Means to solve the problem]

The configuration of the present invention includes: a first decoder that decodes an instruction code; a functional unit block that executes various processes in response to the instruction code;
A microcomputer includes an encoder that encodes the first decoded output as a control signal code for controlling each of these functional unit blocks, and includes a plurality of dynamic decoders that operate at different sampling timings to control each of the functional unit blocks. The present invention is characterized by comprising a second decoder that generates a signal by decoding the encoded output of the encoder.

Further, in the present invention, the second decoder includes a first dynamic decoder that decodes the encoded signal of the encoder, and a second dynamic decoder whose sampling timing is different from that of the first dynamic decoder, and The first dynamic decoder outputs a control signal that controls the operation using the clocks of machine cycles other than the first machine cycle of an instruction that requires multiple machine cycles, and the second dynamic decoder outputs a control signal that controls the operation using the clocks of all machine cycles. It is possible to output a control signal for controlling.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. An encode signal and a machine cycle signal 8 are input to the static decoder 1 . The encode signal 9 and the machine cycle signal 8 are each encoded signal 1 in FIG.
7. It is the same as machine cycle signal 18. The static decoder 1 decodes the encode signal and the machine cycle signal 8, generates a control signal 5, and controls the ALU 4. In the case of an instruction that requires a plurality of machine cycles to execute, the static decoder 1 generates a control signal only in the corresponding machine cycle so that only the first machine cycle is valid.

Similar to the static decoder 1, the dynamic decoder 2 decodes the encode signal and the machine cycle signal 8, generates a control signal 6, and controls the ALU 4. This dynamic decoder 2 becomes effective (E) in machine cycles other than the first machine cycle of an instruction that requires a plurality of machine cycles to execute. The dynamic decoder 3 has the same operation timing and function as the dynamic decoder 3 shown in FIG. 4, so a description thereof will be omitted.

FIG. 2 is an operation timing chart of this embodiment. Basic operating clock, system clock φ0 to φ3. The instruction decoder sampling signal and encode signal are the same as in the conventional example. Static decoder output (
That is, the control signal generated by the static decoder) controls the operation at the system clock φ1 of the first machine cycle of the instruction. The output (control signal) of the dynamic decoder 3 controls the operation at the system clocks φ2 and φ3 of all machine cycles.The dynamic decoder 2 outputs instructions that require multiple machine cycles to execute in machine cycles other than the first machine cycle. A control signal is generated to control the operation of the system clock φ1.

The precharge timing of the dynamic decoder 2 of this embodiment is characterized in that the precharge timing of the dynamic decoder 3 is different, and the dynamic decoder 2 generates a necessary control signal at timing φ1 of a machine cycle other than the first machine cycle. be able to.

〔Effect of the invention〕

As explained above, by having a dynamic decoder that operates at different sampling timings, the present invention can reduce the control signals caused by the static decoder, that is, it is possible to convert a part of the static decoder into a dynamic decoder, and when integrated into an LSI. This has the effect of reducing the chip area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an instruction decoding circuit according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of FIG. 1, FIG. 3 is a block diagram of an example of a conventional microcomputer, and FIG. 4 is a block diagram of an example of a conventional microcomputer. 3 is a block diagram of an example of the instruction decoding circuit, FIG. 5 is a circuit diagram of an example of the static decoder of FIG. 4, FIG. 6 is a circuit diagram of an example of the dynamic decoder of FIG. The operation timing diagram of the dynamic decoder shown in Fig. 8 is
FIG. 3 is an operation timing diagram of the instruction decoding circuit shown in the figure. 1... Static decoder, 2.3... Dynamic decoder, 4.22... Arithmetic logic operation circuit (AL
U>, 5, 6, 7, 25, 26.27... control signal,
8.18... Machine cycle signal, 917... Encode signal, 11... Address bus, 12... Data bus, 13... Instruction register, 14
...Instruction decoder, 15...Instruction decoder, 16...Machine cycle counter, 19, 20.21...Decoder, 23...Register, 24...Address generation unit, 31...N
OR gate, 32...AND gate, 33 34.3
5.36...Inverter, Ql...P channel transistor, Q2-Q6...N channel transistor,
C8...Retention capacity.

Claims (3)

[Claims] (1) A first decoder that decodes an instruction code, a functional unit block that executes various processes in response to the instruction code, and the first decoder as a control signal code that controls each of these functional unit blocks. a second decoder that includes a plurality of dynamic decoders each operating at different sampling timings and generates a control signal for each of the functional unit blocks by decoding the encoded output of the encoder; A microcomputer characterized by being equipped with. (2) The second decoder includes a first dynamic decoder that decodes the encoded signal of the encoder, and a second dynamic decoder whose sampling timing is different from that of the first dynamic decoder. microcomputer. (3) The first dynamic decoder outputs a control signal that controls the operation using the clocks of machine cycles other than the first machine cycle of an instruction that requires multiple machine cycles, and the second dynamic decoder outputs a control signal that controls the operation using the clocks of machine cycles other than the first machine cycle of an instruction that requires multiple machine cycles. 3. The microcomputer according to claim 2, wherein the microcomputer outputs a control signal for controlling the operation of the microcomputer.