JPH05224968A - Data check system - Google Patents

Abstract

PURPOSE:To detect and correct the data errors in a bus interface device in an early stage by providing a calculation circuit and a comparator of data check codes in the bus interface device. CONSTITUTION:This system is provided with a memory bus 1, an input/output bus 2, an arithmetic processor 3, a main storage 4, a bus interface device 5, and the input/output devices 6-8. When the device 6 writes the data into the storage 4, the device 6 outputs the write data and its check code on the bus 2. The device 5 calculates a check code from the data onto the bus 2 by a check code calculation circuit. Meanwhile the check codes are compared with each other by a check code comparator. When the coincidence of check codes is secure, i.e., a normal state is confirmed, the write data is outputted onto a memory bus 1. If not, an error signal is outputted to the bus 2 and no data is outputted to the bus 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer data check method, and more particularly to a data check method using a bus interface.

[0002]

2. Description of the Related Art Conventionally, in this type of system, a bus interface device has a function of comparing a check code of received data with a check code calculated by itself, and of generating a syndrome from the received data and the check code. Absent. The bus interface device did not check the data and check code received from the bus, but output them as they were.

[0003]

In the above-mentioned conventional method, for example, when data is written from the input / output device on the input / output bus to the main storage device on the memory bus, the data output by the input / output device and the check code are The data arrives at the main memory via the bus interface device and is checked by the main memory to determine whether it is an error.

When the input / output device reads data from the main storage device, the data output by the main storage device and the check code reach the input / output device via the bus interface device and are checked by the input / output device for error. It turned out whether.

Next, for example, when writing data from the arithmetic processing unit on the memory bus to the input / output unit on the input / output bus,
The data output by the arithmetic processing unit and the check code arrived at the I / O device via the bus interface unit and were checked by the I / O unit to find out whether or not there was an error.

When the arithmetic processing device reads data from the input / output device, the data output by the input / output device and the check code reach the arithmetic processing device through the bus interface device and are checked by the arithmetic processing device to cause an error. It turned out whether.

This method has a problem that it takes time to determine whether or not the transfer data is normal after the input / output device or the arithmetic processing device starts to start.

An object of the present invention is to allow a bus interface device to detect a data error at an early stage when a large amount of data transfer such as block transfer is performed.

[0009]

[Means for solving the problem]

(1) In order to solve the above problem, in the present invention, the check code calculation circuit for calculating the check code from the data received by the bus interface device and the check code calculated by the check code calculation circuit match the received check code. It has a check code comparison circuit for comparing whether or not it is. If the check codes do not match, the bus interface device outputs an error signal. (2) Further, the present invention includes a syndrome generation circuit that generates a syndrome from the data received by the bus interface device and the check code. Therefore, when a syndrome is generated and an error is detected, an error signal is output.

[0010]

In the data processing device including the arithmetic processing device, the main memory device and the plurality of input / output devices, the bus interface device connecting the memory bus and the input / output bus detects and corrects an error in the received data. By having the function to do so, it is possible to detect and correct it at an early stage.

[0011]

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the entire information processing apparatus according to the present invention.

Reference numeral 1 is a memory bus, 2 is an input / output bus, 3 is an arithmetic processing unit, 4 is a main storage unit, 5 is a bus interface unit, and 6 to 8 are input / output units. (1) FIG. 2 shows an embodiment in which the bus interface device 5 in the configuration of FIG. 1 includes a check code calculation circuit 51 and a check code comparison circuit 52. There is a parity check and the like in this system.

When the input / output device 6 writes data to the main storage device 4, the input / output device 6 outputs a check code of the data on the input / output bus 2 together with the write data. The bus interface device 5 calculates a check code in the check code calculation circuit 51 from the data on the input / output bus 2. The check code calculated thereafter enters the check code comparison circuit 52. The check code on the input / output bus 2 enters the check code comparison circuit 52 of the bus interface device 5. Check code comparison circuit 52
Then, the two check codes are compared with each other. If they match, that is, if the data is normal, the bus interface device 5 outputs the received write data onto the memory bus 1. If they do not match, the bus interface device 5 judges that an error has occurred in the data, outputs an error signal on the input / output bus 2, and notifies the input / output device 6 of the error. In this case, no data is output on the memory bus 1.

Next, a case where the input / output device 6 reads data from the main memory 4 will be described. The main storage device 4 outputs a check code of data on the memory bus 1 together with the read data. The bus interface device 5 calculates a check code in the check code calculation circuit 51 from the data on the memory bus 1. The check code calculated thereafter enters the check code comparison circuit 52. The check code on the memory bus 1 enters the check code comparison circuit 52 of the bus interface device 5. The check code comparison circuit 52 compares the two check codes, and if the two check codes match, that is, if the data is normal, the bus interface device 5 outputs the received read data to the input / output bus 2. If they do not match, the bus interface device 5 determines that an error has occurred in the data, outputs an error signal on the input / output bus 2, and notifies the input / output device 6 of the error. Also, no data is output on the input / output bus 2.

Next, when the arithmetic processing unit 3 writes data to the input / output unit 6, the arithmetic processing unit 3 outputs a check code of data on the memory bus 1 together with the write data. The bus interface device 5 calculates a check code in the check code calculation circuit 51 from the data on the memory bus 1. The check code calculated thereafter enters the check code comparison circuit 52. Also, memory bus 1
The above check code enters the check code comparison circuit 52 of the bus interface device 5. The check code comparison circuit 52 compares the two check codes, and if the two check codes match, that is, if the data is normal, the bus interface device 5 outputs the received write data to the input / output bus 2. If they do not match, the bus interface unit 5 judges that an error has occurred in the data, outputs an error signal on the memory bus 1, and notifies the arithmetic processing unit 3 of the error. In this case, no data is output on the input / output bus 2.

Next, a case where the arithmetic processing unit 3 reads data from the input / output unit 6 will be described. The input / output device 6 outputs a read data and a data check code onto the input / output bus 2. The bus interface device 5 calculates a check code in the check code calculation circuit 51 from the data on the input / output bus 2. The check code calculated thereafter enters the check code comparison circuit 52. Also,
The check code on the input / output bus 2 enters the check code comparison circuit 52 of the bus interface device 5. The check code comparison circuit 52 compares the two check codes, and if the two check codes match, that is, if the data is normal, the bus interface device 5 outputs the received read data onto the memory bus 1. If they do not match, the bus interface device 5 determines that an error has occurred in the data, outputs an error signal on the memory bus 1, and notifies the input / output device 6 of the error. Also, no data is output on the input / output bus 2. (2) FIG. 3 shows an embodiment in which the bus interface device 5 includes the syndrome generation circuit 53 in the configuration of FIG. An error correction code (ECC) or the like is used in this system.

When the input / output device 6 writes data to the main storage device 4, the input / output device 6 outputs a check code of data on the input / output bus 2 together with write data. The bus interface device 5 calculates the syndrome in the syndrome generation circuit 53 from the data on the input / output bus 2 and the check code. As a result, if the data is normal, the bus interface device 5 outputs the received write data onto the memory bus 1. If an error is detected, the bus interface device 5 determines that an error has occurred in the data, outputs an error signal on the input / output bus 2, and notifies the input / output device 6 of the error. In this case, no data is output on the memory bus 1.

Next, a case where the input / output device 6 reads data from the main storage device 4 will be described. The main storage device 4 outputs a check code of data on the memory bus 1 together with the read data. The bus interface device 5 calculates the syndrome in the syndrome generation circuit 53 from the data on the memory bus 1 and the check code. as a result,
If the data is normal, the bus interface device 5
Outputs the received read data to the input / output bus 2. If an error is detected, the bus interface unit 5 determines that an error has occurred in the data and the input / output bus 2
An error signal is output above and the input / output device 6 is notified of the error. Also, no data is output on the input / output bus 2.

Next, when the arithmetic processing unit 3 writes data to the input / output unit 6, the arithmetic processing unit 3 outputs a check code of data on the memory bus 1 together with the write data. The bus interface device 5 calculates the syndrome in the syndrome generation circuit 53 from the data on the memory bus 1 and the check code. As a result, if the data is normal, the bus interface device 5 outputs the received write data onto the input / output bus 2. If an error is detected, the bus interface device 5 determines that an error has occurred in the data, outputs an error signal on the memory bus 1, and notifies the arithmetic processing device 3 of the error. In this case, no data is output on the input / output bus 2.

Next, a case where the arithmetic processing unit 3 reads data from the input / output unit 6 will be described. The input / output device 6 outputs a read data and a data check code onto the input / output bus 2. The bus interface device 5 calculates the syndrome in the syndrome generation circuit 53 from the data on the input / output bus 2 and the check code. As a result, if the data is normal, the bus interface device 5 outputs the received read data onto the memory bus 1. If an error is detected, the bus interface device 5 determines that an error has occurred in the data, outputs an error signal on the memory bus 1, and notifies the input / output device 6 of the error. Also, no data is output on the input / output bus 2. (3) FIG. 4 shows an embodiment in which the bus interface device 5 includes the syndrome generation circuit 53 and the error correction circuit 54 in the configuration of FIG. In this case, the bus interface device 5 calculates the syndrome in the syndrome generation circuit 53, judges that the data has an error according to the syndrome when the error is detected, and the error correction circuit 54 corrects the received data according to the syndrome, A method of outputting correct data in which

[0022]

As described above, according to the present invention, since the bus interface device for connecting the memory bus and the input / output bus has the data check code calculation circuit and comparison circuit, or the syndrome generation circuit, block transfer and the like can be performed. When a large amount of data is transferred, a data error can be detected and corrected early in the bus interface device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an entire information processing apparatus according to the present invention.

FIG. 2 is a configuration diagram of a bus interface device having a check code calculation circuit and a comparison circuit.

FIG. 3 is a configuration diagram of a bus interface device having a syndrome generation circuit.

FIG. 4 is a configuration diagram of a bus interface device having a syndrome generation circuit and an error correction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory bus 2 input / output bus 3 arithmetic processing device 4 main memory device 5 bus interface device 6 to 8 input / output device 51 check code calculation circuit 52 check code comparison circuit 53 syndrome generation circuit 54 error correction circuit

Claims (3)

[Claims] 1. A memory bus, an input / output bus, a bus interface device for connecting the memory bus and the input / output bus, a processing unit and a main memory device connected on the memory bus. In an information processing device having a plurality of input / output devices on an output bus, a bus interface device receives a check code calculation circuit that calculates a check code from the data received from the bus and a check code calculated by itself and the bus. When the input / output device transfers data to / from the main storage device via the bus interface device, or the arithmetic processing device has a check code comparison circuit for comparing the check code with the input / output device via the bus interface device. When data is delivered, the device that outputs the data checks the data together with the data. The bus interface device calculates the check code from the data received by the check code calculation circuit and compares the check code with the received check code to compare the check code with each other. A data check method characterized by detecting. 2. A memory bus, an input / output bus, a bus interface device for connecting the memory bus and the input / output bus, and an arithmetic processing unit and a main storage device connected on the memory bus. In an information processing device having a plurality of input / output devices on an output bus, a bus interface device has a syndrome generation circuit, and the syndrome generation circuit generates a syndrome from data received from a device that outputs data and a check code. A data check method characterized by early detection of errors during data transfer by generating and detecting errors. 3. The data check system according to claim 2, further comprising an error correction circuit that corrects a transfer error according to the syndrome when an error is detected in the generated syndrome.