JPH05218509A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH05218509A JPH05218509A JP4038401A JP3840192A JPH05218509A JP H05218509 A JPH05218509 A JP H05218509A JP 4038401 A JP4038401 A JP 4038401A JP 3840192 A JP3840192 A JP 3840192A JP H05218509 A JPH05218509 A JP H05218509A
- Authority
- JP
- Japan
- Prior art keywords
- optical semiconductor
- conductor pattern
- recess
- package
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/8506—Containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Light Receiving Elements (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
Abstract
(57)【要約】
【目的】 プラスチックパッケージの外部表面の導体パ
ターンをプリント基板の導体に半田付けにより実装する
際、導体パターン間で短絡が発生しないようにする。
【構成】 プリント基板等に装着する面に複数個の突起
部を設け、光半導体チップの各電極に接続される導体パ
ターンを上記突起部の表面にまで導いた。
(57) [Summary] [Purpose] When soldering the conductor pattern on the outer surface of the plastic package to the conductor of the printed circuit board, a short circuit does not occur between the conductor patterns. [Structure] A plurality of protrusions are provided on a surface to be mounted on a printed circuit board or the like, and a conductor pattern connected to each electrode of an optical semiconductor chip is guided to the surface of the protrusion.
Description
【0001】[0001]
【産業上の利用分野】本発明は、中央部に凹部を備えた
プラスチックパッケージの上記凹部内部の底面上に光半
導体チップが搭載され、該光半導体チップの各電極がそ
れぞれ該プラスチックパッケージ表面に設けられた上記
凹部内部の底面上から該パッケージの外部表面に達する
導体パターンに接続され、上記凹部内部に光透過性封止
樹脂が充填されてなる光半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor chip mounted on the bottom surface of the inside of the recess of a plastic package having a recess at the center, and each electrode of the optical semiconductor chip is provided on the surface of the plastic package. The present invention relates to an optical semiconductor device, which is connected to a conductor pattern reaching the outer surface of the package from above the bottom surface inside the recess, and in which the inside of the recess is filled with a light-transmissive sealing resin.
【0002】[0002]
【従来の技術】図5は従来のこの種の光半導体装置の一
例の構造を示す。中央部に凹部を備えたプラスチックパ
ッケージ1の表面に凹部内部の底面上からパッケージ1
の裏面に達する2つの導体パターン2が設けられてい
て、凹部内部の底面の一方の導体パターン2上に光半導
体チップ3がダイボンドされ、光半導体チップ3の上面
の電極と上記導体パターンとは電気的に分離した別の導
体パターン2が金線4で接続された後、パッケージ1の
凹部内部に光透過性封止樹脂5が充填されて形成され
る。この種の光半導体装置では、導体パターン2の一端
はパッケージ1の裏面に導かれていて、裏面の導体パタ
ーン2部分がプリント基板等に半田付けされて実装され
る。2. Description of the Related Art FIG. 5 shows the structure of an example of a conventional optical semiconductor device of this type. On the surface of the plastic package 1 having a recess in the center, the package 1 is
Two conductor patterns 2 reaching the back surface of the optical semiconductor chip 3 are die-bonded to one conductor pattern 2 on the bottom surface inside the recess, and the electrodes on the upper surface of the optical semiconductor chip 3 and the conductor pattern are electrically connected. After the separate conductive pattern 2 is electrically connected with the gold wire 4, the inside of the recess of the package 1 is filled with the light-transmissive sealing resin 5 to be formed. In this type of optical semiconductor device, one end of the conductor pattern 2 is guided to the back surface of the package 1, and the conductor pattern 2 portion on the back surface is soldered and mounted on a printed circuit board or the like.
【0003】[0003]
【発明が解決しようとする課題】上記のようにパッケー
ジ1の裏面が平坦のままでは、プリント基板等への実装
時に、パッケージ1の裏面とプリント基板等の間に隙間
が全くないため、半田ペーストが裏面に完全に押し潰さ
れ、広範囲に広がり、半田ペーストにより電極間がショ
ートしたり、半田ペーストのキュアの際の発生ガスによ
り、パッケージ1が持ち上げられてしまったりするとい
う問題があった。そして、電極間が狭くなればなるほ
ど、電極間のショートの懸念が高まり、ファインピッチ
化(狭ピッチ化)に適さないという問題があった。本発
明は上記の問題を解決することを目的とする。When the back surface of the package 1 remains flat as described above, there is no gap between the back surface of the package 1 and the printed board or the like during mounting on the printed board or the like. However, there is a problem that the package 1 is completely crushed on the back surface and spreads over a wide area, the electrodes are short-circuited by the solder paste, and the package 1 is lifted due to the gas generated when the solder paste is cured. Then, as the distance between the electrodes becomes narrower, there is a concern that a short circuit between the electrodes may occur, and there is a problem that it is not suitable for a fine pitch (narrow pitch). The present invention aims to solve the above problems.
【0004】[0004]
【課題を解決するための手段】本発明の光半導体装置
は、基板に実装する際に基板に装着される面と基板との
間に隙間ができるように基板に装着される側の面に複数
個の突起部を設け、光半導体チップの各電極に接続され
る導体パターンを上記突起部のいずれかの表面にまで導
き、突起部表面を覆う導体パターンをプリント基板等の
導体に半田付けして実装することとし、半田ペーストが
押し潰されて基板上の不要な領域に広がらない構造とし
たものである。An optical semiconductor device of the present invention has a plurality of optical semiconductor devices mounted on a substrate so that a gap is provided between the substrate mounted surface and the substrate mounted surface. Providing individual protrusions, guide the conductor pattern connected to each electrode of the optical semiconductor chip to any surface of the protrusion, and solder the conductor pattern covering the surface of the protrusion to a conductor such as a printed circuit board. It is mounted so that the solder paste is not crushed and spreads to unnecessary areas on the substrate.
【0005】図1は本発明の一実施例を示す説明図で、
図1(a)は断面構造を、図1(b)は裏面構造を示
す。図において1,2,3,4,5は図5の同一符号と
同一又は相当するものを示し、6はパッケージ1の裏面
に設けられた半球状の突起部である。FIG. 1 is an explanatory view showing an embodiment of the present invention.
FIG. 1A shows a sectional structure and FIG. 1B shows a back surface structure. In the figure, reference numerals 1, 2, 3, 4, and 5 are the same as or correspond to the same reference numerals in FIG. 5, and 6 is a hemispherical protrusion provided on the back surface of the package 1.
【0006】パッケージ1の裏面の四隅にそれぞれ半球
状の突起部6が設けられ、2個の電極を備えた光半導体
チップ3が搭載され、光半導体チップ3の各電極に接続
された導体パターン2がそれぞれ凹部内部の底面上から
突起部6の表面に達するように配設されている例であ
る。半球状の突起部6表面を覆う導体パターン2をプリ
ント基板等に半田付けする際、図2に示すように、半田
ペーストが押し潰されて不要な領域に広がることがな
く、確実に付着される。図において7はプリント基板、
8は半田ペーストである。Hemispherical projections 6 are provided on the four corners of the back surface of the package 1, an optical semiconductor chip 3 having two electrodes is mounted, and a conductor pattern 2 connected to each electrode of the optical semiconductor chip 3 is mounted. Are arranged so as to reach the surface of the protrusion 6 from the bottom surface inside the recess. When the conductor pattern 2 covering the surface of the hemispherical protrusion 6 is soldered to a printed circuit board or the like, as shown in FIG. 2, the solder paste is securely attached without being crushed and spread to an unnecessary area. .. In the figure, 7 is a printed circuit board,
8 is a solder paste.
【0007】突起部6が上記のような形状の場合、実装
時にパッケージ1の姿勢を安定に保つためには、突起部
6は少なくとも3個必要であり、搭載光半導体チップの
電極が2個の場合、表面に電極導出用導体パターン2を
設ける必要のない突起部6ができる。この場合、図1
(b)に示すようにこれら突起部6を覆う導体パターン
を設けておき、全ての突起部を半田付けする方法を採る
と、より確実な装着が得られる。When the projecting portions 6 have the above-mentioned shape, at least three projecting portions 6 are required to keep the posture of the package 1 stable at the time of mounting, and the number of electrodes of the mounted optical semiconductor chip is two. In this case, the protruding portion 6 that does not need to be provided with the electrode leading conductor pattern 2 is formed on the surface. In this case,
As shown in (b), if a conductor pattern covering these protrusions 6 is provided and all the protrusions are soldered, more reliable mounting can be obtained.
【0008】従来、この種の光半導体装置は、裏面をプ
リント基板等に装着し、基板上方の空間のみを動作対象
とする実装方法が採られてきたが、基板下方の空間を動
作対象とする構成とした方が都合がよい場合がある。こ
の場合、基板の光半導体装置の動作領域に対応する部分
を開口し、パッケージの凹部の周りの側壁部上面を基板
に装着して実装する方法を採ればよい。図3はパッケー
ジの凹部の周りの側壁部上面を基板に装着して実装する
本発明の一実施例を示す説明図で、図3(a)は断面と
凹部内部の構造を、図3(b)は実装状態を示す。図に
おいて1,2,3,4,5,7,8は図1及び図2の同
一符号と同一又は相当するものを示し、6aはパッケー
ジ1の凹部の周りの側壁上面に設けられた帯状の突起部
である。光半導体チップ3の各電極に接続された導体パ
ターン2はそれぞれ対向する両側壁上面に設けられた突
起部6a表面を覆う状態に配設されていて、この突起部
6aを覆う導体パターン2がプリント基板7等の導体に
半田付けされて実装される。突起部6aが上記のような
形状の場合は、2個の突起部6aによって実装の際のパ
ッケージ1の姿勢が十分安定に保たれる。そして、図2
に示すように、半田ペースト8が基板7上に不要な領域
に広がることなく、確実に半田付けされる。Conventionally, in this type of optical semiconductor device, a mounting method has been adopted in which the back surface is mounted on a printed circuit board or the like and only the space above the board is operated. However, the space below the board is operated. It may be more convenient to have a configuration. In this case, a method may be adopted in which a portion of the substrate corresponding to the operation region of the optical semiconductor device is opened, and the upper surface of the side wall portion around the recess of the package is mounted on the substrate. FIG. 3 is an explanatory view showing an embodiment of the present invention in which the upper surface of the side wall portion around the recess of the package is mounted on the substrate and mounted. FIG. 3 (a) shows the cross section and the structure inside the recess, and FIG. ) Indicates the mounting state. In the figure, reference numerals 1, 2, 3, 4, 5, 7, and 8 indicate the same or corresponding parts with the same reference numerals in FIGS. 1 and 2, and 6a represents a strip-shaped strip provided on the upper surface of the side wall around the recess of the package 1. It is a protrusion. The conductor patterns 2 connected to the respective electrodes of the optical semiconductor chip 3 are arranged so as to cover the surfaces of the protrusions 6a provided on the upper surfaces of the opposing side walls, and the conductor pattern 2 covering the protrusions 6a is printed. It is mounted by being soldered to a conductor such as the board 7. When the protrusion 6a has the above-described shape, the posture of the package 1 at the time of mounting is kept sufficiently stable by the two protrusions 6a. And FIG.
As shown in FIG. 3, the solder paste 8 is reliably soldered without spreading on an unnecessary region on the substrate 7.
【0009】上記のような実装方法が採られる場合は、
基板7とパッケージ1の装着する側の面との間に間隔を
とる必要がなく、図4(a),(b)に示すように、突
起部6bが基板7に設けられた穴9に挿し込まれて半田
付けされる実装方法によってもよい。この場合は、突起
部6bは帯状にする必要がなく、又、2つの突起部6b
を異なる形状にして、実装の際方向性を間違えることの
ない構造にすることもできる。When the mounting method as described above is adopted,
There is no need to provide a space between the board 7 and the surface on which the package 1 is mounted, and the protrusion 6b is inserted into the hole 9 provided in the board 7 as shown in FIGS. 4 (a) and 4 (b). The mounting method may be such that it is embedded and soldered. In this case, the protrusion 6b does not need to have a strip shape, and the two protrusions 6b
It is also possible to adopt a different shape to make a structure that does not confuse the directionality during mounting.
【0010】[0010]
【発明の効果】以上説明したように、本発明によれば、
電極間の間隔を狭くすることが可能となり、かつ、安定
した半田付けが可能になり、また、動作方向をプリント
基板等の下方に向けて容易に実装できるようになる。ま
た、突起部の形状を変えて、実装の際の方向性の間違い
を防止する効果もある。As described above, according to the present invention,
This makes it possible to reduce the distance between the electrodes, enable stable soldering, and facilitate the mounting so that the operation direction is directed downwardly on the printed circuit board or the like. In addition, the shape of the protrusion is changed to prevent an error in directionality during mounting.
【図1】本発明の一実施例を示す説明図である。FIG. 1 is an explanatory diagram showing an embodiment of the present invention.
【図2】図1に示す実施例の突起部の効果を示す説明図
である。FIG. 2 is an explanatory diagram showing an effect of a protrusion of the embodiment shown in FIG.
【図3】本発明の他の実施例を示す説明図である。FIG. 3 is an explanatory view showing another embodiment of the present invention.
【図4】本発明のその他の実施例を示す説明図である。FIG. 4 is an explanatory diagram showing another embodiment of the present invention.
【図5】従来のこの種の光半導体装置の一例の構造を示
す説明図である。FIG. 5 is an explanatory diagram showing the structure of an example of a conventional optical semiconductor device of this type.
1 プラスチックパッケージ 2 導体パターン 3 光半導体チップ 4 金線 5 光透過性封止樹脂 6 突起部 7 プリント基板 8 半田ペースト 9 穴 1 Plastic Package 2 Conductor Pattern 3 Optical Semiconductor Chip 4 Gold Wire 5 Light Transmissive Sealing Resin 6 Projection 7 Printed Circuit Board 8 Solder Paste 9 Hole
Claims (1)
ケージの上記凹部内部の底面上に光半導体チップが搭載
され、該光半導体チップの各電極がそれぞれ該プラスチ
ックパッケージ表面に設けられた上記凹部内部の底面上
から該プラスチックパッケージの外部表面に達する導体
パターンに接続された後、上記凹部内部に光透過性封止
樹脂が充填されてなる光半導体装置において、 基板に実装する際に基板に装着される面に複数個の突起
部が設けられ、光半導体チップの各電極に接続された導
体パターンが上記突起部の表面にまで導かれ、導体パタ
ーンを基板の導体部に半田付けされることを特徴とする
光半導体装置。1. An optical semiconductor chip is mounted on the bottom surface of the inside of the recess of a plastic package having a recess at the center, and each electrode of the optical semiconductor chip is provided inside the recess provided on the surface of the plastic package. An optical semiconductor device in which a light-transmissive sealing resin is filled inside the recess after being connected to a conductor pattern reaching from the bottom surface to the outer surface of the plastic package, which is mounted on the substrate when mounting on the substrate. A plurality of protrusions are provided on the surface, the conductor pattern connected to each electrode of the optical semiconductor chip is guided to the surface of the protrusion, and the conductor pattern is soldered to the conductor portion of the substrate. Optical semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4038401A JPH05218509A (en) | 1992-01-30 | 1992-01-30 | Optical semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4038401A JPH05218509A (en) | 1992-01-30 | 1992-01-30 | Optical semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05218509A true JPH05218509A (en) | 1993-08-27 |
Family
ID=12524275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4038401A Pending JPH05218509A (en) | 1992-01-30 | 1992-01-30 | Optical semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05218509A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270903A (en) * | 2001-03-08 | 2002-09-20 | Rohm Co Ltd | Back emission chip-type light emitting device |
JP2002305346A (en) * | 2001-04-05 | 2002-10-18 | Hamamatsu Photonics Kk | Semiconductor laser device and manufacturing method therefor |
US6856017B2 (en) * | 1995-11-08 | 2005-02-15 | Fujitsu Limited | Device having resin package and method of producing the same |
EP1717871A2 (en) * | 2005-04-15 | 2006-11-02 | Osram Opto Semiconductors GmbH | Optoelectronic surface-mountable component |
US7737462B2 (en) | 2003-02-28 | 2010-06-15 | Citizen Electronics Co., Ltd | Light emitting diode and light emitting diode device including the light emitting diode element and method for manufacturing the light emitting diode |
KR100985668B1 (en) * | 2008-06-20 | 2010-10-05 | 서울반도체 주식회사 | Light emitting device |
JP2020096154A (en) * | 2018-09-26 | 2020-06-18 | 日亜化学工業株式会社 | Manufacturing method of light emitting device and light emitting device |
-
1992
- 1992-01-30 JP JP4038401A patent/JPH05218509A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856017B2 (en) * | 1995-11-08 | 2005-02-15 | Fujitsu Limited | Device having resin package and method of producing the same |
US7144754B2 (en) | 1995-11-08 | 2006-12-05 | Fujitsu Limited | Device having resin package and method of producing the same |
JP2002270903A (en) * | 2001-03-08 | 2002-09-20 | Rohm Co Ltd | Back emission chip-type light emitting device |
JP2002305346A (en) * | 2001-04-05 | 2002-10-18 | Hamamatsu Photonics Kk | Semiconductor laser device and manufacturing method therefor |
US7737462B2 (en) | 2003-02-28 | 2010-06-15 | Citizen Electronics Co., Ltd | Light emitting diode and light emitting diode device including the light emitting diode element and method for manufacturing the light emitting diode |
US7745835B2 (en) | 2003-02-28 | 2010-06-29 | Citizen Electronics Co., Ltd. | Light emitting diode and light emitting diode device including the light emitting diode element and method for manufacturing the light emitting diode |
EP1717871A2 (en) * | 2005-04-15 | 2006-11-02 | Osram Opto Semiconductors GmbH | Optoelectronic surface-mountable component |
EP1717871A3 (en) * | 2005-04-15 | 2008-11-19 | OSRAM Opto Semiconductors GmbH | Optoelectronic surface-mountable component |
KR100985668B1 (en) * | 2008-06-20 | 2010-10-05 | 서울반도체 주식회사 | Light emitting device |
JP2020096154A (en) * | 2018-09-26 | 2020-06-18 | 日亜化学工業株式会社 | Manufacturing method of light emitting device and light emitting device |
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