JPH05218428A - Thin film semiconductor element, thin film semiconductor device, and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Structure] An n-type impurity having a concentration distribution that exponentially decreases in the depth direction from the surface is introduced into the entire surface of the semiconductor layer 30, and the source electrode 15 and the drain of the semiconductor layer 30 are included. Into the channel region which is not in contact with the electrode 14, p-type impurities having a concentration distribution that also decreases exponentially in the depth direction from the surface are introduced to compensate for the n-type impurities described above. The drain electrode 14 is electrically separated from the drain electrode 14. [Effect] Since the etching step, which was required to electrically separate the source electrode 15 and the drain electrode 14 from each other, is not required, the semiconductor layer 30 can be thinned and at the same time the conventional semiconductor layer 30 can be thinned. Then, there is no unavoidable increase in the number of Photomax, so that the manufacturing cost can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor element, a thin film semiconductor device constructed using the same, and a method of manufacturing a thin film semiconductor element.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs) formed on an insulating substrate such as glass have been applied to active matrix liquid crystal flat panel displays and line image sensors for facsimiles. , Is being developed in various fields.

In these applications, amorphous Si is currently easy to form in large areas at low temperatures.
A TFT using (hereinafter referred to as a-Si) is widely used. 18 and 19 are sectional views of a typical device structure of an a-Si TFT. The structure of FIG. 19 (hereinafter,
Described as NSI type. ) Is a gate after forming the gate electrode 10.
The insulating film 20, the a-Si film 30, and the n-type a-Si film 31 are continuously formed, and after the drain electrode 14 and the source electrode 15 are formed, the n-type a-Si film 31 is etched off to form the drain electrode 14. And the source electrode 15 are electrically separated from each other.

On the other hand, in the structure of FIG. 19 (hereinafter referred to as ISI type), the gate insulating film 2 is formed after the gate electrode 10 is formed.
0, an a-Si film 30, a channel protection insulating film 22 are continuously formed, and the channel protection insulating film 22 is etched.
Type a-Si film 31, drain electrode 14, source electrode 15
The manufacturing process of forming is taken.

[0005]

Each of the above two TFT structures has its own advantages and disadvantages. Since the NSI type does not require a mask for etching the protective insulating film 21 as compared with the ISI type, it has an advantage that the number of masks is one less than that of the ISI type. However, in the NSI type, the n-type a-Si film 31
It is difficult to reduce the film thickness of the a-Si film 30 because the a-Si film 30 is also etched to some extent because an etching selection ratio with the a-Si film 30 cannot be obtained when etching is performed.

Therefore, in the NSI type, the off-resistance of the TFT is apt to decrease due to the photocurrent of the a-Si film.
The decrease in the off-resistance of the TFT has a fatal effect such as a decrease in the contrast ratio of the image and the printing of the image when applied to a display device. Further, since the a-Si film 30 is thick, the time required for the formation is inevitably long and the throughput does not rise.

On the other hand, in the ISI type, since it is not necessary to etch the n-type a-Si film 31, the thickness of the a-Si film 30 can be reduced, but the number of photomasks increases by one as described above, A patterning process of the channel protective film is required. There is a problem that an increase in the number of masks and the number of steps causes an increase in manufacturing cost and a decrease in yield.

The object of the present invention is to solve the above problems,
A structure of a thin film semiconductor element capable of thinning a semiconductor film without increasing the number of masks and the number of steps, a thin film semiconductor device configured using the same, and a method of manufacturing a thin film semiconductor element.

[0009]

In order to solve the above problems, the present invention is characterized by adopting the following means. (1) A first electrode formed on an insulating substrate, a gate insulating film formed on the first electrode, and a gate insulating film formed on the first electrode. A semiconductor film and a second film formed on the semiconductor film and separated from each other.
In a thin film semiconductor device having an electrode and a third electrode, an n-type impurity is introduced into the semiconductor film, and in a region of the semiconductor film that is not in contact with the second electrode and the third electrode. Is a structure in which at least a p-type impurity having a concentration equal to or higher than that of the n-type impurity is introduced.

(2) In the above (1), the concentration distribution of one or both of the n-type and p-type impurities in the semiconductor film or the n-type semiconductor film decreases substantially exponentially from the film surface in the depth direction. Concentration distribution.

(3) In the above (1), the thickness of the semiconductor film and the intrinsic semiconductor film is 20 nm or more and 100
nm or less.

(4) In the above (1), the semiconductor film is made of any one of hydrogenated amorphous Si, hydrogenated amorphous Si-Ge, and hydrogenated amorphous Ge.

(5) First electrodes formed in a matrix on a transparent insulating substrate, a gate insulating film formed on the first electrode, and the gate insulating film interposed between the first electrodes. A plurality of thin film semiconductor elements each including a semiconductor film formed on a first electrode, and second and third electrodes formed on the semiconductor film and separated from each other; A first wire connecting between the first electrodes, a second wire connecting between the second electrodes of the plurality of semiconductor elements, and a transparent wire connected to the third electrode of each of the plurality of semiconductor elements. In a thin film semiconductor device having a pixel electrode composed of an electrode, the plurality of thin film semiconductor elements are replaced by the above (1) to (4).
The thin film semiconductor element described above was used.

(6) In the above (5), the pixel electrode made of a transparent electrode is arranged below the gate insulating film.

(7) First electrodes formed in a matrix on a transparent insulating substrate, a gate insulating film formed on the first electrode, and the gate insulating film interposed between the first electrodes. A plurality of thin film semiconductor elements each including a semiconductor film formed on a first electrode, and a second electrode and a third electrode formed on the semiconductor film so as to be separated from each other, and the plurality of semiconductors. A first wiring connecting between first electrodes of the element, a second wiring connecting between second electrodes of the plurality of semiconductor elements, and a third electrode of each of the plurality of semiconductor elements In the thin film semiconductor device having the photoconductor, the plurality of thin film semiconductor elements are configured by the thin film semiconductor elements described in (1) to (4) above.

(8) A step of forming a first electrode on an insulating substrate, a step of forming an insulating film and a first semiconductor film on the first electrode, and an n-type on the first semiconductor film. A step of introducing an n-type impurity by an ion beam containing impurities and not mass-separated, a step of patterning the first semiconductor film, and a part of the first semiconductor film separated from each other A step of forming a second electrode and a third electrode,
And a step of introducing the p-type impurity into the first semiconductor film by an ion beam containing the p-type impurity without mass separation using the second and third electrodes as a mask. did.

(9) In the method of manufacturing a thin film semiconductor device described in (8), the acceleration energy of ions in the ion beam without mass separation is set to 2500 eV or less.

[0018]

As described in (1) above, the first electrode (gate electrode) formed on the transparent insulating substrate, the gate insulating film formed on the first electrode, and the insulation An NSI type TFT comprising a semiconductor film formed on the first electrode via a film, and a second electrode and a third electrode formed on the semiconductor film so as to be separated from each other. By introducing n-type impurities into the entire film, the second and third electrodes (source,
The drain electrode) is used as a mask to introduce a p-type impurity having a concentration equal to or higher than that of the n-type impurity into a region of the semiconductor film between the source electrode and the drain electrode to enhance resistance. Therefore, the n-type a-
The source and drain electrodes can be electrically separated without etching the Si film. Therefore, in this structure, NSI
The semiconductor film can be thinned even though it is a TFT of the type.

Further, in the above structure, n-type and p-type impurities are introduced into the semiconductor film of the active layer, but in the hydrogenated a-Si film, n-type or p-type is used for controlling conductivity. It is known that when only one type impurity is doped, structural defects in the film increase, and when both n-type and p-type impurities are doped, the increase in defects is suppressed. Since defects in the semiconductor film have an undesired effect such as an increase in the threshold voltage of the TFT and an increase in off current, it is necessary to reduce the defects as much as possible. In the above structure, since both n-type and p-type impurities are introduced, it is possible to prevent an increase in defects. However, if impurities are excessively doped, a composite defect of an n-type impurity and a p-type impurity is generated and the device characteristics are deteriorated. On the other hand, in order to maintain good contact between the source / drain electrode and the semiconductor film, the surface layer of the semiconductor film, which is in contact with the source / drain electrode, should be doped with impurities of a certain amount or more.
Must be enabled.

In order to satisfy the above two requirements, a steep concentration distribution that exponentially decreases from the surface in the depth direction as in (2) above, and a semiconductor as in (3) above is used. The film thickness may be in the range of 20 to 100 nm. By doing so, a sufficient concentration of impurities is present in the contact portion with the electrode, and a concentration such that the above-mentioned compound defects are not formed near the interface between the semiconductor film on which carriers travel and the gate insulating film. Since it is possible to make only the impurities described above exist, good device characteristics can be realized.

Further, as in the above (5), the TFT having the above structure is formed in a matrix on the transparent insulating substrate, and the first wiring for connecting between the first electrodes of the TFT and the second wiring. By configuring the TFT active matrix for the liquid crystal image display device by the second wiring connecting between the electrodes of and the pixel electrode formed of the transparent electrode connected to the third electrode of each of the plurality of semiconductor elements. Since the off resistance of the TFT can be increased, a high quality image can be obtained. In addition, without increasing the number of photomasks, the TFT
Since the semiconductor layer can be thinned, the yield can be improved, the time required to form the semiconductor layer can be shortened, and the throughput can be improved, so that the manufacturing cost can be reduced.

Further, the TFT of the present invention is not limited to the TFT active matrix for the liquid crystal image display device described above, and as shown in (7), the pixel electrode formed of a transparent electrode in the TFT active matrix is formed of a-Si or the like. It can be applied to other thin film semiconductor devices such as a line image sensor for image reading by replacing the photoconductive material. Also in this case, the manufacturing cost can be reduced and the image can be read with high accuracy for the same reason as described in (5) above.

As will be described later, it is indispensable to use the ion beam without mass separation for the introduction of the impurities from the viewpoint of productivity and device performance. However, such non-mass separation ion beam is used. In particular, when the transparent electrode is irradiated with an ion beam containing H, the transparent electrode surface is reduced and devitrified.
At this time, if the transparent electrode is protected by an insulating film such as SiO _2, such damage of the transparent electrode can be prevented. Therefore, in the thin film semiconductor device having the above structure (5), the above (6)
As described above, by arranging the pixel electrode composed of the transparent electrode in the lower layer of the gate insulating film, the gate insulating film prevents the transparent electrode from being damaged by the ion beam in the step of introducing the p-type impurity. it can.

The structure of the TFT described above is not limited to the most general element using hydrogenated amorphous Si as a semiconductor film, but hydrogenated amorphous Si--Ge, hydrogenated amorphous Ge,
The same can be applied to the element using.

The thin film semiconductor device having the above structure can be realized by adopting the following manufacturing method. After the n-type impurities are introduced into the entire surface of the semiconductor film and the semiconductor film is patterned to form the second and third electrodes (source and drain electrodes) as in the above (8), the second and third electrodes are formed. The structure of (1) above is obtained by the step of introducing the p-type impurity using the electrode of (1) as a mask. Further, when n-type or p-type impurities are introduced into the semiconductor film, the productivity of the impurity introduction step can be dramatically improved by using an ion beam containing ions of these impurities and not subjected to mass separation. ..

Conventionally, in the ion implantation method widely used in the LSI process, a thin ion beam previously mass-separated is extracted with an acceleration energy of 10 keV or more,
Although a method of irradiating the entire surface of the substrate with the ion beam by moving the substrate is adopted, in such a method, when a large-area substrate is used such as an image display device,
It takes a lot of time to irradiate the entire surface of the substrate with the ion beam, which is a serious problem in manufacturing. Further, in the case where the thickness of the semiconductor film is 100 nm or less as in the above (3), it is necessary to lower the acceleration energy of the ions in order to accurately implant the impurities into the semiconductor film. In the ion implantation method (1), when the acceleration energy is lowered, the ion current is lowered and the productivity is further lowered. In addition, it is difficult to realize the special impurity concentration distribution that exponentially decreases in the depth direction as described in (2) above by the conventional ion implantation method.

The above problems can be solved by using a large-diameter ion beam that does not undergo mass separation. That is, by using an ion beam that does not undergo mass separation, a large ion current can be secured even with low acceleration energy. Further, by using a large-diameter ion beam, it is not necessary to scan the substrate, so that processing can be performed in a short time.
Further, by introducing the impurity ions at a low energy of 2500 eV or less as in the above (9), the above (2)
A concentration distribution that decreases exponentially in the depth direction can be easily realized. In such a low energy region,
Since the difference in the range of the ions in the semiconductor film due to the mass of the impurity ions is small, the concentration distributions of the n-type impurities and the p-type impurities having different masses can be made almost the same, so that the impurities of the opposite conductivity type are well compensated. be able to.
Further, by using low energy ions, damage to the semiconductor film due to ion bombardment can be reduced, so that device characteristics are not deteriorated.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are cross-sectional views showing the manufacturing process of the first embodiment of the present invention. Cr is deposited on the glass substrate 1 by the sputtering method and patterned to form the gate electrode 10. Then, silicon nitride (S
iN) film 20 of 400 nm, hydrogenated amorphous silicon (a
-Si: H) film 30 is continuously deposited to a thickness of 60 nm. Next, while maintaining the substrate at a temperature of about 200 ° C., P + and PH extracted from the plasma of phosphine (PH ₃ ) gas
Large-diameter ion beam 5 containing phosphorus (P) such as + and PH ₂ +
0 at an acceleration energy of 1.0 kV is 5 × 10 ¹⁵ (/ c
m ² ), and pattern the a-Si: H film 30 into a predetermined shape.
To learn.

A technique for performing such low energy, non-mass separation type ion implantation is, for example, Japanese Patent Laid-Open No. 2-1.
Japanese Patent Publication No. 99824 discloses an example using a magnetic bucket ion source. Further, Japanese Patent Laid-Open No. 63-234519 discloses an impurity introduction method using a high frequency plasma type ion source. Among them, the magnetic bucket type ion source is 1 k compared to the high frequency plasma type ion source.
Since the ion beam having a large current can be extracted even at a low accelerating voltage of about V or less, the former bucket is used for manufacturing the element of the present invention which requires an ion beam of low energy of 2.5 kV or less. Type ion sources are more advantageous. For example, 5 × 10 at an acceleration energy of 1.0 kV
^The time required to inject ¹⁵ (/ cm ² ) is within 10 s, which is an extremely high throughput.

Next, Mo and Al are successively formed by the sputtering method and patterned to form the source electrode 14 and the drain electrode 15. Next, while maintaining the substrate at a temperature of about 200 ° C., a large-diameter ion beam 51 containing boron (B) extracted from plasma of diborane (B ₂ H ₆ ) gas.
5 × 10 ¹⁵ (/ cm ² ) at an acceleration energy of 1.0 kV
inject. Also in this case, the magnetic bucket ion source can be used as in the above case. Finally, a SiN film is formed as the passivation film 23 to complete the device.

According to this embodiment, in the NSI type TFT having a small number of photomasks, the step of etching the n type semiconductor layer is not necessary, so that the thinning of the semiconductor film of the active layer can be achieved. This can improve the productivity during the formation of the semiconductor film. Further, since it is possible to suppress the decrease in the off resistance of the TFT due to the photocurrent, it is possible to realize a good image quality when a display device is configured using this element.

FIG. 7 shows the depth direction of impurities (FIG. 6) in the a-Si: H film 30 in the channel region of the first embodiment.
A-A ') concentration profile of FIG. Both the implanted phosphorus and boron are 10 ²¹ near the surface of the film.
At a high concentration of (1 / cm ² ) or more, the concentration decreases exponentially in the depth direction, and is 10 near the interface with the gate SiN film 20.
^{It has} a rapid concentration distribution that drops to a concentration of ¹⁸ (1 / cm ² ). Also, the distributions of phosphorus and boron almost overlap. According to the experiments by the inventors, the resistivity of the a-Si: H film implanted with phosphorus and boron is 10 ⁹ (Ωc).
m) and higher values, confirming that both impurities are condensed. Further, since the impurity concentration in the vicinity of the interface with the gate SiN film 20 serving as a carrier accumulation layer is sufficiently low, composite defects of phosphorus and boron are not generated, and good device characteristics can be realized.

When the thickness of the a-Si: H film 30 is 20 nm or less, the gate SiN is obtained even if the acceleration voltage is lowered as much as possible.
The impurity concentration near the interface with the film 20 is 10 ¹⁹ (1 / c
Above m ² ), the characteristics deteriorate due to the formation of complex defects of phosphorus and boron. Therefore, it is desirable that the thickness of the a-Si: H film 30 be 20 nm or more.

FIG. 8 shows the relationship between the acceleration energy of ions at the time of doping and the threshold voltage of the produced TFT. When the acceleration voltage is 2.5 kV or more, the threshold voltage rapidly increases. This is an a-Si: H film 30 by ion bombardment.
It is considered that this is due to damage to the gate SiN film 20. Therefore, the acceleration energy of the ions during doping
Is at least 2.5 kV or less, preferably 1.0 kV or less.

9 to 16 are sectional views showing the manufacturing process of the second embodiment of the present invention. Gate electrode 1 is formed by depositing Al on the glass substrate 1 by sputtering and patterning.
Set to 0. Next, an alumina (Al ₂ O ₃ ) film 21 is formed on the surface and side surfaces of the gate electrode 10 by the anodic oxidation method. Next, an indium-tin oxide film (ITO) having a thickness of 100 nm is deposited by a sputtering method and patterned to form the pixel electrode 13. Then, Si is formed by the plasma CVD method.
N film 20 is 400 nm, a-Si: H film 30 is 60 nm
Are continuously deposited.

[0036] Next, P + drawn from the plasma of phosphine (PH ₃₎ gas, PH +, large diameter ion beam containing phosphorus (P) of the PH ₂ +, etc. - the beam 50 acceleration energy of 1.0 kV - 5 × 10 ¹⁵ (/ cm ² ) is injected. Then a
The -Si: H film 30 is patterned into a predetermined shape, and a part of the SiN film 20 on the pixel electrode 13 is opened. Next, Mo and Al are successively formed by the sputtering method,
Source electrode 14 and drain electrode 15 by patterning
And A large-diameter ion beam 51 containing boron (B) extracted from a plasma of diborane (B ₂ H ₆ ) gas was added to 1.0.
5 × 10 ¹⁵ (/ cm ² ) injection with acceleration energy of kV,
Heat treatment is performed at 250 ° C. to 300 ° C. for 60 minutes to activate the implanted phosphorus and boron. Finally, the passivation film 23
As a result, a SiN film is formed to complete a TFT active matrix substrate for a display device.

In the present embodiment, not only the same effect as in the first embodiment described above is obtained, but since the pixel electrode 13 made of the ITO film is arranged in the lower layer of the SiN film 20, boron (B) is included. When the ion beam 51 is irradiated, the pixel electrode 13 is not directly irradiated with the ion beam, so that it is possible to prevent clouding of the pixel electrode 13 due to H contained in the ion beam.

The thin film semiconductor element of the present invention can be used as a TFT active matrix substrate for a liquid crystal display device as shown in FIG. The drain electrode 14 and the gate electrode 10 are formed in a matrix on the glass substrate, and the TFT 502 is formed near the intersection of the drain electrode 14 and the gate electrode 10.
The pixel electrode 13 made of a TO film is driven. Liquid crystal layer 503
A counter electrode 510 made of an ITO film and a color filter 507 are formed on a glass substrate 508 facing each other with a polarizing plate 505 interposed between the pair of glass substrates 1 and 508. A TFT driving type color liquid crystal display device is configured by adjusting the transmission of light from the light source at the pixel electrode 13 portion. The TFT according to the present invention is
Since the semiconductor layer can be thinned, there is no reduction in off resistance due to photocurrent, and high-quality image display with a high contrast ratio is possible. Further, since the number of photomasks does not increase due to the thinning, it is possible to reduce the manufacturing cost of the active matrix substrate.

Although the TFT active matrix substrate for a display device has been described in the above embodiment, by replacing the pixel electrode 13 of the above with a photoconductor made of an a-Si film or the like, an image reading image is obtained. It can also be used as an element.

[0040]

As described above, according to the present invention,
Since a thin semiconductor layer can be realized without increasing the number of photomasks, a TFT having high off resistance and good characteristics
Can be manufactured at low cost. Further, by using the thin film semiconductor element of the present invention, the performance of the thin film semiconductor device such as a display device can be improved and at the same time the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 7 is a diagram showing an impurity concentration distribution in the AA ′ cross section in FIG. 6.

FIG. 8: Accelerating voltage of ions at the time of implanting impurities and T produced
It is a figure which shows the relationship of the threshold voltage of FT.

FIG. 9 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 17 is a perspective view of a liquid crystal display device configured using the thin film semiconductor element of the present invention.

FIG. 18 is an explanatory diagram of a first conventional technique.

FIG. 19 is an explanatory diagram of a second conventional technique.

[Explanation of symbols]

1 Glass Substrate 10 Gate Electrode 13 Pixel Electrode 14 Drain Electrode 15 Source Electrode 20 SiN Film 21 Al ₂ O ₃ Film 22 Channel Protection Insulation Film 23 Passivation Film 30 a-Si: H Film 31 n-type a- Si: H film 50 Ion beam containing phosphorus 51 Ion beam containing boron 502 TFT 506 Liquid crystal layer 507 Color filter 508 Counter glass substrate 510 Counter electrode 505 Polarizing plate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 8617-4M H01L 21/265 W

Claims (9)

[Claims] 1. A first electrode formed on an insulating substrate,
A gate insulating film formed on the first electrode, a semiconductor film formed on the first electrode via the gate insulating film, and formed on the semiconductor film separately from each other. In a thin film semiconductor device including a second electrode and a third electrode, an n-type impurity is introduced into the semiconductor film, and does not contact the second electrode and the third electrode of the semiconductor film. A p-type impurity having a concentration of at least the same concentration as the n-type impurity is introduced into the region. 2. The thin-film semiconductor device according to claim 1, wherein the n-type and p-type impurities in the semiconductor film have a concentration distribution that decreases substantially exponentially from the film surface in the depth direction. Thin film semiconductor device. 3. The thin film semiconductor element according to claim 1, wherein the thickness of the semiconductor film is 20 nm or more and 100 nm or less. 4. The thin film semiconductor device according to claim 1, wherein the semiconductor film is hydrogenated amorphous Si or hydrogenated amorphous S.
A thin film semiconductor device composed of either i-Ge or hydrogenated amorphous Ge. 5. A first electrode formed in a matrix on a transparent insulating substrate, a gate insulating film formed on the first electrode, and the first electrode via the gate insulating film. A plurality of thin film semiconductor elements including a semiconductor film formed on one electrode, and a second electrode and a third electrode formed on the semiconductor film and separated from each other, and the plurality of semiconductor elements A first wiring connecting the first electrodes of the plurality of semiconductor elements, a second wiring connecting the second electrodes of the plurality of semiconductor elements, and a third electrode of each of the plurality of semiconductor elements. A thin film semiconductor device having a pixel electrode formed of a transparent electrode, wherein the plurality of thin film semiconductor elements are constituted by the thin film semiconductor element according to any one of claims 1 to 4. 6. The thin film semiconductor device according to claim 5, wherein the pixel electrode composed of the transparent electrode is arranged in a lower layer of the gate insulating film. 7. A first electrode formed in a matrix on a transparent insulating substrate, a gate insulating film formed on the first electrode, and the first electrode via the gate insulating film. A plurality of thin film semiconductor elements including a semiconductor film formed on one electrode, and a second electrode and a third electrode formed on the semiconductor film and separated from each other, and the plurality of semiconductor elements A first wiring connecting the first electrodes of the plurality of semiconductor elements, a second wiring connecting the second electrodes of the plurality of semiconductor elements, and a third electrode of each of the plurality of semiconductor elements. A thin film semiconductor device having a photoconductor, wherein the plurality of thin film semiconductor elements are constituted by the thin film semiconductor element according to any one of claims 1 to 4. 8. A step of forming a first electrode on an insulating substrate, a step of forming an insulating film and a first semiconductor film on the first electrode, and an n-type impurity in the first semiconductor film. A step of introducing an n-type impurity with an ion beam containing a metal; a step of patterning the first semiconductor film;
Forming a second electrode and a third electrode separated from each other on a part of the semiconductor film, and using the second and third electrodes as a mask, the first semiconductor film contains a p-type impurity. And a step of introducing a p-type impurity at a concentration equal to or higher than that of the n-type impurity by an ion beam. 9. The method of manufacturing a thin film semiconductor element according to claim 8, wherein the acceleration energy of ions in the ion beam is 2500 eV or less.