JPH09139503A - Reverse stagger type thin film transistor, its manufacture, and liquid crystal display using the it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT(thin film transistor) wherein channel length is reduced, leak current is hard to be generated, and self-alignment is perfect, and shorten the manufacturing process of a TFT without using silicide. SOLUTION: A Ta thin film is formed on a glass substrate 1, and gate electrode 2 is formed by patterning. An insulating film 3 of Ta2 O5 is formed, and three layers of a gate insulating film 4 of Si3 N4 , I-type microcrystal silicon 5 and a channel protecting film 6 of Si3 N4 are laminated in this order by using a plasma CVD equipment. Photoresist 7 is spread on the channel protecting film 6, rear exposure is performed from the gate side by using the gate as a mask, and the photoresist 7 self-aligned with the gate electrode 2 is left. By using the photoresist 7 as a mask, the I-type microcrystal silicon 5 is doped with PH3 ions, and N<+> type microcrystal silicon 8 is formed. After that, source.drain electrodes 9a, 9b are formed, and a reverse stagger type TFT is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverted stagger type thin film transistor (Thin F Thin Film Transistor) mainly used for liquid crystal displays.
The present invention relates to an ilm transistor (TFT), a manufacturing method thereof, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a structure of a thin film transistor 61 which is mainly used in a liquid crystal display and manufactured by a conventional technique. First, the manufacturing process of the thin film transistor 61 will be described with reference to FIG.

The thin film transistor 61 is made of a transparent or electrically insulating substrate 62 such as resin or glass.
A band-shaped gate electrode 63 made of a metal film such as chromium
A gate insulating film 64 of silicon nitride (SiN _x ) formed so as to cover the gate electrode 63, a semiconductor layer 65 made of amorphous silicon, and a channel protection film 6.
6, ohmic contact layers 67 and 68 doped with impurities such as phosphorus, a source electrode 69 and a drain electrode 70 made of metal such as chromium, and a protective layer 71 are laminated in this order.

As described above, the thin film transistor 61 having a structure in which the gate electrode 63 is first formed on the substrate 62 is called an inverted stagger type. On the other hand, although not shown, a thin film transistor having a structure in which a source electrode and a drain electrode are formed on a substrate is called a forward stagger type as opposed to the above-mentioned inverted stagger type.

In the inverted staggered thin film transistor 61, ohmic contact layers 67 and 6 are formed on the semiconductor layer 65.
8 is formed, ohmic contact layers 67 and 6 are formed corresponding to the source electrode 69 and the drain electrode 70.
In order to prevent the semiconductor layer 65 from being etched at the time of etching the channel 72 portion for separating the channel 8, the channel protective film 6 is usually formed on the semiconductor layer 65.
6 is formed.

In this case, the obtained thin film transistor 61
However, since the channel protective film 66 is formed, complete self-alignment is not possible, and it is difficult to shorten the channel length to less than the usual 10 μm.

On the other hand, in order to shorten the channel length, there is also a method of completing the thin film transistor 61 without using the channel protective film 66, for example. However, in that case, the semiconductor layer 65 is etched when the channel 72 is etched.
Therefore, the semiconductor layer 65 needs to be thick. As a result, backside exposure cannot be performed using the gate electrode as a mask, which causes a problem that self-alignment cannot be performed.

In view of this, an inverted staggered thin film transistor, which uses a channel protective film to achieve complete self-alignment and shortens the channel length, is disclosed in Japanese Patent Application Laid-Open No. 63-168052. FIG. 6 is a cross-sectional view showing the manufacturing process of the thin film transistor described in the above publication.
The manufacturing process of the thin film transistor will be described based on FIG.

First, as shown in FIG. 6A, a gate electrode 82 is formed by sputtering a metal such as chromium as a gate metal on an insulating substrate 81 such as glass and patterning it.
Mold into Next, a silicon nitride (SiN _x ) gate insulating film 83, an amorphous silicon film 84, and a silicon oxide (S
A channel protection layer 85 of iO _x ) is laminated in this order by a plasma CVD method, and further, the amorphous silicon film 8 is formed.
4 and the channel protection layer 85 are patterned into an island shape. After that, the photoresist 86 is coated on the surface, and the back surface is exposed from the gate side using the gate as a mask.

After patterning the photoresist 86, the photoresist 86 is used as a mask as shown in FIG.
As shown in (b), the channel protection layer 85 is patterned. Next, using the channel protection layer 85 as a mask, phosphorus as impurity atoms is ion-implanted into the amorphous silicon film 84 to form source / drain regions 87. Subsequently, as shown in FIG. 6C, a metal such as chromium is sputtered as the source / drain electrode metal 88. At this time, the silicide layer 8 is formed between the source / drain electrode metal 88 and the source / drain region 87.
9 (see FIG. 6D) is formed. After that, FIG.
As shown in (d), metal 88 for source / drain electrodes
Is etched to pattern the source / drain electrodes 90 to complete the thin film transistor 91.

[0011]

However, in the above publication, the silicide layer 89 is formed between the source / drain electrode metal 88 and the source / drain region 87 in order to reduce the resistance. In order to form the silicide layer 89, it is necessary to perform annealing at 150 ° C. for 20 minutes, and to devise not to etch the silicide layer 89 when the source / drain electrode metal 88 is etched and patterned. Therefore, there is a problem that the number of manufacturing processes is increased. Furthermore, the silicide layer 89 may be formed on the upper surface or the side surface of the channel protection layer 85, and at that time, a leak occurs and the off current increases. Therefore, when the silicide layer 89 formed on the channel protective layer 85 or the like is etched and removed in order to reduce the off current, the channel protective layer 85 needs to be large so that it can be etched. As a result, the channel length becomes longer, and the number of manufacturing steps increases due to the etching of the silicide layer 89.

The present invention has been made in order to solve the above problems, and an object thereof is to provide a fully self-aligned thin film transistor having a short channel length, a leak current is unlikely to occur, and a silicide. Another object of the present invention is to provide a method of manufacturing a thin film transistor, which has a shortened manufacturing process.

[0013]

In order to solve the above problems, an inverted stagger type thin film transistor according to the present invention is formed so as to cover a gate electrode formed on an insulating substrate and the gate electrode. The first insulating film formed on the first insulating film, the island-shaped semiconductor layer formed on the first insulating film, and the gate electrode formed on the semiconductor layer at least in the same direction as the channel width direction. In the inverted staggered thin film transistor including the second insulating film and the source / drain electrodes, at least a part of the semiconductor layer in the film thickness direction is a microcrystalline semiconductor, and the second insulating film of the semiconductor layer is formed. It is characterized in that a source / drain region containing impurities is provided in the microcrystalline semiconductor portion excluding the region right below.

With the above structure, the gate electrode is formed on the insulating substrate. The first insulating film is formed so as to cover the gate electrode. A semiconductor layer is formed on the first insulating film. At least part of this semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor and has source / drain regions. Source / drain electrodes are formed on the source / drain regions.

The source / drain regions correspond to the regions except directly under the second insulating film, and the source / drain regions are implanted with impurities. The source / drain regions are electrically connected to the source / drain electrodes by the impurity implantation. At least the length of the second insulating film in the channel width direction is substantially the same as and coincides with that of the gate electrode, and is self-aligned with the gate electrode.

As described above, when at least a part of the semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor, the conductivity of the source / drain regions after impurity implantation is higher than that in the conventional case made of an amorphous semiconductor. Become. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In order to solve the above-mentioned problems, an inverted staggered thin film transistor according to a second aspect of the present invention has the structure according to the first aspect, wherein the semiconductor layer includes an amorphous semiconductor layer and a microcrystalline semiconductor layer. Two or more layers, at least 1
It is characterized in that source / drain regions containing an impurity are formed in a portion of the microcrystalline semiconductor layer above the second insulating film except the above layers.

With the above structure, in addition to the effect of the structure of claim 1, the on-state current of the inverted staggered thin film transistor can be remarkably increased as compared with the case where the microcrystalline semiconductor is not laminated with the amorphous semiconductor. it can.

Moreover, when forming the semiconductor layer, for example, after forming the amorphous semiconductor layer, at least one microcrystalline semiconductor layer is laminated on the amorphous semiconductor layer. Since an amorphous semiconductor is formed at a higher speed than a microcrystalline semiconductor, a microcrystalline semiconductor layer is formed alone by stacking an amorphous semiconductor layer and a microcrystalline semiconductor layer as described above. Compared with the case, the time required for film formation can be significantly reduced and the throughput can be improved.

Further, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, it is possible to prevent the lower layer from being reduced by hydrogen plasma during the film formation of the microcrystalline semiconductor layer. In the semiconductor layer, an amorphous semiconductor having a poor film quality at the beginning of film formation can be removed in a portion where a channel is formed, and an amorphous semiconductor having a good film quality can be introduced.

In order to solve the above-mentioned problems, an inverted staggered thin film transistor according to a third aspect of the present invention has the structure according to the first aspect, wherein at least a portion of the semiconductor layer in the film thickness direction is made of silicon germanium SiGe _x (0). ≦ x ≦
1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), silicon oxide Si
It is characterized by being made of a microcrystalline semiconductor of O _x (0 ≦ x ≦ 2).

With the above structure, in addition to the effect of the structure according to claim 1, the microcrystalline semiconductor of silicon carbon SiC _x , silicon nitride Si ₃ N _x , and silicon oxide SiO _x is formed by a conventional non-crystalline semiconductor. Since the band gap is larger than that of a crystalline semiconductor, even if light is irradiated to this thin film transistor, electrons are not excited from the valence band to the conduction band, and thus the off current is less likely to increase. As described above, if the microcrystalline semiconductor is formed on at least a part of the semiconductor layer in the film thickness direction to manufacture a thin film transistor, it can be suitably used for a projection type liquid crystal panel using light of high intensity. In addition, since the band gap of the silicon germanium SiGe _x microcrystalline semiconductor can be controlled to be narrow, _if the microcrystalline semiconductor is formed on at least a part of the semiconductor layer in the film thickness direction to manufacture a thin film transistor, The thin film transistor can be driven at a low voltage.

In order to solve the above-mentioned problems, an inverted staggered thin film transistor according to a fourth aspect of the present invention has a structure according to the second aspect, wherein the semiconductor layer includes an amorphous semiconductor layer and a microcrystalline semiconductor layer. It is a lamination of at least one layer, and at least one microcrystalline semiconductor layer is made of silicon germanium SiG.
e _x (0 ≦ x ≦ 1), silicon carbon SiC _x (0 ≦
x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), and silicon oxide SiO _x (0 ≦ x ≦ 2).

With the above structure, in addition to the function of the second aspect, the microcrystalline semiconductor of silicon carbon SiC _x , silicon nitride Si ₃ N _x , and silicon oxide SiO _x is not formed by the conventional non-crystalline semiconductor formed on the semiconductor layer. Since the band gap is larger than that of a crystalline semiconductor, even if light is irradiated to this thin film transistor, electrons are not excited from the valence band to the conduction band, and thus the off current is less likely to increase. As described above, a thin film transistor is manufactured by forming the above microcrystalline semiconductor in at least one microcrystalline semiconductor layer among semiconductor layers in which two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer are stacked. By doing so, it can be suitably used for a projection type liquid crystal panel using light of high intensity.
In addition, since the band gap of the microcrystalline semiconductor of silicon germanium SiGe _x can be controlled to be narrow,
When the thin film transistor is manufactured by forming the microcrystalline semiconductor on at least one microcrystalline semiconductor layer of a semiconductor layer in which two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer are stacked, a thin film transistor is manufactured. It can be driven at a low voltage.

In order to solve the above problems, a method of manufacturing an inverted stagger type thin film transistor according to the invention of claim 5 is
At least one step of forming a gate electrode on an insulating substrate, a first insulating film so as to cover the gate electrode, and a semiconductor layer or an amorphous semiconductor layer containing a microcrystalline semiconductor at least in part in a film thickness direction; The step of forming a semiconductor layer in which the above-described microcrystalline semiconductor is laminated and a second insulating film, and the step of exposing from the side of the insulating substrate using the gate electrode as a mask
Patterning the photoresist on the insulating film, the step of implanting impurities into at least the microcrystalline semiconductor portion of the semiconductor layer using the patterned photoresist as a mask, and the second insulating film using the photoresist as a mask. , A step of patterning the semiconductor layer into an island shape, and a step of forming a metal film and patterning to form source / drain electrodes electrically connected to the impurity-doped semiconductor region. It is characterized by including and.

With the above structure, the gate electrode is formed on the insulating substrate, and the first insulating film is formed so as to cover the gate electrode. A semiconductor layer is formed on the first insulating film. This semiconductor layer contains a microcrystalline semiconductor at least in a part in the film thickness direction, or is formed by laminating an amorphous semiconductor layer and at least one or more microcrystalline semiconductor layers. A second insulating film and a photoresist are stacked in this order on this semiconductor layer.

The photoresist is patterned from the side of the insulating substrate by backside exposure using the gate electrode as a mask. As a result, the patterned photoresist is obtained by self-alignment with the gate electrode.
Then, using this photoresist as a mask, impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer except the region below the photoresist, and source / drain regions are formed. Then, the second insulating film is patterned using the photoresist as a mask.

Subsequently, the semiconductor layer is patterned into an island shape. After that, a metal film is formed and patterned to form source / drain electrodes. As a result, the source / drain electrodes are electrically connected to the semiconductor region in which the impurities are implanted.

As described above, the second insulating film is self-aligned with the gate electrode, and impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer except directly under the second insulating film to form the source / drain regions. Therefore, the conductivity of the source / drain regions after the impurity implantation can be made higher than in the conventional case where the semiconductor layer is made of an amorphous semiconductor.
For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which has been conventionally required to reduce the resistance.

In particular, when a semiconductor layer in which an amorphous semiconductor layer and at least one microcrystalline semiconductor layer are stacked is formed, the amorphous semiconductor is formed at a faster speed than the microcrystalline semiconductor. As compared with the case where the microcrystalline semiconductor layer is formed alone, the time required for film formation as a whole can be significantly shortened and the throughput can be improved.

In addition, for example, if the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, reduction of the first insulating film by hydrogen plasma at the time of forming the microcrystalline semiconductor layer is prevented. At the same time, in the semiconductor layer, the amorphous semiconductor having a poor film quality at the initial stage of film formation can be deleted in the portion where the channel is formed, and an amorphous semiconductor having a good film quality can be introduced.

In order to solve the above-mentioned problems, a method of manufacturing an inverted stagger type thin film transistor according to a sixth aspect of the present invention,
At least one step of forming a gate electrode on an insulating substrate, a first insulating film so as to cover the gate electrode, and a semiconductor layer or an amorphous semiconductor layer containing a microcrystalline semiconductor at least in part in a film thickness direction; The step of forming a semiconductor layer in which the above-described microcrystalline semiconductor is laminated and a second insulating film, and the step of exposing from the side of the insulating substrate using the gate electrode as a mask
Patterning the photoresist on the insulating film, the step of patterning the second insulating film using the patterned photoresist as a mask, and the photoresist or the second insulating film and the photoresist as a mask. A step of injecting an impurity into at least the microcrystalline semiconductor portion of the semiconductor layer, a step of patterning the semiconductor layer in an island shape, and a step of electrically forming a metal film and patterning the semiconductor region into which the impurity is injected. And a step of forming connected source / drain electrodes.

With the above structure, the gate electrode is formed on the insulating substrate, and the first insulating film is formed so as to cover the gate electrode. A semiconductor layer is formed on the first insulating film. This semiconductor layer contains a microcrystalline semiconductor at least in a part in the film thickness direction, or is formed by laminating an amorphous semiconductor layer and at least one or more microcrystalline semiconductor layers. A second insulating film and a photoresist are stacked in this order on this semiconductor layer.

The photoresist is patterned from the side of the insulating substrate by backside exposure using the gate electrode as a mask. As a result, the patterned photoresist is obtained by self-alignment with the gate electrode.
Then, after patterning the second insulating film using the photoresist as a mask, a semiconductor layer containing a microcrystalline semiconductor at least in a part in the film thickness direction, or an amorphous semiconductor layer and at least one or more microcrystalline semiconductor layers. Impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer formed by stacking and. Then, the semiconductor layer is patterned into an island shape. Then, a metal film is formed and patterned to form source / drain electrodes. As a result, the source / drain electrodes are electrically connected to the semiconductor region in which the impurities are implanted.

As described above, since the impurities are implanted through the portion of the second insulating film that has been removed by patterning, the ion acceleration voltage in the impurity implantation can be reduced and the semiconductor layer accompanying the impurity implantation can be reduced. Damage to the can be reduced.

Impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer except in the region directly below the second insulating film, and the conductivity of the source / drain regions after the impurity implantation is: This is larger than in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In particular, when a semiconductor layer in which an amorphous semiconductor layer and at least one microcrystalline semiconductor layer are stacked is formed, the amorphous semiconductor is formed at a faster speed than the microcrystalline semiconductor. Therefore, as compared with the case where the microcrystalline semiconductor layer is formed alone, the time required for film formation as a whole can be significantly shortened and throughput can be improved.

In addition, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, reduction of the first insulating film due to hydrogen plasma at the time of forming the microcrystalline semiconductor layer is prevented. At the same time, in the semiconductor layer, the amorphous semiconductor having a poor film quality at the initial stage of film formation can be deleted in the portion where the channel is formed, and an amorphous semiconductor having a good film quality can be introduced.

A liquid crystal display device according to a seventh aspect of the present invention is characterized by using the inverted stagger type thin film transistor according to the first aspect in order to solve the above problems.

With the above configuration, the inverted staggered thin film transistor according to claim 1 has an on-current improved by about 1.5 times as compared with a conventional thin film transistor in which an amorphous semiconductor is formed on a semiconductor layer. Can be made. Therefore, when the above-mentioned inverted staggered thin film transistor is adopted in a liquid crystal display, a 10.4 inch VGA (Vide
o The aperture ratio of the Graphics Array is 60% from the conventional 60%
The liquid crystal display can be brightened as well. Also, due to the increase in on-current,
17-inch 1280 x 3 x 102, which was difficult in the past
A liquid crystal display for an engineering workstation having 4 picture elements can be produced.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] FIG. 1 is an embodiment of the present invention and is a cross-sectional view showing a manufacturing process of an inverted stagger type thin film transistor of the present invention used for a liquid crystal display. The manufacturing process will be described in detail below with reference to FIG.

First, as shown in FIG. 1A, a tantalum (Ta) thin film is formed on an electrically insulating glass substrate 1 by sputtering, and then patterned by a normal photolithography technique and dry etching. Then, the gate electrode 2 is formed. Subsequently, with the gate electrode 2 attached, the glass substrate 1 is dipped in an ammonium tartrate solution, anodized by applying a voltage from the outside, and tantalum oxide having a film thickness of about 300 nm is formed so as to cover the gate electrode 2. The (Ta ₂ O ₅ ) insulating film 3 is formed.

Next, a gate insulating film 4 of silicon nitride (Si ₃ N ₄ ) is used as a first insulating film, i-type microcrystalline silicon (μc-Si) 5 is used as a microcrystalline semiconductor, and nitride is used as a second insulating film. Plasma C having three layers of the channel protection film 6 of silicon (Si ₃ N ₄ ) having three in-line reaction chambers
By the VD device, the following layers are stacked in this order.

First, in the first reaction chamber, the substrate temperature 3
Silane (SiH ₄ ) 130 sccm and nitrogen (N ₂ ) under the conditions of 50 ° C., pressure 130 Pa, and RF power 1000 W.
2500 sccm and 300 nm thick Si ₃
A gate insulating film 4 of N ₄ is formed.

Next, in the second reaction chamber, the substrate temperature 3
Silane (SiH ₄ ) 30 sccm and hydrogen (H ₂ ) 3 under the conditions of 00 ° C., pressure 110 Pa, and RF power 250 W.
The i-type microcrystalline silicon 5 having a film thickness of 50 nm is formed by using 000 sccm. By the way, the film forming rate at this time is about 2 nm / min, and the conductivity is 3.0 × 10 ⁻⁸ / Ωcm.
It is.

Then, in the third reaction chamber, silane (SiH ₄ ) 130 sccm and nitrogen (N ₂ ) 2500 sccm were used under the conditions of substrate temperature of 300 ° C., pressure of 130 Pa and RF power of 1000 W, and a film thickness of 250 nm.
The Si ₃ N ₄ channel protective film 6 is formed.

Next, a photoresist 7 (see FIG. 1B) is applied on the channel protection film 6, and a portion other than islands is exposed from the resist side using a photomask to remove the photoresist 7. . After that, this time, back surface exposure is performed from the gate side using the gate as a mask, and as shown in FIG. 1B, at least the channel width direction and the gate electrode 2 are almost the same and coincide with each other on the channel protective film 6, that is, the gate. The photoresist 7 self-aligned with the electrode 2 is left.

Next, using the photoresist 7 as a mask, an ion doping apparatus is used to apply PH ₃ from above the channel protective film 6 to the i-type microcrystalline silicon 5 excluding the region in the thickness direction below the photoresist 7. Is ion-doped. Here, the energy of the ions to be doped is 100 keV, and the dose is 1.0 × 10 ¹⁶ ions / cm 2.
² As a result, n + type microcrystalline silicon 8 is formed.

Subsequently, as shown in FIG. 1C, the channel protection film 6 is etched using the photoresist 7 as a mask. After that, CF ₄ was added at 280 sccm and O ₂ was added.
Under conditions of 120 sccm and RF power of 500 W, the n + type microcrystalline silicon 8 of the semiconductor layer is dry-etched into an island shape to form the source / drain regions 8a and 8b.
As a result, the island-shaped channel protection film 6 and the source / drain regions 8a and 8b are obtained by self-alignment with the gate electrode 2.

Next, titanium (Ti) is formed to a thickness of about 300 nm by a sputtering method and patterned to form a source electrode 9a and a drain electrode 9b.

Thereafter, indium oxide (ITO) containing 5% tin (Sn) was used as a target, and sputtering was performed in an oxygen atmosphere to form indium oxide (ITO) of about 70 nm and patterning was performed. As shown in FIG. 1D, the source protective film 1
0 and the pixel electrode 11 are formed.

Finally, the substrate temperature is 250 ° C. and the pressure is 110P.
a, silane (Si
H ₄ ) 150 sccm, ammonia (NH ₃ ) 200 s
A thin film transistor 13 is completed by forming a protective film 12 of Si ₃ N ₄ by plasma CVD using ccm and 2000 sccm of nitrogen (N ₂ ) and patterning.

Although not shown, a glass substrate having a color filter and a black matrix and an ITO electrode formed thereon is bonded to the substrate on the side of the thin film transistor 13 of the liquid crystal display, and the glass substrate is bonded to the substrate. Inject liquid crystal. After that, by attaching polarizing plates on both sides and attaching a backlight, a liquid crystal display is completed.

The thin film transistor 13 shown in FIG.
When the characteristics are measured under this condition, the channel length is 5μ.
m, and the channel width is 15 μm. Regarding the electrical characteristics, the on-current generated when a gate voltage of 10 V and a source-drain voltage of 10 V is applied is 0.9 ×.
It is 10 ⁻⁶ A or more. This is 1.2 times or more the value when amorphous silicon is used for the semiconductor layer. In addition, a gate voltage of -15 V and a source-drain voltage of 10
The off current generated when V is applied is 1.0 × 10
^-12 A or less, most of which is about 1.0 × 10 ^-13 A.

Whether or not microcrystalline silicon is formed as the semiconductor layer can be determined by measuring the conductivity. It was confirmed by transmission electron diffraction that the crystallized when the conductivity was 5.0 × 10 ⁻¹⁰ / Ωcm or more.

Therefore, one of the important conditions for achieving the above-mentioned conductivity as well as for microcrystallization is the hydrogen dilution rate H.
₂ / SiH ₄ . For example, if the hydrogen dilution ratio is 40 or more, i-type microcrystalline silicon having a conductivity of 5.0 × 10 ⁻¹⁰ / Ωcm or more can be obtained. Further, for example, the substrate temperature is 300 ° C., the pressure is 110 Pa, and the RF power is 4
Silane (SiH ₄ ) 15 sccm and hydrogen (H ₂ ) 3000 sc with hydrogen dilution ratio of 200 or more under the condition of 50 W
When cm is used, i-type microcrystalline silicon having a conductivity of 2.0 × 10 ⁻⁷ / Ωcm can be obtained. Thus, it can be said that the higher the hydrogen dilution rate and the higher the RF power, the higher the conductivity can be obtained, and the more easily the crystallize.

With the above structure, when at least a part of the semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor, the conductivity of the source / drain regions 8a and 8b after the impurity implantation is as follows.
It is larger than the conventional case made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

[Embodiment 2] FIG. 2 is a cross-sectional view showing a manufacturing process of a thin film transistor, which is another embodiment of the present invention. The details will be described below with reference to FIG.

First, the steps until the photoresist 27 is formed on the channel protection film 26 as the second insulating film so as to be self-aligned with the gate electrode, are exactly the same as those in the first embodiment. Next, as shown in FIG. 2A, before ion-doping the i-type microcrystalline silicon 25, 280 scc of CF ₄ is used with the photoresist 27 as a mask.
Under the conditions of m, H ₂ of 120 sccm and RF power of 500 W, the channel protective film 26 is first dry-etched to remove the channel protective film 26 except under the photoresist 27.

Next, an ion doping apparatus is used with the remaining two layers of the channel protection film 26 and the photoresist 27 directly below the photoresist 27 as masks.
The i-type microcrystalline silicon 25 except under the channel protective film 26 is ion-doped with PH ₃ . Here, as described above, since the channel protective film 26 other than directly under the photoresist 27 is first etched and removed, the acceleration voltage of the ions to be doped is lowered in order to reduce the damage to the i-type microcrystalline silicon 25. Then, ion doping is performed with the energy of ions being 30 keV. The dose amount of ions at this time is 1.0 × 10 ¹⁶ ions / cm ^2, which is the same as that in the first embodiment. As a result, FIG.
As shown in (b), n + type microcrystalline silicon 28 is formed in the semiconductor layer.

Then, as shown in FIG. 2C, CF ₄
Under conditions of 280 sccm, O ₂ 120 sccm, and RF power of 500 W, the n + type microcrystalline silicon 28 of the semiconductor layer is dry-etched into an island shape to form source / drain regions 28a and 28b. As a result, the island-shaped channel protective film 26 and the source / drain regions 28a, 2
8b is obtained by self-aligning with the gate electrode 22.

Next, titanium (Ti) is formed by a sputtering method and patterned to form a source electrode 29a and a drain electrode 29b.

After that, as shown in FIG. 4D, tin (S
n) Sputtering is performed using indium oxide (ITO) containing 5% as a target, and indium oxide (IT
O) is formed and patterned to form the source protective film 30 and the pixel electrode 31.

Finally, the plasma CVD method is used to form Si ₃
A protective film 32 of N ₄ is formed and patterned to complete the thin film transistor 33.

Regarding the characteristics of the thin film transistor 33 shown in FIG. 2D, the channel length is 5 as in the first embodiment.
μm, and the channel width is 15 μm. Regarding the electrical characteristics, the on-current generated when a gate voltage of 10 V and a source-drain voltage of 10 V is applied is 1.0.
× 10 ⁻⁶ A or more. The off-current generated when a gate voltage of −15 V and a source-drain voltage of 10 V is applied is 1.0 × 10 ⁻¹² A or less.

With the above structure, after patterning the channel protective film 26, the source / source layer is formed on the semiconductor layer at least a part of which in the film thickness direction is made of a microcrystalline semiconductor.
Ion doping is performed on the drain regions 28a and 28b. At this time, since ion doping is performed through the portion of the channel protective film 26 that is removed by patterning, the ion acceleration voltage can be reduced and damage to the semiconductor layer due to ion doping can be reduced.

The conductivity of the source / drain regions 28a and 28b after the ion doping is higher than that in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In the second embodiment, the gate electrode 2
Although two layers of the channel protective film 26 and the photoresist 27 self-aligned with 2 are used as a mask for ion doping, the photoresist 27 may be removed and only the channel protective film 26 may be used as a mask for ion doping. . In this case, since the photoresist 27 is not put in the ion doping apparatus, maintenance is easy. However, since the ion doping apparatus does not perform mass separation, hydrogen is injected into the channel portion to deteriorate the characteristics of the thin film transistor. Therefore, the thickness of the channel protective film 26 is set to 200 nm.
It is necessary to be above.

[Embodiment 3] FIG. 3 shows the relationship between the film thickness and the electrical conductivity of a semiconductor layer during the formation of microcrystalline silicon. The film formation conditions of the microcrystalline silicon at this time are as follows: substrate temperature 300 ° C., pressure 110 Pa, RF power 350 W.
Silane (SiH ₄ ) 15 sccm and hydrogen (H
₂ ) 3000 sccm is used. Even if microcrystalline silicon is formed under the above film forming conditions, the conductivity is as low as 5.0 × 10 ⁻¹² / Ωcm or less at a film thickness of 200 Å or less. This is because the conductivity of amorphous silicon is about 0.3.
Considering that the film thickness is up to 5.0 × 10 ^-11 / Ωcm, it is presumed that the film having a film thickness of 200 Å at the initial stage of film formation is amorphous silicon. However, since the above film forming conditions are not suitable for forming amorphous silicon, the film quality of amorphous silicon at this time is poor. After that, in FIG. 3 again, since the electric conductivity also greatly increases as the film thickness increases, it is conceivable that microcrystalline silicon has grown on the amorphous silicon at the initial stage of film formation.

The film formation rate of microcrystalline silicon is about 0.
The film forming rate is 3 Å / sec, which is slower than the film forming rate of amorphous silicon of about 1.0 Å / sec.

Furthermore, under the film forming conditions of microcrystalline silicon by the plasma CVD method, hydrogen (H ₂ ) is large with respect to silane (SiH ₄ ), and the hydrogen dilution ratio is high. Therefore, the lower layer gate insulating film is subjected to hydrogen plasma treatment, and there is a problem that the lower layer is reduced.

Therefore, in the third embodiment, a method of manufacturing a thin film transistor in which two layers of microcrystalline silicon and amorphous silicon are formed as a semiconductor layer in order to improve the above-mentioned problems will be described with reference to FIG. The details will be described below.

First, a tantalum (Ta) thin film is formed on an electrically insulating glass substrate 41 by sputtering in the same manner as in the first and second embodiments described above, as shown in FIG. 4 (a). Then, patterning is performed to form the gate electrode 42. Subsequently, the glass substrate 41 is dipped in an ammonium tartrate solution and anodized to form a tantalum oxide (Ta ₂ O ₅ ) insulating film 43 so as to cover the gate electrode 42.

Next, a gate insulating film 44 of silicon nitride (Si ₃ N ₄ ) is used as a first insulating film and i is used as a semiconductor layer.
-Type amorphous silicon 45 and i-type microcrystalline silicon 46
Of two layers, and silicon nitride (Si
A channel protection film 47 of ₃ N ₄ ) is laminated in this order as follows by a plasma CVD apparatus having three in-line reaction chambers.

First, in the first reaction chamber,
Similarly, the gate insulating film 44 is formed.

Next, a semiconductor layer is formed in the second reaction chamber. First, silane (SiH ₄ ) 200 scc at a substrate temperature of 350 ° C., a pressure of 80 Pa, and an RF power of 150 W.
m and hydrogen (H ₂ ) 2000 sccm, a film thickness of 3
A 0 nm i-type amorphous silicon 45 is formed. Then, in the same reaction chamber, the substrate temperature is 300 ° C. and the pressure is 110 P.
a, silane (SiH ₄ ) under the condition of RF power 350W
The i-type microcrystalline silicon 46 having a film thickness of 30 nm is formed by using 15 sccm and 3000 sccm of hydrogen (H ₂ ).

Then, in the third reaction chamber, the substrate temperature 300
Under conditions of ℃, pressure 130Pa, RF power 1000W,
Silane (SiH ₄ ) 130 sccm and nitrogen (N ₂ ) 25
00 sccm and Si ₃ N ₄ having a film thickness of 250 nm.
The channel protection film 47 of is formed.

After that, a photoresist 48 is applied on the channel protection film 47, and the back surface is exposed from the gate electrode 42 side, so that the gate electrode 42 and the channel width direction are substantially the same as shown in FIG. 4B. A photoresist 48 that is matched, that is, self-aligned with the gate electrode 42 is formed. Next, using the photoresist 48 as a mask, an ion doping apparatus is used to perform the photoresist 48.
The i-type amorphous silicon 45 and the i-type microcrystalline silicon 46 excluding the region in the thickness direction below is ion-doped with PH ₃ from above the channel protective film 47. here,
The energy of the ions to be doped is 100 keV, and the dose amount is 1.0 × 10 ¹⁶ ions / cm ² . As a result, n + type amorphous silicon 45a and n + type microcrystalline silicon 46a are formed. At this time, in the formed n + type microcrystalline silicon 46a, 5.0 × 10 ⁻¹
A conductivity of / Ωcm is obtained.

Hereinafter, the same procedure as in the first embodiment will be repeated.
As shown in FIG. 4C, the channel protective film 47 is etched by using the photoresist 48 as a mask, and the channel protective film 47 having an island shape is self-aligned with the gate electrode 42 and patterned. After that, two layers of the semiconductor layer, n + type amorphous silicon 45a and n + type microcrystalline silicon 46a, are dry-etched into an island shape,
Source / drain regions 49 and 50 are formed. As a result, the island-shaped channel protection film 47 and the source / drain regions 49 and 50 are obtained by self-alignment with the gate electrode 42.

Next, titanium (Ti) is formed by a sputtering method and patterned to form a source electrode 51 and a drain electrode 52.

Thereafter, as shown in FIG. 4D, tin (S
n) Sputtering is performed using indium oxide (ITO) containing 5% as a target, and indium oxide (IT
O) is formed and patterning is performed to form the source protective film 53 and the pixel electrode 54.

Finally, the Si ₃
A protective film 55 of N ₄ is formed and patterned to complete the thin film transistor 56. After that, a liquid crystal display is manufactured similarly to the first embodiment.

Regarding the electrical characteristics of the thin film transistor 56 shown in FIG. 4D, the on-current when the gate voltage is 10 V and the source-drain voltage is 10 V is
1.2 × 10 ⁻⁶ A, which is the on-current 0.9 × when the amorphous silicon layer is not stacked in Embodiment 1.
It is about 30% higher than that of 10 ^-6 A. Further, the off-current is 1.0 × 10 ⁻¹² A or less when the gate voltage is −15 V and the source-drain voltage is 10 V, which is equal to the values obtained in Embodiments 1 and 2. Is the same.

Regarding the relationship between the amorphous silicon film thickness and the ON current, the amorphous silicon film thickness is 1
At 0 nm, the on-current is 1.1 × 10 ⁻⁶ A,
At this time as well, it can be seen that the on-current has increased by about 20% as compared with the on-current of 0.9 × 10 ⁻⁶ A obtained in the first embodiment. That is, the amorphous silicon film thickness is 10 nm
With the above formation, the effect of increasing the on-current can be obtained.

With the above structure, at the time of forming the semiconductor layer, after forming the i-type amorphous silicon 45, at least one layer of i-type microcrystalline silicon 46 is laminated on the i-type amorphous silicon 45. Since the i-type amorphous silicon 45 is formed at a higher speed than the i-type microcrystalline silicon 46, by stacking the i-type amorphous silicon 45 and the i-type microcrystalline silicon 46 as described above, the i-type microcrystalline silicon 45 is formed. The time required for film formation as a whole can be greatly shortened as compared with the case where the crystalline silicon 46 is formed alone.

Further, in the above structure, since the i-type microcrystalline silicon 46 is formed after the i-type amorphous silicon 45 is formed, the amorphous semiconductor in the initial stage of film formation where the film quality is poor in the portion where the channel is formed in the semiconductor layer. Can be eliminated, and an amorphous semiconductor having a good film quality can be introduced.

In addition, the source / drain regions 49, 50 are formed by implanting impurities into the region of the i-type microcrystalline silicon 46 excluding the region in the thickness direction below the photoresist 48.
Therefore, the conductivity of the source / drain regions 49 and 50 after the impurity implantation is higher than that in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In the third embodiment, it was confirmed from the distribution of phosphorus concentration in the thickness direction of the source / drain regions 49, 50 by simulation that both amorphous silicon and n-type are n-type. However, the effect of the present invention can be obtained if at least the microcrystalline silicon is made n-type.

Further, in the third embodiment, the i-type microcrystalline silicon 46 is formed on the i-type amorphous silicon 45 and ion doping is performed, but as the semiconductor layers, an amorphous semiconductor layer and a microcrystalline semiconductor layer are used. And two or more layers are laminated together, and impurities are added to at least one of the microcrystalline semiconductor layers to form an n + type microcrystalline semiconductor layer,
Of course, the effects of the present invention can be obtained.

In the first to third embodiments described above,
I-type microcrystalline silicon is used for a part of the semiconductor layer in the film thickness direction or one or more laminated microcrystalline semiconductors.
It is not necessarily limited to this. As the above microcrystalline semiconductor, for example, silicon germanium SiGe _x (0 ≦
x ≦ 1), silicon carbon SiC _x (0 ≦ x ≦ 1),
The effect of the present invention can also be obtained by using a microcrystalline semiconductor of silicon nitride Si ₃ N _x (0 ≦ x ≦ 4) or silicon oxide SiO _x (0 ≦ x ≦ 2).

Conventionally, the band gap is about 1.7 eV.
Since amorphous silicon is used for the semiconductor layer, the off current increases because electrons are excited from the valence band to the conduction band when light is irradiated. In order to suppress the off current, the conductivity of the semiconductor layer should be about 1.0 × 10 ⁻⁶ / Ω.
It has been empirically obtained that a lower value of about cm or less is better.

Therefore, silicon carbon SiC _x and silicon nitride Si as described above, in which another element is added to silicon, are used.
_{With 3} N _x and silicon oxide SiO _x , the band gap can be controlled from about 1.7 eV to 2.1 eV. If the band gap is large, even if the thin film transistor is irradiated with light, electrons are not excited from the valence band to the conduction band, and the off current hardly increases. Therefore, if the pixel is small like a projection liquid crystal module that uses strong light and you want to suppress the off-current even if the on-current decreases a little, implant an appropriate amount of impurities in silicon and Alloy (conductivity about 1.0 × 10 ^-6 /
Ωcm or less) is more suitable.

In the case of silicon germanium SiGe _x , the band gap is approximately 1.7 eV to 1.4 eV.
Can be controlled up to. When the band gap is narrowed in this way, it is weak against light, but there is an advantage that the thin film transistor can be driven at a low voltage.

Therefore, as described above, by using the microcrystalline semiconductor in which another element is added to silicon and controlling the band gap, a thin film transistor suitable for the application of the liquid crystal module can be manufactured.

Further, according to the first to third embodiments, since at least a part of the semiconductor layer in the film thickness direction or at least one amorphous semiconductor layer and a microcrystalline semiconductor layer are formed, the amorphous semiconductor is formed. It is possible to improve the on-current by about 1.5 times as compared with the conventional case where the film was formed. Therefore, when the inverted staggered thin film transistor of the present invention is used in a liquid crystal display, a 10.4 inch VGA
The aperture ratio of (Video Graphics Array) can be improved from the conventional 60% to 65%, and the liquid crystal display can be brightened. Also, due to the increase in on-current, the 17-inch 1280 × 3 × which was difficult in the past
A liquid crystal display for an engineering workstation with 1024 picture elements can be made.

[0096]

As described above, in the inverted staggered thin film transistor according to the first aspect of the present invention, at least a part of the semiconductor layer in the film thickness direction is a microcrystalline semiconductor, and the semiconductor layer is directly below the second insulating film. The source / drain regions containing impurities are provided in the microcrystalline semiconductor portion excluding.

Therefore, since the second insulating film is self-aligned with the gate electrode and at least a part of the semiconductor layer in the film thickness direction is made of the microcrystalline semiconductor film, the conductivity of the source / drain regions after the impurity implantation is high. , Which is larger than the conventional case made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

Further, since the step of forming a silicide is unnecessary, the sputtering or etching of the metal film necessary for the step is unnecessary, and the manufacturing process can be simplified as a whole.
In addition, the effect that leakage of silicide can be surely avoided is also obtained.

As described above, the inverted stagger type thin film transistor according to the invention of claim 2 has the following structure.
The semiconductor layer is a stack of two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer, and an impurity is contained in at least one or more layers of the microcrystalline semiconductor layer except a portion right below the second insulating film. This is a structure in which source / drain regions are formed.

Therefore, in addition to the effect of the first aspect, the on-current of the inverted staggered thin film transistor can be remarkably increased as compared with the case where the microcrystalline semiconductor is not laminated with the amorphous semiconductor.

Moreover, when forming the semiconductor layer, for example, after forming the amorphous semiconductor layer, at least one microcrystalline semiconductor layer is stacked on the amorphous semiconductor layer. Since an amorphous semiconductor is formed at a higher speed than a microcrystalline semiconductor, a microcrystalline semiconductor layer is formed alone by stacking an amorphous semiconductor layer and a microcrystalline semiconductor layer as described above. Compared with the case, the time required for film formation can be significantly reduced and the throughput can be improved.

Further, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, it is possible to prevent the lower layer from being reduced by hydrogen plasma during the film formation of the microcrystalline semiconductor layer. In the semiconductor layer, it is possible to remove the amorphous semiconductor having a poor film quality at the initial stage of film formation and introduce an amorphous semiconductor having a good film quality in the portion where the channel is formed.

As described above, the inverted staggered thin film transistor according to the invention of claim 3 has the following structure:
At least a part of the semiconductor layer in the film thickness direction is silicon germanium SiGe _x (0 ≦ x ≦ 1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0
≦ x ≦ 4) and a silicon oxide SiO _x (0 ≦ x ≦ 2) microcrystalline semiconductor.

Therefore, in addition to the effect of the structure of claim 1, silicon carbon SiC _x , silicon nitride Si ₃
N _x, the microcrystalline semiconductor silicon oxide SiO _x, it is possible to control a large band gap, if produced a thin film transistor by forming such a microcrystalline semiconductor in at least the thickness direction of the portion of the semiconductor layer, It can also be suitably used for a projection type liquid crystal panel using light of high intensity. In addition, silicon germanium Si
Since the band gap of a Ge _x microcrystalline semiconductor can be controlled to be narrow, _if the microcrystalline semiconductor is formed on at least a part of the semiconductor layer in the film thickness direction to manufacture a thin film transistor, the above thin film transistor can be operated at a low voltage. It also has the effect of being driven.

As described above, the inverted staggered thin film transistor according to the invention of claim 4 has the following structure.
The semiconductor layer is a stack of two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer, and at least one or more microcrystalline semiconductor layers are silicon germanium SiGe _x (0 ≦ x ≦ 1),
Silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), silicon oxide SiO
_{The structure is made of x} (0 ≦ x ≦ 2) microcrystalline semiconductor.

Therefore, in addition to the effect of the structure of claim 2, silicon carbon SiC _x , silicon nitride Si ₃
N _x, microcrystalline semiconductor silicon oxide SiO _x, since it is possible to control a large band gap, such microcrystalline semiconductor, two or more layers of the amorphous semiconductor layer and a microcrystalline semiconductor layer When a thin film transistor is manufactured by forming at least one microcrystalline semiconductor layer of the semiconductor layer to be formed, a thin film transistor can be suitably used for a projection type liquid crystal panel using light of high intensity. In addition, since the band gap of a silicon germanium SiGe _x microcrystalline semiconductor can be controlled to be narrow, a semiconductor layer formed by stacking two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer is used. If a thin film transistor is manufactured by forming at least one or more microcrystalline semiconductor layers, it is possible to drive the above thin film transistor at a low voltage.

As described above, the method of manufacturing an inverted stagger type thin film transistor according to the present invention comprises the step of forming a gate electrode on an insulating substrate, the first insulating film so as to cover the gate electrode, and A semiconductor layer containing a microcrystalline semiconductor or an amorphous semiconductor layer and a semiconductor layer in which at least one or more microcrystalline semiconductors are stacked at least in part in a film thickness direction;
Forming an insulating film, patterning the photoresist on the second insulating film by exposing from the side of the insulating substrate using the gate electrode as a mask, and the semiconductor using the patterned photoresist as a mask. A step of implanting impurities into at least a microcrystalline semiconductor portion of the layer, a step of patterning the second insulating film using the photoresist as a mask, a step of patterning the semiconductor layer into an island shape, and a metal film being formed. And a step of forming source / drain electrodes electrically connected to the semiconductor region into which the above impurities are implanted by patterning.

Therefore, the second insulating film is self-aligned with the gate electrode, and impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer excluding the region in the thickness direction immediately below the second insulating film. Since the source / drain regions are formed, the conductivity of the source / drain regions after the impurity implantation can be made higher than in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which has been conventionally required to reduce the resistance.

In particular, when a semiconductor layer in which an amorphous semiconductor layer and at least one microcrystalline semiconductor layer are stacked is formed, the amorphous semiconductor is formed at a higher speed than the microcrystalline semiconductor. As compared with the case where the microcrystalline semiconductor layer is formed alone, the time required for film formation as a whole can be significantly shortened and the throughput can be improved.

In addition, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, reduction of the first insulating film by hydrogen plasma at the time of forming the microcrystalline semiconductor layer is prevented. In addition, it is possible to remove the amorphous semiconductor in the initial stage of film formation, which has poor film quality, and to introduce the amorphous semiconductor having good film quality into the portion where the channel is formed in the semiconductor layer. Play.

As described above, in the method for manufacturing an inverted staggered thin film transistor according to the invention of claim 6, the step of forming the gate electrode on the insulating substrate, the first insulating film so as to cover the gate electrode, A semiconductor layer containing a microcrystalline semiconductor or an amorphous semiconductor layer and a semiconductor layer in which at least one or more microcrystalline semiconductors are stacked at least in part in a film thickness direction;
Forming an insulating film, patterning the photoresist on the second insulating film by exposing from the side of the insulating substrate using the gate electrode as a mask, and the second using the patterned photoresist as a mask. A step of patterning an insulating film, the photoresist or the second
By injecting impurities into at least the microcrystalline semiconductor portion of the semiconductor layer using the insulating film and the photoresist as a mask, patterning the semiconductor layer in an island shape, and forming and patterning a metal film. And a step of forming source / drain electrodes electrically connected to the semiconductor region into which the impurities are implanted.

Therefore, since the ion doping is performed through the portion of the second insulating film that is removed by patterning, the ion acceleration voltage can be reduced and the semiconductor layer is damaged by the ion doping. It can be reduced.

Further, the conductivity of the source / drain regions after ion doping is higher than that in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In particular, when a semiconductor layer in which an amorphous semiconductor layer and at least one microcrystalline semiconductor layer are stacked is formed, the amorphous semiconductor is formed at a faster speed than the microcrystalline semiconductor. As compared with the case where the microcrystalline semiconductor layer is formed alone, the time required for film formation as a whole can be significantly shortened and the throughput can be improved.

In addition, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, reduction of the first insulating film by hydrogen plasma at the time of forming the microcrystalline semiconductor layer is prevented. In addition, it is possible to remove the amorphous semiconductor in the initial stage of film formation, which has poor film quality, and to introduce the amorphous semiconductor having good film quality into the portion where the channel is formed in the semiconductor layer. Play.

As described above, the liquid crystal display device according to the seventh aspect of the present invention is configured to use the inverted stagger type thin film transistor according to the first aspect.

Therefore, the inverted staggered thin film transistor according to claim 1 can improve the on-current by about 1.5 times as compared with the conventional thin film transistor in which the amorphous semiconductor is formed in the semiconductor layer. Therefore, when the above inverted staggered thin film transistor is adopted for a liquid crystal display, 10.4 inch VGA (Video Graphics Array)
The aperture ratio can be improved from the conventional 60% to 65%, and the liquid crystal display can be brightened. In addition, the increase in on-current also brings about an effect that it is possible to manufacture a liquid crystal display for an engineering workstation having 17-inch 1280 × 3 × 1024 picture elements, which has been difficult in the past.

[Brief description of the drawings]

1A to 1D are cross-sectional views showing a manufacturing process of an inverted staggered thin film transistor according to an embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views showing a manufacturing process of an inverted staggered thin film transistor according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a film thickness of microcrystalline silicon and conductivity.

4A to 4D are cross-sectional views showing a manufacturing process of an inverted stagger type thin film transistor according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the structure of a conventional inverted staggered thin film transistor.

6A to 6D are cross-sectional views showing a manufacturing process of a conventional inverted staggered thin film transistor.

[Explanation of symbols]

1 glass substrate (insulating substrate) 2 gate electrode 4 silicon nitride (Si ₃ N ₄ ) gate insulating film (first
Insulating film 5 i-type microcrystalline silicon (microcrystalline semiconductor film) 6 Silicon nitride (Si ₃ N ₄ ) channel protective film (second insulating film) 7 photoresist 8a source region 8b drain region 9a source electrode 9b drain electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/78 618B (72) Inventor Masahiro Date 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Osaka Prefecture Within the corporation

Claims (7)

[Claims] 1. A gate electrode formed on an insulating substrate, a first insulating film formed so as to cover the gate electrode, and an island-shaped semiconductor layer formed on the first insulating film. A second insulating film formed on the semiconductor layer and having at least substantially the same channel width direction as the gate electrode and matching the gate electrode;
In an inverted staggered thin film transistor including a source / drain electrode, at least a part of the semiconductor layer in a film thickness direction is a microcrystalline semiconductor, and the microcrystalline semiconductor except a portion right below the second insulating film of the semiconductor layer An inverted staggered thin film transistor having a source / drain region containing an impurity in a portion thereof. 2. The semiconductor layer is a laminate of two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer, and a layer directly under a second insulating film of at least one or more microcrystalline semiconductor layers. The inverted staggered thin film transistor according to claim 1, wherein source / drain regions containing impurities are formed in the removed portion. 3. At least a part of the semiconductor layer in the film thickness direction is made of silicon germanium SiGe _x (0 ≦ x ≦).
1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), silicon oxide Si
The inverted staggered thin film transistor according to claim 1, which is made of a microcrystalline semiconductor of O _x (0 ≦ x ≦ 2). 4. The semiconductor layer is a laminate of two or more layers of an amorphous semiconductor layer and a microcrystalline semiconductor layer, and at least one or more microcrystalline semiconductor layers is formed of silicon germanium SiGe.
_x (0 ≦ x ≦ 1), silicon carbon SiC _x (0 ≦ x
<1), silicon nitride Si ₃ N _x (0 ≤ x ≤ 4), silicon oxide SiO _x (0 ≤ x ≤ 2), which is a microcrystalline semiconductor. . 5. A step of forming a gate electrode on an insulating substrate, a first insulating film so as to cover the gate electrode, and a semiconductor layer or an amorphous semiconductor containing a microcrystalline semiconductor at least in part in the film thickness direction. A layer and a semiconductor layer in which at least one or more microcrystalline semiconductors are stacked, and a step of forming a second insulating film; and exposing from the side of the insulating substrate using the gate electrode as a mask to form a second insulating film Patterning the photoresist, implanting impurities into at least the microcrystalline semiconductor portion of the semiconductor layer using the patterned photoresist as a mask, and patterning the second insulating film using the photoresist as a mask A step of patterning the semiconductor layer into an island shape, and a step of forming a metal film and patterning the semiconductor region into which the impurities are implanted. Inverted staggered thin film transistor manufacturing method that is characterized in that it comprises a step of forming a vapor to the source and drain electrodes connected. 6. A step of forming a gate electrode on an insulating substrate, a first insulating film so as to cover the gate electrode, and a semiconductor layer or an amorphous semiconductor containing a microcrystalline semiconductor at least in part in the film thickness direction. A layer and a semiconductor layer in which at least one or more microcrystalline semiconductors are stacked, and a step of forming a second insulating film; and exposing from the side of the insulating substrate using the gate electrode as a mask to form a second insulating film Patterning the photoresist, patterning the second insulating film using the patterned photoresist as a mask,
A step of implanting an impurity into at least the microcrystalline semiconductor portion of the semiconductor layer using the photoresist or the second insulating film and the photoresist as a mask; a step of patterning the semiconductor layer into an island shape; and a metal film And forming a source / drain electrode electrically connected to the semiconductor region in which the impurity is implanted by forming and patterning the reverse stagger type thin film transistor. 7. A liquid crystal display device using the inverted staggered thin film transistor according to claim 1.