JPH05151106A - Memory card device - Google Patents

Abstract

(57) [Summary] [Object] The present invention makes it possible to write and read data to and from an EEPROM storage area that cannot normally be directly accessed from the outside by supplying a special command from the outside. It is an object of the present invention to provide a memory card device capable of effectively dealing with a failure or a test. In a memory card device having a first area that can be accessed by inputting an address signal from the outside and a second area that is normally inaccessible in a data storage area of an EEPROM 17, By supplying a special command, the second area can be accessed from the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and more particularly to a digital image of an optical image of a photographed subject. The present invention relates to a device suitable for use in an electronic still camera device or the like that converts data and records it in a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized, and the built-in semiconductor memory is required to have a large storage capacity for recording a plurality of digital image data. For example, SR
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and has a high data writing speed and a high data reading speed, but holds the written data. Since it is necessary to store a backup battery for storing in the memory card, the storage capacity is reduced by the amount of the battery storage space and SR
There is a problem that the cost of AM itself is high and causes an economic disadvantage.

Therefore, in recent years, in order to solve the problems of the SRAM, the EEPROM has been attracting attention as a semiconductor memory used for a memory card. This EEP
The ROM has been attracting attention as a recording medium that replaces the magnetic disk, and it does not require a backup battery for holding data and can reduce the cost of the chip itself, which is a unique advantage that SRAM does not have. Therefore, development for use as a memory card has been actively carried out.

Here, FIG. 4 shows a comparison between the length of a memory card using SRAM (SRAM card) and the length of a memory card using EEPROM (EEPROM card). First, regarding the backup battery and the cost of the comparison items 1 and 2, the SRAM card needs the backup battery and the cost is high as described above, while the EEPROM card does not need the backup battery and the cost is high. Also has the advantage that it can be lowered.

Regarding the write speed and read speed of comparison items 3 and 4, random access common to SRAM and EEPROM is performed for writing and reading data to or from a byte or bit arbitrarily designated by an address. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode, the SRAM has both a high writing speed and a high reading speed, and the EEPROM has a low writing speed and a low reading speed. Also, EEPRO
In the page mode, the M simultaneously writes and reads a large amount of data for one page, so the data writing speed and the data reading speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM, which is the SRAM.
Is a mode that does not exist in. That is, the EEPROM
When writing new data to an area where data has already been written, new data cannot be written unless the previously written data is erased. Therefore, when writing data, this erase mode Is to be executed. The erase mode includes a chip erase that erases all the contents stored in the EEPROM at once and a page erase that erases the contents stored in page units.

Also, the write verify of the comparison item 6 is a mode peculiar to the EEPROM and a mode not existing in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the written contents of the ROM and check whether or not they are correctly written, and this is the write verify.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM, and is written.
The written contents of the EEPROM are read and compared with the contents of the buffer memory to determine whether they match. Then, when it is determined as a result of the write verify that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM does not require a backup battery, is low in cost, and is capable of writing and reading data in page units. It has unique advantages not found in SRAM, but on the other hand, it does not store data in the random access mode. There is also a disadvantage that the writing speed and the reading speed are slow and that a mode such as an erase mode and a write verify which is not in the SRAM is required.

Therefore, as the semiconductor memory used for the memory card, the EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, and the problem of needing erase mode and write verify, etc. are solved, and handling equivalent to that of a memory card with built-in SRAM can be performed. As described above, that is, it is important to make various improvements in details so that the card can be used in an SRAM card-like manner.

In this case, the EEP is particularly problematic.
In the ROM, when the number of data rewrites exceeds a certain number, the memory cells are rapidly deteriorated, and a data write failure is likely to occur. That is, since the EEPROM was developed for recording program data and intended to be able to rewrite data when the program version is upgraded, it is possible to support rewriting of data many times. Because it is not designed to.

However, as described above, when the EEPROM is used in place of the conventionally used SRAM as a semiconductor memory for a memory card used in, for example, an electronic still camera device, it goes without saying. Since it is used in such a manner that data is rewritten frequently with respect to the EEPROM, it is inevitable that the rate of occurrence of write defects will increase dramatically. Is becoming

Regarding this write failure, conventionally, it is determined that the write failure occurs when the write verify processing described above is not correctly written even after repeating a predetermined number of times. However, in the past, EEPRO
Even if a write error occurs in part of M, the EEP
Since the entire memory card containing the ROM is treated as a defective product, there is a problem that it is very inefficient and economically disadvantageous.

Therefore, at present, in order to solve the above problems, a memory card as disclosed in, for example, Japanese Patent Application No. 3-200308 is being considered. That is, this memory card has a storage area of the built-in EEPROM,
Dividing into a data area and a relief area, each of which is composed of a plurality of blocks each having a certain capacity (one block is several kbytes), and writing to the defective block in the state where a write failure is detected in the block of the data area. The data that could not be recovered is relieved by automatically searching for and writing an empty block in the relief area. At this time, by providing a management table that associates the defective block with the relief block, inconvenience may occur during data reading. It was designed so that it would not occur.

However, as described above, the EEPROM
In the memory card having the relief measure against the writing failure of the above, the writing failure is detected in the block of the data area, and the data that could not be written in the defective block is automatically transferred to the empty block of the saving area. The relieving operation of searching and writing is automatically performed by self-processing inside the memory card. For this reason,
For example, from the outside of the memory card, the internal state of the EEPROM itself, such as in which block of the EEPROM the writing failure has occurred and in which block of the relief area the data requested to be written in this defective block has been rescued, I couldn't grasp it, and E
If you want to know the data recording status inside the EPROM,
It is necessary to disassemble the memory card and directly access the EEPROM, which causes a problem of complicated handling.

[0019]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In a conventional memory card that is intended to be used as an SRAM card using a ROM, there is an EEPROM storage area that cannot be directly accessed from the outside of the memory card, such as a relief area. There is a problem that it is very inconvenient when it is desired to know the data recording status of.

Therefore, the present invention has been made in consideration of the above circumstances, and by supplying a special command from the outside, data can be written even in the storage area of the EEPROM which cannot normally be directly accessed from the outside. It is also an object of the present invention to provide a very good memory card device which can read and read and can effectively deal with a failure or a test.

[0021]

In the memory card device according to the present invention, a first area in the data storage area of the EEPROM which is accessible by inputting an address signal from the outside and a normally inaccessible area. It is intended for those having a second area. Then, by supplying a special command from the outside, the second area can be accessed from the outside.

[0022]

According to the above-mentioned structure, by supplying a special command from the outside, it is possible to write and read the data even to the storage area of the EEPROM, which cannot normally be directly accessed from the outside. Therefore, it becomes possible to effectively deal with a failure or a test.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described in detail below with reference to the drawings. In FIG. 1, 11 is a memory card main body, which is connected to an electronic still camera main body (not shown) via a connector 12 installed at one end thereof. The connector 12 is provided with digital data DA to be written in the memory card body 11 from the electronic still camera body side and address data AD indicating the writing location.
And are supplied. The digital data DA and the address data AD are supplied to the data input / output control circuit 13 via the bus lines D0 to D7.

Also, from the electronic still camera body, to the connector 12, a card enable signal CE which becomes H (high) level when the memory card body 11 is selected.
And an address / data switching signal A / D which becomes L (low) level when the data supplied to the bus lines D0 to D7 is address data AD and becomes H level when the data is digital data DA, and a data write request to an EEPROM described later. The read / write switching signal R / W which becomes L level at the time of and becomes H level at the time of data read request, and the bus clock BCK synchronized with the address data AD
It is being supplied.

These card enable signal CE, address / data switching signal A / D, read / write switching signal R
/ W and the bus clock BCK are also supplied to the data input / output control circuit 13. Further, from the electronic still camera body, a command for requesting data erase to the EEPROM is also supplied to the data input / output control circuit 13 via the connector 12. Further, from the data input / output control circuit 13, when the input of the digital data DA from the electronic still camera main body is permitted, it becomes H level,
Ready / busy switching signal R which becomes L level when input is rejected
DY / BSY is generated.

The digital data DA supplied to the connector 12 is temporarily fetched and recorded in the buffer memory 14 under the control of the data input / output control circuit 13. Digital data D of the buffer memory 14 at this time
The acquisition timing of A is controlled by the address data output from the address generation circuit 15. In addition, the address generation circuit 15 includes a selector 16
The clock data CK selected by is counted, and the address data to the buffer memory 14 is generated. The bus clock BCK and the clock YCK output from the data input / output control circuit 13 are supplied to the selector 16.

Then, when the digital data DA of the buffer memory 14 is fetched, the selector 16 selects the bus clock BCK by the select signal SEL output from the data input / output control circuit 13 and outputs it to the address generation circuit 15 as the clock CK. is doing. Therefore, the digital data DA sent from the electronic still camera body to the connector 12 is stored in the buffer memory 1 according to the address data generated based on the bus clock BCK.
4 will be written.

After that, when the writing of the digital data DA into the buffer memory 14 is completed, the data input / output control circuit 13 controls the select signal SEL, and the clock YCK generated by itself is derived to the address generation circuit 15. The selector 16 is switched as follows. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 15 based on the clock YCK.
The digital data DA is read from 4.

At this time, the data input / output control circuit 13 is
Chip enable signal CEN for EEPROM 17
Also, the write enable signal WE is output and the address data AD is output, and the digital data DA read from the buffer memory 14 is controlled to be written to the EEPROM 17 in page units of 512 bytes, for example. Then, with the digital data DA written in the EEPROM 17, the data input / output control circuit 13
Outputs to the EEPROM 17 the out-enable data OE and the address data AD that has previously specified the writing of data to read the written digital data DA from the EEPROM 17, and the buffer memory 14
Write verify is executed to determine whether or not the data matches the digital data DA recorded in the above.

If the digital data DA read from the EEPROM 17 and the digital data DA recorded in the buffer memory 14 do not match, the data input / output control circuit 13 again outputs the data from the buffer memory 14 to the E memory.
The digital data DA is transferred to and written in the EPROM 17, and this operation is repeated until the digital data DA read from the EEPROM 17 and the digital data DA recorded in the buffer memory 14 completely match, and the digital data DA is written there. Data DA EEPROM 17
Is written to.

In addition, from the electronic still camera body to the EEPR
When an instruction to erase the data recorded in the OM 17 is generated, the data input / output control circuit 13 drives the erasing circuit 18 based on the erasing instruction. This erase circuit 18
On the basis of the control of the data input / output control circuit 13,
By outputting a signal for erasing to the address line and data line of the PROM 17, the EEPROM 17 is electrically chip-erased or page-erased.

Next, the operation of reading the digital data DA from the EEPROM 17 to the outside of the memory card body 11 will be described. First, a read request and a recorded address of data to be read are specified from the electronic still camera body side via the connector 12. Then, the data input / output control circuit 13 sends the chip enable signal CEN and the out enable data O to the EEPROM 17.
E and address data AD are output, and the EEPROM 17
The digital data DA is read in page units from, and the selector 16 is switched so that the clock YCK generated by itself is derived to the address generation circuit 15 and written in the buffer memory 14.

After that, the data input / output control circuit 13 switches the selector 16 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 15, and the bus clock BCK. Based on the address data generated by the address generation circuit 15, the data is read from the buffer memory 14 and led out to the electronic still camera body through the connector 12, and the digital data DA is read there.

Here, FIG. 2 shows the detailed timing of the writing operation of the digital data DA to the EEPROM 17. First, the card enable signal CE is H
When the memory card body 11 is designated as the level,
When the address / data switching signal A / D is at L level, the address data AD is supplied to the bus lines D0 to D7. At this time, the bus clock BC is synchronized with the address data AD.
K is generated and read / write switching signal R /
W is in the L level data write request state, and ready / busy switching signal RDY / BSY is in the H level input enable state.

In this state, the address / data switching signal A / D is inverted to H level, and the bus lines D0 to D7.
When the data of No. changes to digital data DA, D0
512 digital data DA up to D511, that is, one page of digital data DA is input to the data input / output control circuit 13 together with 512 bus clocks BCK and sequentially written in the buffer memory 14. Then, the data input / output control circuit 13 inverts the ready / busy switching signal RDY / BSY to the L level in synchronization with the 512th bus clock BCK, and the input of the electronic still camera body is rejected.

Then, the data input / output control circuit 13 collectively writes the data recorded in the buffer memory 14 to the EEPROM 17 page by page in the input refusal state from the electronic still camera body, and performs the write verify operation. , The digital data DA for one page is recorded in the EEPROM 17. After that, the data input / output control circuit 13 determines the digital data DA for one page.
When it is determined that the data has been completely written in the EEPROM 17, the ready / busy switching signal RDY / BSY is inverted to the H level to enable the input from the electronic still camera body, and the digital data DA of the next page is stored in the buffer memory 14. Works to capture.

Above, the digital data DA is EEPRO
The normal operation mode when writing to the M17 is described. Next, due to a failure, a test, or the like, a storage area of the EEPROM 17, such as a relief area, which cannot be directly accessed from the outside of the memory card body 11, will be described. A so-called test mode for writing the digital data DA will be described.

That is, when the test mode is entered, the card enable signal CE is set to H level as shown in FIG.
While specifying the memory card body 11 as a level,
The address / data switching signal A / D is set to L level to supply 2-byte test mode data TD to the bus lines D0 to D7. At this time, the bus clock BCK is generated in synchronization with the test mode data TD, the read / write switching signal R / W is set to the L level data write request state, and the ready / busy switching signal RDY / BSY is input at the H level. Set to the permit state. Then, as in the normal data write operation, after supplying 3-byte address data AD to the bus lines D0 to D7, the address / data switching signal A / D is inverted to the H level, and the bus lines D0 to D
The data of 7 is converted into digital data DA.

That is, the card enable signal CE is set to H level to specify the memory card body 11, and then the address / data switching signal A / D is inverted to H level to change the data on the bus lines D0 to D7 into digital data DA. In the period up to, a total of five bus clocks BCK, which are two bus clocks BCK synchronized with the 2-byte test mode data TD and three bus clocks BCK synchronized with the 3-byte address data AD, are used for data input / output control. It will be supplied to the circuit 13. Then, in the period from when the card enable signal CE is set to the H level until the address / data switching signal A / D is inverted to the H level,
The five bus clocks BCK are used as the data input / output control circuit 13
Is a special command input state that does not exist in the standard of the memory card using the EEPROM, that is, it is not input in the normal operation mode,
At this time, the data input / output control circuit 13 determines that the test mode is requested.

In this test mode, the data input / output control circuit 13 can directly write the input digital data DA to the address of the EEPROM 17 designated by the address data AD input to the connector 12.

In the above description, the case of writing data in the test mode has been described, but in the case of reading data from the EEPROM 17 in the test mode, FIG.
It can be realized by setting the read / write switching signal R / W to the H level data read request state and setting the ready / busy switching signal RDY / BSY to the L level input refusal state.

Therefore, according to the configuration of the above embodiment, the five bus clocks BCK are set in the period from the time when the card enable signal CE is set to the H level to the time when the address / data switching signal A / D is inverted to the H level. The test mode is entered by supplying a special command, which is not input in the normal operation mode, to the data input / output control circuit 13, and the external mode of the memory card main body 11 is entered in the normal operation mode. Since the data can be written and read even in the storage area of the EEPROM 17 which cannot be directly accessed from, it is possible to effectively deal with a failure or a test.

The present invention is not limited to the above embodiment, but can be variously modified and implemented without departing from the scope of the invention.

[0044]

As described in detail above, according to the present invention,
By supplying a special command from the outside, EEPRO, which normally cannot be directly accessed from the outside
It is possible to provide a very good memory card device that enables data to be written to and read from the M storage area and can effectively deal with a failure or a test.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a timing chart for explaining an operation of a main part of the embodiment.

FIG. 4 is a diagram showing the lengths of an SRAM card and an EEPROM card in comparison.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Data input / output control circuit, 14 ... Buffer memory, 15 ... Address generation circuit, 16 ... Selector, 17 ... EEPROM,
18 ... Erase circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location G11C 16/06 (72) Inventor Kazuo Konishi 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Corporation Video Media Technology Laboratory (72) Inventor Satoshi Sato 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E. Co., Ltd.

Claims (1)

[Claims] 1. A data storage area of an EEPROM,
In a memory card device having a first area accessible by inputting an address signal from the outside and a second area normally inaccessible, by supplying a special command from the outside to the second area The memory card device is characterized in that the area of is accessible from the outside.