JPH0546469A - Memory card - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a memory card device using an EEPROM to improve the data writing speed and the data reading speed as much as possible, and to improve it so that it can be used for SRAM card-like. Has a purpose. [Structure] Digital data DA input through a connector 12 and written in a buffer memory 13 is EEPRO.
It is written in M17 in page units. The header data HD, which is often required to be rewritten in bytes, is E
The data is transferred from the EPROM 17 to the buffer memory 13 in page units, rewritten in bytes in the buffer memory, and then written in the EEPROM 17 in page units. The data transfer with the outside and the write verification of the EEPROM 17 are both performed using the buffer memory 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and more particularly to a digital image of an optical image of a photographed subject. The present invention relates to a device suitable for use in an electronic still camera device or the like that converts data and records it in a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized, and the built-in semiconductor memory is required to have a large storage capacity for recording a plurality of digital image data. For example, SR
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and has a high data writing speed and a high data reading speed, but holds the written data. Since it is necessary to store a backup battery in the memory card for this purpose, the storage capacity is reduced by the amount of the battery storage space and SR
There is a problem that the cost of AM itself is high and causes an economic disadvantage.

Therefore, in order to solve the problems of the SRAM, the EEPROM is now attracting attention as a semiconductor memory used for a memory card. This EEP
The ROM has been attracting attention as a recording medium that replaces the magnetic disk, and it does not require a backup battery for holding data and can reduce the cost of the chip itself, which is a unique advantage that SRAM does not have. Therefore, development for use as a memory card has been actively carried out.

Here, FIG. 2 shows a comparison between the length of a memory card using SRAM (SRAM card) and the length of a memory card using EEPROM (EEPROM card). First, regarding the backup battery and the cost of the comparison items 1 and 2, the SRAM card needs the backup battery and the cost is high as described above, while the EEPROM card does not need the backup battery and the cost is high. Also has the advantage that it can be lowered.

Regarding the write speed and read speed of comparison items 3 and 4, random access common to SRAM and EEPROM is performed for writing and reading data to or from a byte or bit arbitrarily designated by an address. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode,
The SRAM has a high writing speed and a high reading speed, and the EEPROM has a low writing speed and a low reading speed. In addition, EEPROM
In the page mode, since a large amount of data for one page is written and read all at once, the data write speed and the data read speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM, which is the SRAM.
Is a mode that does not exist in. That is, the EEPROM
When writing new data to the area where data has already been written, new data cannot be written unless the previously written data is erased. Therefore, when writing data, this erase mode Is to be executed.

Further, the write verify of the comparison item 6 is also a mode peculiar to the EEPROM and is not present in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the written contents of the ROM and check whether or not they are correctly written, and this is the write verify.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM and written, and then,
The contents written in the EEPROM are read out and compared with the contents in the buffer memory to determine whether they match. Then, when it is determined as a result of the write verify that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM does not require a backup battery, is low in cost, and is capable of writing and reading data in page units. It has unique advantages not found in SRAM, but on the other hand, it does not store data in the random access mode. There is also a disadvantage that the writing speed and the reading speed are slow and that a mode such as an erase mode and a write verify which is not in the SRAM is required.

Therefore, as the semiconductor memory used for the memory card, the EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, the problem of needing erase mode and write verify, etc. can be solved, and it can be handled in the same manner as a memory card with built-in SRAM. As described above, that is, it is important to make various improvements in detail so that it can be used in an SRAM card-like manner.

[0014]

As described above, SRA
Considering the use of the EEPROM for the memory card instead of the M, it is an important problem in practical use to improve the EEPROM card so that it can be used as an SRAM card.

Therefore, the present invention has been made in consideration of the above circumstances, and an EEPROM is used to improve the data writing speed and the data reading speed as much as possible, and the SR
It is an object of the present invention to provide an extremely good memory card device which has been improved so that it can be used in an AM card-like manner.

[0016]

SUMMARY OF THE INVENTION A memory card device according to the present invention has a first data group having a property that a small amount of total data is required and a large amount of writing and reading of data in byte units is required, and a total data amount. However, it is intended to record and input the data including the second data group having a large number of sequential characteristics. And, it has a storage capacity for recording the entire first data group, is capable of high-speed writing and high-speed reading of data, and stores data between the buffer memory for transferring data to and from the outside. An EEPROM for inputting / outputting, having first and second storage areas in which first and second data groups are respectively recorded, and capable of writing / reading data in page units, and this EEPROM All data in the first storage area of the EEPROM is transferred to the buffer memory in a state where the rewriting of the byte data is requested for the recorded first data group, and the byte data is stored in the buffer memory. After rewriting, all data in the buffer memory is EEPRO page by page.
The data written in the EEPROM is compared with the data in the read buffer memory in the state in which the data is transferred from the buffer memory to the EEPROM and written in the control means for writing in the first storage area of M and the data does not match. In this state, the determination means for transferring the data from the buffer memory to the EEPROM again for writing is provided.

[0017]

According to the above configuration, when a rewriting request is made to the first data group having a property that the total data amount is small and the writing and reading of data in byte units are often required, the EEPROM is Read all the first data group from the buffer memory to the buffer memory,
After rewriting data in byte units by random access in 3, all data in the buffer memory 13 is written in the EEPROM again in page units, so that it is not possible to write or read data in byte units. Even if a large capacity EEPROM is used, data can be written and read in byte units easily.

In addition, since data transfer with the outside is always performed via the buffer memory, the data writing speed and the data reading speed are improved, and the memory card can be used like an SRAM card. Also, E
Since the write verify unique to the EPROM is also performed using the buffer memory 13, it can be used as an SRAM card like.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described in detail below with reference to the drawings. In FIG. 1, 11 is a memory card main body, which is connected to an electronic still camera main body (not shown) via a connector 12 installed at one end thereof. The connector 12 is provided with digital data DA to be written in the memory card body 11 from the electronic still camera body side and address data AD indicating the writing location.
And are supplied.

The digital data DA supplied to the connector 12 is once taken in and recorded in the buffer memory 13. At this time, the fetch timing of the digital data DA of the buffer memory 13 is controlled by the address data output from the address generation circuit 14. The address generation circuit 14 also counts the clock CK selected by the selector 15 to generate address data for the buffer memory 13.

Address data A is stored in the selector 15.
A bus clock BCK synchronized with D and a clock YCK output from the data processing control circuit 16 are supplied. Then, when the digital data DA in the buffer memory 13 is fetched, the selector 15 outputs the select signal SEL output from the data processing control circuit 16.
The bus clock BCK is selected by and is derived to the address generation circuit 14 as the clock CK.

The address data AD supplied to the connector 12 is supplied to the data processing control circuit 16,
It is determined whether the header address data HAD or the image address data PAD. That is, the digital data DA output from the electronic still camera main body side includes header data HD which is memory management information such as memory card attribute information, various information unique to each image data, date information, and the number of recordable images. , And image (including audio) data PD corresponding to the subject.

Of these, the header data HD has a small total capacity of about 16 Kbytes, and many of them need to be rewritten on a byte-by-byte basis, such as date information and information about the number of shootable images. have. Then, the buffer memory 13 stores the header data H
It has a storage capacity (16 Kbytes or more) capable of storing all D. The image data PD is the image 1
It has a very large amount of data for one sheet and is sequential in nature.

Then, the digital data DA taken into the buffer memory 13 is read from the buffer memory 13 and written in the EEPROM 17 under the control of the data processing control circuit 16 which will be described later. This EEPRO
M17 has a large storage capacity of 4 Mbits or more, cannot write or erase data in byte units, and can perform batch erase or block unit erase of several Kbytes, and pages of hundreds of bytes. Data can be written and read in units.

In the data processing control circuit 16, the input address data AD is the header address data H.
When it is determined that the AD is detected, the out enable data OE is activated to the EEPROM 17 (for example, H
In addition, the address data AD for designating the entire header data HD storage area of the EEPROM 17 is generated, and the entire header data HD stored in the EEPROM 17 is read in page units.

Next, the data processing control circuit 16 sets the write enable data WE to the active state (for example, H level) for the buffer memory 13 and controls the select signal SEL to generate the clock Y generated by itself.
The selector 15 is switched so that CK is led to the address generation circuit 14. Therefore, all the header data HD read from the EEPROM 17 is written in the buffer memory 13 by the address data generated by the address generation circuit 14 based on the clock YCK.

After that, with all the header data HD written in the buffer memory 13, the data processing control circuit 16 determines, based on the header address data HAD,
The address generation circuit 14 generates the set address data SA that specifies the bytes of the header data HD to be rewritten.
And the address set data AS for setting the set address data SA in the address generation circuit 14 to the address generation circuit 14.

Then, the address generation circuit 14 generates address data from the set address data SA set based on the address set data AS, and outputs it to the buffer memory 13. At this time, the data processing control circuit 16 activates the write enable data WE to the buffer memory 13, so that the contents of the byte designated by the input address data of the buffer memory 13 are transferred via the connector 12. It is rewritten to the new header data HD that has been input.

When the rewriting of the header data HD in bytes is completed in the buffer memory 13, the data processing control circuit 16 causes the clock YCK generated by itself.
Selector 1 so that the
5 and controls the out enable data OE to the buffer memory 13 in the active state. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 14 based on the clock YCK.
The header data HD is sequentially read from 3.

At this time, the data processing control circuit 16 causes the E
The write enable data WE is activated for the EPROM 17, and the address data AD designating the entire header data HD storage area of the EEPROM 17 is generated. Therefore, all the header data HD after the rewriting stored in the buffer memory 13 is
The data is transferred to the ROM 17 and written in the header data HD storage area in page units.

After that, with all the header data HD written in the EEPROM 17, the data processing control circuit 16 activates the out enable data OE to the EEPROM 17 and specifies all the header data HD storage areas. Address data AD is output, the written header data HD is read, and write verification is executed to determine whether the header data HD matches the header data HD recorded in the buffer memory 13.

If the header data HD read from the EEPROM 17 and the header data HD recorded in the buffer memory 13 do not match, the header data HD is read from the buffer memory 13 to the EEPROM 17 again.
Is transferred and written, and this operation is
This is repeated until the header data HD read from M17 and the header data HD recorded in the buffer memory 13 completely match, and the header data HD is written there.

In the data processing control circuit 16, the input address data AD is the image address data PA.
When it is determined that the data is D, the image address data PAD is output to the EEPROM 18 and the write enable data WE is activated. next,
The data processing control circuit 16 controls the select signal SEL to switch the selector 15 so that the clock YCK generated by itself is derived to the address generation circuit 14.

At the same time, the data processing control circuit 16 causes the buffer memory 13 to output the out enable data OE.
Is activated. Therefore, the image data PD from the buffer memory 13 is generated by the address data generated by the address generation circuit 14 based on the clock YCK.
Are sequentially read and written in the EEPROM 17 page by page.

After that, the EEPROM 17 stores the image data P
With D written, the data processing control circuit 16
Out enable data O for the EEPROM 17
When E is set to the active state, the image address data PAD is output, the written image data PD is read out, and it is determined whether or not it matches the image data PD recorded in the buffer memory 13. Perform verification.

If the image data PD read from the EEPROM 17 and the image data PD recorded in the buffer memory 13 do not match, the image data PD is transferred from the buffer memory 13 to the EEPROM 17 again to perform the writing operation. Perform this operation, EEPRO
This is repeated until the image data PD read from M17 and the image data PD recorded in the buffer memory 13 completely match, and the image data PD is written there.

Next, the operation of reading the header data HD and the image data PD from the EEPROM 17 to the outside of the memory card body 11 will be described. First, the address at which the data to be read is recorded from the electronic still camera body side via the connector 12 is designated. Then, the specified address is supplied to the data processing control circuit 16, and it is determined whether the address data HAD for the header or the address data PAD for the image.

After that, the data processing control circuit 16 activates the out enable data OE and the write enable data WE to the EEPROM 17 and the buffer memory 13 based on the determination result, and
The clock YCK generated by itself is the address generation circuit 1
4 switches the selector 15 so that the EEP
The header data HD and the image data PD are read from the ROM 17 in page units and written in the buffer memory 13.

Then, the data processing control circuit 16 switches the selector 15 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 14, and the bus clock BCK is supplied.
The address data generated by the address generation circuit 14 based on CK is read out from the buffer memory 13 and led out to the electronic still camera main body via the connector 12, where the header data HD and the image data PD are stored.
Is read.

Therefore, according to the configuration of the above-described embodiment, when there is a rewriting request for the header data HD having a property that the data amount is small and there are many data to be rewritten in byte units, the entire header is read from the EEPROM 17. The data HD is read to the buffer memory 13, and the header data HD is rewritten byte by byte in the buffer memory 13 by random access.
Since all the header data HD of No. 3 is written to the EEPROM 17 in page units, the EEPR having a large storage capacity in which writing and reading of data in byte units cannot be performed.
Even using the OM 17, it is possible to easily write and read data in byte units.

In addition, since data transfer between the electronic still camera body and the memory card body 11 is always performed via the buffer memory 13, the data writing speed and the data reading speed are improved, and the data is used in an SRAM card-like manner. Will be able to. Also,
The write verify unique to the EEPROM 17 is also provided in the buffer memory 1 provided inside the memory card body 11.
3 is used, the memory card main body 11 can be used just like an SRAM card. The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0042]

As described in detail above, according to the present invention,
It is possible to provide an extremely good memory card device in which the writing speed and the reading speed of data are improved as much as possible by using the EEPROM and the memory card device is improved so that it can be used like an SRAM card.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a diagram showing the lengths of an SRAM and an EEPROM in comparison with each other.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Buffer memory, 14 ... Address generating circuit, 15 ... Selector, 16 ... Data processing control circuit, 17 ... EEPROM.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Terasaki 1-9-2 Harara-cho, Fukaya-shi, Saitama Prefecture Fukaya Plant, Toshiba Corporation (72) Hiroaki Matsubara Inc. 1-9, Harara-cho, Fukaya-shi, Saitama No. 2 inside Toshiba Fukaya Plant (72) Inventor Koji Maruyama 8 Shinsita-cho, Isogo-ku, Yokohama, Kanagawa Kanagawa Prefecture Media Media Technology Research Institute (72) Inventor Takaaki Suyama 3-3 Shinbashi, Minato-ku, Tokyo No. 9 In Toshiba A & V Co., Ltd. (72) Inventor Satoshi Sato 3-3-9 Shimbashi, Minato-ku, Tokyo Within Toshiba A & V E. Co., Ltd.

Claims (1)

[Claims] 1. A first data group having a property that a small amount of total data is required to write and read data in units of bytes, and a second data group having a large total data amount and an overall sequential property. A memory card device for inputting and recording data including a data group,
Has a storage capacity for recording all of the data group, is capable of high-speed writing and reading of data, and inputs / outputs data between the buffer memory for external data transfer and this buffer memory. The first one
First and second data groups in which the first and second data groups are recorded, respectively
And an EEPROM capable of writing and reading data in page units and having a storage area of
In a state in which data rewriting in byte units is requested for the first data group recorded in
After transferring all the data in the first memory area to the buffer memory and rewriting the data in byte units in the buffer memory, all the data in the buffer memory in page units in the first memory of the EEPROM. Control means for writing in a storage area, and the EEPROM from the buffer memory
In the state where the data is transferred and written to the EEPROM,
The data written in the buffer memory is read out and compared with the data in the buffer memory, and if the data does not match, the data is written again by transferring the data from the buffer memory to the EEPROM. Memory card device.