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JPH0468318A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH0468318A
JPH0468318A JP2181939A JP18193990A JPH0468318A JP H0468318 A JPH0468318 A JP H0468318A JP 2181939 A JP2181939 A JP 2181939A JP 18193990 A JP18193990 A JP 18193990A JP H0468318 A JPH0468318 A JP H0468318A
Authority
JP
Japan
Prior art keywords
insulating film
active matrix
inter
matrix substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2181939A
Other languages
Japanese (ja)
Other versions
JP3053848B2 (en
Inventor
Hirohisa Tanaka
田仲 広久
Koji Taniguchi
幸治 谷口
Tadanori Hishida
忠則 菱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP18193990A priority Critical patent/JP3053848B2/en
Publication of JPH0468318A publication Critical patent/JPH0468318A/en
Application granted granted Critical
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Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133357Planarisation layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer

Landscapes

  • Liquid Crystal (AREA)

Abstract

PURPOSE:To easily form an inter-layer insulating film in a fine shape and to eliminate a defect in insulation between a signal line and a pixel electrode by forming the inter-layer insulating film in multi-layered structure of an organic insulating film and an organic insulating film. CONSTITUTION:This active matrix substrate is equipped with the inter-layer insulating film 10 which is formed covering a switching element 13 formed on an insulating substrate 1, a contact hole 12 formed at the part of the inter- layer insulating film 10 on the output terminal of the switching element 13, and the picture element electrode 11 which is connected to the output terminal of the switching element 13 through the contact hole 12 formed on the inter- layer insulating film. The inter-layer insulating film 10 is formed in the multi- layered structure of the organic insulating film 10a of polyimide resin, etc., and the inorganic insulating film 10b of silicon oxide, etc., and the organic insulating film 10a is etched by using the inorganic insulating film 10b as an etching mask, and then the inter-layer insulating film 10 can be patterned in the fine shape. Consequently, the inter-layer insulating film 10 in the fine shape can easily be formed and an insulation defect between a signal line and a picture element electrode is eliminated.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、液晶等の表示媒体と組み合わせてマトリクス
型の表示装置を構成するためのアクティブマトリクス基
板に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix substrate for constructing a matrix type display device in combination with a display medium such as a liquid crystal.

(従来の技術) アクティブマトリクス型表示装置は、高いコントラスト
有し、絵素数が制約されない等の利点がある。そのため
、アクティブマトリクス表示装置に用いられるアクティ
ブマトリクス基板に関する研究が盛んに行われている。
(Prior Art) Active matrix display devices have advantages such as high contrast and no restrictions on the number of picture elements. Therefore, active matrix substrates used in active matrix display devices are being actively researched.

アクティブマトリクス基板は複雑な製造工程を経て製造
されるため、製造歩留りが低く製造コストが高いという
欠点を有している。
Since active matrix substrates are manufactured through complicated manufacturing processes, they have the drawbacks of low manufacturing yield and high manufacturing cost.

典型的なアクティブマトリクス基板の部分平面図を第3
図に、第3図のIV−rV線に沿った断面図を第4図に
示す。ガラス等の絶縁性基板1上に、CrS Ta等か
らなる多数のゲートバス配線3が平行に設けられ、ゲー
トバス配線3からはゲート電極2が分岐している。ゲー
トバス配線3は走査線として機能している。ゲート電極
2上には、スイッチング素子として薄膜トランジスタ(
以下では「TFTJと称する)13が形成されている。
The third partial plan view of a typical active matrix substrate
FIG. 4 shows a sectional view taken along the line IV-rV in FIG. 3. A large number of gate bus lines 3 made of CrS Ta or the like are provided in parallel on an insulating substrate 1 made of glass or the like, and gate electrodes 2 are branched from the gate bus lines 3. The gate bus wiring 3 functions as a scanning line. On the gate electrode 2, a thin film transistor (
13 (hereinafter referred to as "TFTJ") is formed.

TFTI 3の断面構造を第4図に従って説明する。ゲ
ート電極2を覆って絶縁性基板1上の全面に、5iNx
(窒化シリコン)、5fOx(酸化シリコン)等からな
るゲート絶縁膜4が形成されている。ゲート電極2の上
方のゲート絶縁膜4上には、非晶質シリコン(以下では
ra−SiJと称する)、多結晶シリコン、CdS e
等からなる半導体層5が形成されている。半導体層5の
一方の端部には、Ti、Mo、AI等からなるソース電
極6が重畳形成されている。また、半導体層5のもう一
方の端部には、同様にTI、MOlAl等からなるドレ
イン電極8が重畳形成されている。
The cross-sectional structure of TFTI 3 will be explained with reference to FIG. 5iNx is applied to the entire surface of the insulating substrate 1 covering the gate electrode 2.
A gate insulating film 4 made of (silicon nitride), 5fOx (silicon oxide), or the like is formed. On the gate insulating film 4 above the gate electrode 2, amorphous silicon (hereinafter referred to as ra-SiJ), polycrystalline silicon, CdS e
A semiconductor layer 5 is formed. At one end of the semiconductor layer 5, a source electrode 6 made of Ti, Mo, AI, etc. is formed in an overlapping manner. Further, on the other end of the semiconductor layer 5, a drain electrode 8 similarly made of TI, MOlAl, etc. is formed in an overlapping manner.

ドレイン電極80半導体層5とは反対側の端部には、I
 T O(IndiurATin 0xide)からな
る絵素電極11が重畳されている。第3図に示すように
ソース電極6には、ゲートバス配線3に前述のゲート絶
縁膜4を挟んで交差するソースバス配線7が接続されて
いる。ソースバス配線7は信号線として機能している。
At the end of the drain electrode 80 opposite to the semiconductor layer 5, an I
A picture element electrode 11 made of T O (Indiur ATin Oxide) is superimposed. As shown in FIG. 3, the source electrode 6 is connected to a source bus line 7 that intersects the gate bus line 3 with the gate insulating film 4 interposed therebetween. The source bus wiring 7 functions as a signal line.

ソースバス配線7もソース電極6と同様の金属で形成さ
れている。
The source bus wiring 7 is also made of the same metal as the source electrode 6.

(発明が解決しようとする課題) 第3図及び第4図に示すアクティブマトリクス基板では
、ソースバス配線7と絵素電極11との間の絶縁不良が
生じ易い。ソースバス配線7と絵素電極11とが同一の
ゲ・−ト絶縁膜4上に形成されているからである。
(Problems to be Solved by the Invention) In the active matrix substrates shown in FIGS. 3 and 4, poor insulation between the source bus wiring 7 and the picture element electrode 11 tends to occur. This is because the source bus wiring 7 and the picture element electrode 11 are formed on the same gate insulating film 4.

このような絶縁不良を解消するために、第5図に示すよ
うに、TFT13上にポリイミド樹脂等からなる層間絶
縁膜10を形成し、この層間絶縁膜io上に絵素電極1
1を形成した構成が考えられる。この構成ではドレイン
電極8と絵素電極11とは、層間絶縁膜10に形成され
たコンタクトホール12を介して接続されている。尚、
第5図のアクティブマトリクス基板では、半導体層5と
ソース電極6及びドレイン電極8との間のオーミックコ
ンタクトをとるため、P(リン)をドープしたa−Sf
(以下では「n+型a−3iJと称する)からなるコン
タクト層9.9が設けられている。第5図の構成ではソ
ースバス配線7と絵素電極11とが異なる層上に形成さ
れるので、前述の絶縁不良は生じない。
In order to eliminate such insulation defects, as shown in FIG.
A configuration in which 1 is formed is conceivable. In this configuration, the drain electrode 8 and the picture element electrode 11 are connected through a contact hole 12 formed in an interlayer insulating film 10. still,
In the active matrix substrate of FIG. 5, a-Sf doped with P (phosphorus) is used to establish ohmic contact between the semiconductor layer 5 and the source electrode 6 and drain electrode 8.
(hereinafter referred to as "n+ type a-3iJ") contact layer 9.9 is provided. In the configuration shown in FIG. 5, the source bus wiring 7 and the pixel electrode 11 are formed on different layers. , the aforementioned insulation failure does not occur.

また、第5図の断面構成を有するアクティブマトリクス
基板では、第6図に示すように、絵素電極11とゲート
バス配線3及びソースバス配線7とを重畳して形成する
ことができるので、絵素電極11とゲートバス配線3及
びソースバス配線7との間の間隙を無くして絵素電極1
1の面積を大きくすることができるいう利点がある。絵
素電極の面積が大きくなると、表示画面の開口率が大き
くなり、画像品位が高められる。
Furthermore, in the active matrix substrate having the cross-sectional configuration shown in FIG. 5, the picture element electrode 11, the gate bus wiring 3, and the source bus wiring 7 can be formed in an overlapping manner as shown in FIG. The picture element electrode 1 is formed by eliminating gaps between the element electrode 11 and the gate bus wiring 3 and source bus wiring 7.
There is an advantage that the area of 1 can be increased. When the area of the picture element electrode becomes larger, the aperture ratio of the display screen becomes larger and the image quality is improved.

更に、層間絶縁膜10をポリイミド膜等の有機絶縁膜で
形成すると、TPT13等による段差を覆って基板上面
を平坦化することができる。液晶を表示媒体として表示
装置を構成する場合には、基板の上面が平坦であると、
更にその上に形成される配向膜も平坦に形成され、表示
媒体である液晶の段差部での配回不良を低減することが
できる。
Furthermore, if the interlayer insulating film 10 is formed of an organic insulating film such as a polyimide film, it is possible to cover the step caused by the TPT 13 or the like and flatten the upper surface of the substrate. When configuring a display device using liquid crystal as a display medium, if the top surface of the substrate is flat,
Further, the alignment film formed thereon is also formed flat, and poor alignment at the stepped portion of the liquid crystal serving as the display medium can be reduced.

ポリイミド樹脂等からなる層間絶縁膜10をパターン形
成するには、以下の2つの方法がある。
There are the following two methods for patterning the interlayer insulating film 10 made of polyimide resin or the like.

■ポリイミド等の膜上にポジ型レジストを塗布し、露光
し、アルカリ系の現像液でレジストと共に現像して、最
後にレジストを剥離するウェットエツチング法 ■ポリイミド膜等の上にレジストをバターニングし、ド
ライエツチング法によりエツチングを行い、最後にレジ
ストを剥離する方法 ■の方法では、現像液でポリイミド膜をエツチングする
ため、現像時間が長くなる。そのため、ポリイミド膜を
微細な形状にバターニングすることができない。また、
■のドライエツチング法によれば、ポリイミド膜とレジ
ストとのエツチングの選択性が低いので、レジストの膜
厚を太き(することが必要となる。そのために、この場
合にもポリイミド膜を微細な形状にバターニングするこ
とができない。
■Wet etching method in which a positive resist is applied onto a film such as polyimide, exposed, developed together with the resist using an alkaline developer, and finally the resist is removed ■Buttering the resist onto a film such as polyimide In method (2), in which etching is performed using a dry etching method and the resist is finally peeled off, the polyimide film is etched with a developer, so the development time becomes longer. Therefore, it is not possible to pattern the polyimide film into a fine shape. Also,
According to the dry etching method (2), the etching selectivity between the polyimide film and the resist is low, so it is necessary to thicken the resist film. Cannot be buttered into shape.

更に、液晶を表示媒体として用いる表示装置を構成する
場合には、絵素電極11を覆って層間絶縁膜10上にポ
リイミド樹脂からなる配向膜が形成されるので、配向膜
を形成するためにポリイミド樹脂を塗布すると、層間絶
縁膜10の膨潤によるクラック、膜剥がれ等が生じ易い
という問題点もある。
Furthermore, when configuring a display device using liquid crystal as a display medium, an alignment film made of polyimide resin is formed on the interlayer insulating film 10 to cover the picture element electrodes 11. When resin is applied, there is also the problem that cracks and film peeling are likely to occur due to swelling of the interlayer insulating film 10.

本発明はこのような問題点を解決するものであリ、本発
明の目的は、微細な形状の層間絶縁膜を容易に形成し得
る構造を有するアクティブマトリクス基板を提供するこ
とである。また、本発明の他の目的は、層間絶縁膜上に
配向膜を塗布して形成しても、層間絶縁膜にクラック、
膜剥がれ等を生じないアクティブマトリクス基板を提供
することである。
The present invention is intended to solve these problems, and an object of the present invention is to provide an active matrix substrate having a structure in which a finely shaped interlayer insulating film can be easily formed. Another object of the present invention is to prevent cracks in the interlayer insulating film even when an alignment film is formed on the interlayer insulating film.
An object of the present invention is to provide an active matrix substrate that does not cause film peeling or the like.

(課題を解決するための手段) 本発明のアクティブマトリクス基板は、絶縁性基板と、
該基板上に形成されたスイッチング素子と、該スイッチ
ング素子を覆って形成された層間絶縁膜と、該スイッチ
ング素子の出力端子上の該層間絶縁膜の部分に形成され
たコンタクトホールと、該層間絶縁膜上に形成され且つ
該コンタクトホールを介して該スイッチング素子の該出
力端子に接続された絵素電極と、を備えたアクティブマ
トリクス基板であって、該層間絶縁膜が有機絶縁膜と無
機絶縁膜との多層構造を有しており、そのことによって
上記目的が達成される。
(Means for Solving the Problems) An active matrix substrate of the present invention includes an insulating substrate,
A switching element formed on the substrate, an interlayer insulating film formed to cover the switching element, a contact hole formed in a portion of the interlayer insulating film above the output terminal of the switching element, and the interlayer insulating film. an active matrix substrate comprising a pixel electrode formed on the film and connected to the output terminal of the switching element via the contact hole, the interlayer insulating film comprising an organic insulating film and an inorganic insulating film. It has a multi-layered structure, thereby achieving the above object.

(作用) 本発明のアクティブマトリクス基板では、スイッチング
素子上に形成された層間絶縁膜が、ポリイミド樹脂やア
クリル樹脂等の有機絶縁膜と、酸化シリコンや窒化シリ
コン等の無機絶縁膜との多層構造を有している。この構
成によれば、有機絶縁膜を無機絶縁膜をエツチングマス
クとして用いてエツチングすることにより、層間絶縁膜
を微細な形状にパターニングすることができる。また、
ポリイミド樹脂等からなる液晶分子配回膜が更にこの上
に形成される場合にも、有機絶縁膜と配向膜との間に無
機絶縁膜が存在するので、有機絶縁膜にクラック、膜剥
がれ等も生じない。
(Function) In the active matrix substrate of the present invention, the interlayer insulating film formed on the switching element has a multilayer structure of an organic insulating film such as polyimide resin or acrylic resin and an inorganic insulating film such as silicon oxide or silicon nitride. have. According to this configuration, by etching the organic insulating film using the inorganic insulating film as an etching mask, the interlayer insulating film can be patterned into a fine shape. Also,
Even when a liquid crystal molecular alignment film made of polyimide resin or the like is further formed on top of this, an inorganic insulating film exists between the organic insulating film and the alignment film, so there is no possibility of cracks or peeling of the organic insulating film. Does not occur.

(実施例) 本発明の実施例について以下に説明する。本実施例のア
クティブマトリクス基板の一実施例の断面図を第1図に
示す。本実施例の部分平面図は、第6図に示すものと同
様である。本実施例のアクティブマトリクス基板は、ガ
ラス等の絶縁性基板1と、基板1上に形成されたスイッ
チング素子として機能するTFTI 3とを有している
。TFTI3の入力端子として機能するソース電極6に
は、信号線として機能するソースバス配線7が接続され
ている。TFTI3及びソースバス配線7を覆って基板
1上の全面に層間絶縁膜10が形成されている。層間絶
縁膜10は有機絶縁膜10aと無機絶縁膜10bとの2
層構造を有している。TFTI3の出力端子として機能
するドレイン電極8上の層間絶縁膜10の部分には、コ
ンタクトホール12が形成されている。絵素電極11は
層間絶縁膜10上に形成され且つコンタクトホール12
を介してTFTI3のドレイン電極8に接続されている
。また、絵素電極11は、第6図に示すように、ケート
バス配線3の一部及びソースバス配線7の一部に重畳さ
れるように形成されている。
(Example) Examples of the present invention will be described below. FIG. 1 shows a cross-sectional view of one embodiment of the active matrix substrate of this embodiment. A partial plan view of this embodiment is similar to that shown in FIG. The active matrix substrate of this embodiment includes an insulating substrate 1 made of glass or the like, and a TFTI 3 formed on the substrate 1 and functioning as a switching element. A source bus wiring 7 functioning as a signal line is connected to a source electrode 6 functioning as an input terminal of the TFTI 3. An interlayer insulating film 10 is formed over the entire surface of the substrate 1, covering the TFTI 3 and the source bus wiring 7. The interlayer insulating film 10 consists of an organic insulating film 10a and an inorganic insulating film 10b.
It has a layered structure. A contact hole 12 is formed in a portion of the interlayer insulating film 10 on the drain electrode 8 that functions as an output terminal of the TFTI 3. The picture element electrode 11 is formed on the interlayer insulating film 10 and has a contact hole 12.
It is connected to the drain electrode 8 of the TFTI 3 via. Further, the picture element electrode 11 is formed so as to overlap a part of the gate bus wiring 3 and a part of the source bus wiring 7, as shown in FIG.

第1図のアクティブマトリクス基板の製造工程を第2図
<a>〜(c)に示す。本実施例のアクティブマトリク
ス基板の製造工程について以下に説明する。まず、ガラ
スからなる絶縁性基板1上に、スパッタリング法により
3000人の厚さのTa金属層を形成し、この金属層を
フォトリングラフィ法及びエツチングによりパターニン
グを行って、ゲートバス配線3及びゲート電極2を形成
した。次に、プラズマCVD法により、4000人の厚
さのSiNxからなるゲート絶縁膜4と、後に半導体層
5となる厚さ1000人のa−Si層と、後にコンタク
ト層9.9となる厚さ400人のn1型a−Si層とを
この順で連続的に形成した。
The manufacturing process of the active matrix substrate of FIG. 1 is shown in FIGS. 2<a> to 2(c). The manufacturing process of the active matrix substrate of this example will be explained below. First, on an insulating substrate 1 made of glass, a Ta metal layer with a thickness of 3000 mm is formed by sputtering, and this metal layer is patterned by photolithography and etching to form gate bus wiring 3 and gate Electrode 2 was formed. Next, by the plasma CVD method, a gate insulating film 4 made of SiNx with a thickness of 4000 nm, an a-Si layer with a thickness of 1000 nm that will later become the semiconductor layer 5, and a thickness that will later become the contact layer 9.9 are formed. 400 n1 type a-Si layers were successively formed in this order.

次に、n9型a −S、 i層とa−Si層のパターニ
ングを行って、コンタクト層9.9及び半導体層5を形
成した。次に、この基板上の全面に、厚さ2000人の
Mo金属層をスパッタリング法によって形成し、このM
o金属層のパターニングを行って、ソース電極6、ドレ
イン電極8、及びソースバス配線7を形成した(第2図
(a))。以上により、TFTI 3が完成する。
Next, the n9 type a-S, i layer and the a-Si layer were patterned to form a contact layer 9.9 and a semiconductor layer 5. Next, a 2,000-layer Mo metal layer was formed on the entire surface of the substrate by sputtering, and the M
o The metal layer was patterned to form the source electrode 6, drain electrode 8, and source bus wiring 7 (FIG. 2(a)). Through the above steps, TFTI 3 is completed.

次に、TFTI3を形成した基板1上の全面にポリイミ
ド樹脂を1μmの厚さに塗布し、有機絶縁膜10aを形
成した。更に、有機絶縁膜10a上の全面に、スパッタ
リング法によって厚さ1゜00 AノS I O21!
iを形成した。この5ioJのパターニングを行って、
TPT13のドレイン電極8上のSiO2膜を除去し、
無機絶縁膜10bを形成した(第2図(b))。
Next, polyimide resin was applied to a thickness of 1 μm over the entire surface of the substrate 1 on which the TFTI 3 was formed, to form an organic insulating film 10a. Furthermore, the entire surface of the organic insulating film 10a is coated with a film having a thickness of 1°00 by sputtering.
i was formed. After patterning this 5ioJ,
The SiO2 film on the drain electrode 8 of the TPT 13 is removed,
An inorganic insulating film 10b was formed (FIG. 2(b)).

次に、無機絶縁膜10bをマスクとしてドライエツチン
グを行い、有機絶縁膜10aにコンタクトホール12を
形成した(第2図(C))。更に、無機絶縁膜10b上
の全面にITO膜を形成し、パターニングを行って絵素
電極11を形成した(第1図)。絵素電極11は層間絶
縁膜10に形成されたコンタクトホール12を介してT
PT13のドレイン電極8に接続されている。
Next, dry etching was performed using the inorganic insulating film 10b as a mask to form a contact hole 12 in the organic insulating film 10a (FIG. 2(C)). Further, an ITO film was formed on the entire surface of the inorganic insulating film 10b and patterned to form a picture element electrode 11 (FIG. 1). The picture element electrode 11 is connected to T through a contact hole 12 formed in the interlayer insulating film 10.
It is connected to the drain electrode 8 of PT13.

本実施例のアクティブマトリクス基板では、層間絶縁膜
10が有機絶縁膜10aと無機絶縁膜lObとの2層構
造を有しているので、有機絶縁膜10aにコンタクトホ
ール12を形成するドライエツチングに際して、無機絶
縁膜10bをマスクとして用いることができる。従って
、有機絶縁膜10aの微細な形状を形成することが可能
となる。
In the active matrix substrate of this embodiment, since the interlayer insulating film 10 has a two-layer structure of the organic insulating film 10a and the inorganic insulating film lOb, during dry etching to form the contact hole 12 in the organic insulating film 10a, The inorganic insulating film 10b can be used as a mask. Therefore, it becomes possible to form the organic insulating film 10a in a fine shape.

また、更に本実施例のアクティブマトリクス基板上にポ
リイミド膜からなる配向膜を形成する場合には、該配向
膜を形成するためにポリイミド樹脂を塗布しても、無機
絶縁膜10bの存在により、有機絶縁膜10aの膨潤に
よるクラック、膜剥がれ等を生じない。層間絶縁膜10
が2層構造なので、層間絶縁膜10の絶縁性も向上して
いる。
Furthermore, when forming an alignment film made of a polyimide film on the active matrix substrate of this embodiment, even if a polyimide resin is applied to form the alignment film, the presence of the inorganic insulating film 10b prevents organic Cracks, film peeling, etc. due to swelling of the insulating film 10a do not occur. Interlayer insulation film 10
Since it has a two-layer structure, the insulation properties of the interlayer insulating film 10 are also improved.

本実施例では無機絶縁膜iobにSiO2を用いたが、
他にSiN、等も用いることができる。また、本実施例
では有機絶縁膜のパターニングをドライエツチング法に
よって行ったが、有機絶縁膜がポリイミド樹脂の場合に
はアルカリ溶液によるウェットエツチング法によって行
ってもよい。更に、本実施例では有機絶縁膜としてポリ
イミド樹脂を用いたが、アクリル樹脂等の他の有機材料
を用いることもできる。
In this example, SiO2 was used for the inorganic insulating film iob, but
In addition, SiN, etc. can also be used. Further, in this embodiment, the organic insulating film was patterned by a dry etching method, but if the organic insulating film is made of polyimide resin, it may be patterned by a wet etching method using an alkaline solution. Furthermore, although polyimide resin was used as the organic insulating film in this embodiment, other organic materials such as acrylic resin may also be used.

また、本実施例ではスイッチング素子としてTPTを用
いた場合について説明したが、他の例えば、M T M
 (Metal−Insulator−Metal)素
子、ダイオード、バリスタ等を用いたアクティブマトリ
クス基板にも適用することができる。
Further, in this embodiment, the case where TPT is used as the switching element has been described, but other examples, such as MTM
The present invention can also be applied to active matrix substrates using (Metal-Insulator-Metal) elements, diodes, varistors, and the like.

(発明の効果) 本発明のアクティブマトリクス基板では、層間絶縁膜が
有機絶縁膜と無機絶縁膜との多層構造を有しているので
、微細な形状の層間絶縁膜を容易に形成することができ
る。従って、本発明によれば、信号線と絵素電極との間
の絶縁不良を生じることのないアクティブマトリクス基
板を得ることができる。また、本発明のアクティブマト
リクス基板上に配向膜を塗布して形成しても、層間絶縁
膜にクラック、膜剥がれ等を生じないので、高い歩留り
でアクティブマトリクス基板を得ることができる。
(Effects of the Invention) In the active matrix substrate of the present invention, since the interlayer insulating film has a multilayer structure of an organic insulating film and an inorganic insulating film, an interlayer insulating film with a fine shape can be easily formed. . Therefore, according to the present invention, it is possible to obtain an active matrix substrate that does not cause insulation defects between signal lines and picture element electrodes. Furthermore, even when an alignment film is applied and formed on the active matrix substrate of the present invention, cracks, film peeling, etc. do not occur in the interlayer insulating film, so that an active matrix substrate can be obtained with a high yield.

4、   の、 な号日 第1図は本発明のアクティブマトリクス基板の一実施例
の断面図、第2図<a>〜(c)は第1図のアクティブ
マトリクス基板の製造工程を示す図、第3図は従来のア
クティブマトリクス基板の部分平面図、第4図は第3図
のTV−TV線に沿った断面図、第5図は絵素電極とソ
ースバス配線との絶縁不良を低減したアクティブマトリ
クス基板の改良例の断面図、第6図は第5図及び第1図
に示したアクティブマトリクス基板の部分平面図である
Figure 1 is a sectional view of an embodiment of the active matrix substrate of the present invention, and Figures 2 <a> to (c) are views showing the manufacturing process of the active matrix substrate of Figure 1. Figure 3 is a partial plan view of a conventional active matrix substrate, Figure 4 is a cross-sectional view taken along the TV-TV line in Figure 3, and Figure 5 is a partial plan view of a conventional active matrix substrate that reduces insulation defects between picture element electrodes and source bus wiring. FIG. 6 is a sectional view of an improved example of the active matrix substrate, and is a partial plan view of the active matrix substrate shown in FIGS. 5 and 1.

1・・・絶縁性基板、2・・・ゲート電極、3・・・ゲ
ートバス配線、4・・・ゲート絶縁膜、5・・・半導体
層、6・・・ソー:2.i極、7・・・ソースバス配線
、8・・・ドレイン電極、9・・・コンタクト層、lO
・・・層間絶縁膜、10a・・・有機絶縁膜、10b・
・・無機絶縁膜、11・・・絵素電極、12・・・コン
タクトホール、13・・・TPT0 以上
DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Gate bus wiring, 4... Gate insulating film, 5... Semiconductor layer, 6... So:2. i-pole, 7... source bus wiring, 8... drain electrode, 9... contact layer, lO
...Interlayer insulating film, 10a...Organic insulating film, 10b.
...Inorganic insulating film, 11...Picture element electrode, 12...Contact hole, 13...TPT0 or more

Claims (1)

【特許請求の範囲】 1、絶縁性基板と、該基板上に形成されたスイッチング
素子と、該スイッチング素子を覆って形成された層間絶
縁膜と、該スイッチング素子の出力端子上の該層間絶縁
膜の部分に形成されたコンタクトホールと、該層間絶縁
膜上に形成され且つ該コンタクトホールを介して該スイ
ッチング素子の該出力端子に接続された絵素電極と、を
備えたアクティブマトリクス基板であって、 該層間絶縁膜が有機絶縁膜と無機絶縁膜との多層構造を
有するアクティブマトリクス基板。
[Claims] 1. An insulating substrate, a switching element formed on the substrate, an interlayer insulating film formed to cover the switching element, and the interlayer insulating film on the output terminal of the switching element. An active matrix substrate comprising a contact hole formed in a portion thereof, and a pixel electrode formed on the interlayer insulating film and connected to the output terminal of the switching element via the contact hole. , an active matrix substrate in which the interlayer insulating film has a multilayer structure of an organic insulating film and an inorganic insulating film.
JP18193990A 1990-07-09 1990-07-09 Active matrix substrate Expired - Lifetime JP3053848B2 (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18193990A JP3053848B2 (en) 1990-07-09 1990-07-09 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPH0468318A true JPH0468318A (en) 1992-03-04
JP3053848B2 JP3053848B2 (en) 2000-06-19

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Country Link
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Cited By (20)

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JPH06118432A (en) * 1992-10-09 1994-04-28 Seiko Epson Corp Liquid crystal display
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JPH06138489A (en) * 1992-10-29 1994-05-20 Seiko Epson Corp Liquid crystal display device
US5866919A (en) * 1996-04-16 1999-02-02 Lg Electronics, Inc. TFT array having planarized light shielding element
US5933208A (en) * 1996-04-25 1999-08-03 Lg Electronics, Inc. Liquid crystal display with color filter and light shielding layer forming a substantially planarized surface over the TFT
JPH11212109A (en) * 1998-01-28 1999-08-06 Sharp Corp Substrate for liquid crystal display device
US6001539A (en) * 1996-04-08 1999-12-14 Lg Electronics, Inc. Method for manufacturing liquid crystal display
US6038008A (en) * 1996-11-29 2000-03-14 Lg Electronics Inc. Method of making LCD having roughened steps of the protection layer
US6052162A (en) * 1995-08-11 2000-04-18 Sharp Kabushiki Kaisha Transmission type liquid crystal display device with connecting electrode and pixel electrode connected via contact hole through interlayer insulating film and method for fabricating
US6100954A (en) * 1996-03-26 2000-08-08 Lg Electronics Inc. Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturing
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US6188452B1 (en) 1996-07-09 2001-02-13 Lg Electronics, Inc Active matrix liquid crystal display and method of manufacturing same
US6211928B1 (en) 1996-03-26 2001-04-03 Lg Electronics Inc. Liquid crystal display and method for manufacturing the same
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US6372534B1 (en) 1995-06-06 2002-04-16 Lg. Philips Lcd Co., Ltd Method of making a TFT array with photo-imageable insulating layer over address lines
US6476901B2 (en) 1997-10-06 2002-11-05 Sharp Kabushiki Kaisha Liquid crystal display including interlayer insulating layer at peripheral sealing portion
US6614493B1 (en) 1996-11-27 2003-09-02 Lg. Philips Lcd Co., Ltd. Liquid crystal display and method of manufacturing the same
US6774975B2 (en) 2000-02-25 2004-08-10 Lg.Philips Lcd Co., Ltd. Liquid crystal display panel having a patterned spacer
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Cited By (30)

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Publication number Priority date Publication date Assignee Title
JPH06118432A (en) * 1992-10-09 1994-04-28 Seiko Epson Corp Liquid crystal display
JPH06138488A (en) * 1992-10-29 1994-05-20 Seiko Epson Corp Liquid crystal display device
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US6507045B2 (en) 1995-06-06 2003-01-14 Lg Philips Lcd Co., Ltd. LCD with increased pixel opening sizes
US7445948B2 (en) 1995-06-06 2008-11-04 Lg. Display Co., Ltd. Method of making a TFT array with photo-imageable insulating layer over address lines
US6376270B1 (en) 1995-06-06 2002-04-23 Lg. Philips Lcd Co., Ltd. Method of making an array of TFTs having an insulation layer with a low dielectric constant
US8198110B2 (en) 1995-06-06 2012-06-12 Lg Display Co., Ltd. Method of making a TFT array with photo-imageable insulating layer over address lines
US6372534B1 (en) 1995-06-06 2002-04-16 Lg. Philips Lcd Co., Ltd Method of making a TFT array with photo-imageable insulating layer over address lines
US7531838B2 (en) 1995-06-06 2009-05-12 Lg Display Co., Ltd. LCD with increased pixel opening sizes
US6870188B2 (en) 1995-06-06 2005-03-22 Lg. Philips Lcd Co., Ltd. LCD with increased pixel opening sizes
US7745830B2 (en) 1995-06-06 2010-06-29 Lg Display Co., Ltd. LCD with increased pixel opening sizes
US6052162A (en) * 1995-08-11 2000-04-18 Sharp Kabushiki Kaisha Transmission type liquid crystal display device with connecting electrode and pixel electrode connected via contact hole through interlayer insulating film and method for fabricating
US6100954A (en) * 1996-03-26 2000-08-08 Lg Electronics Inc. Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturing
US6211928B1 (en) 1996-03-26 2001-04-03 Lg Electronics Inc. Liquid crystal display and method for manufacturing the same
US6001539A (en) * 1996-04-08 1999-12-14 Lg Electronics, Inc. Method for manufacturing liquid crystal display
US5926702A (en) * 1996-04-16 1999-07-20 Lg Electronics, Inc. Method of fabricating TFT array substrate
US5866919A (en) * 1996-04-16 1999-02-02 Lg Electronics, Inc. TFT array having planarized light shielding element
US5933208A (en) * 1996-04-25 1999-08-03 Lg Electronics, Inc. Liquid crystal display with color filter and light shielding layer forming a substantially planarized surface over the TFT
US6188452B1 (en) 1996-07-09 2001-02-13 Lg Electronics, Inc Active matrix liquid crystal display and method of manufacturing same
US6614493B1 (en) 1996-11-27 2003-09-02 Lg. Philips Lcd Co., Ltd. Liquid crystal display and method of manufacturing the same
US6038008A (en) * 1996-11-29 2000-03-14 Lg Electronics Inc. Method of making LCD having roughened steps of the protection layer
KR100287666B1 (en) * 1997-06-23 2001-04-16 마찌다 가쯔히꼬 Active matrix substrate
KR100264759B1 (en) * 1997-06-25 2000-09-01 가네꼬 히사시 Structure of thin film transistor and gate terminal manufactured reliably by simple process
US6476901B2 (en) 1997-10-06 2002-11-05 Sharp Kabushiki Kaisha Liquid crystal display including interlayer insulating layer at peripheral sealing portion
JPH11212109A (en) * 1998-01-28 1999-08-06 Sharp Corp Substrate for liquid crystal display device
EP1058314B1 (en) * 1999-06-04 2011-08-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an electro-optical device
US8890172B2 (en) 1999-06-04 2014-11-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an electro-optical device
US9293726B2 (en) 1999-06-04 2016-03-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an electro-optical device
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