JPH046153B2 - - Google Patents

Description

[Detailed description of the invention]

Industrial Application Field The present invention provides a memory device that reads N= ^2k bits of data in parallel.
2 ⁿ (1≦M≦2 ⁿ ) for data reduction and reading. 2. Description of the Related Art When displaying data with a large amount of information, such as an image, on a display device that can display only a small amount of information, the original data is sampled, reduced in size, and displayed. Conventionally, when reducing data stored in a memory device that can read N bits in parallel, a method has been used in which N bits are read out simultaneously and then the data is sampled. For example, if data stored in a memory device that can be read 8 bits in parallel is reduced to 3/8 and 24 bits are extracted, 8 bits of data will be read out from the memory device.
Each bit is read eight times (64 bits) and only the necessary data is sampled from this data. Fifth
The figure shows the principle of reduction according to the conventional method, where a shows data read out in 8-bit units, and b shows data sampled from 8 bits to 3 bits (reduced to 3/8). Problems to be Solved by the Invention In the conventional method described above, if the read speed of data from the memory device is the same as that without reduction, the data will be reduced compared to when 24 bits of data are retrieved without reduction. The subsequent data retrieval speed has decreased to 3/8. In general, if the speed of reading data from a memory device is constant, the speed of retrieving data after reduction decreases depending on the reduction ratio, and if the speed of retrieval of data after reduction is constant, the speed of retrieval of data after reduction decreases depending on the reduction ratio. A drawback is that the speed at which data can be read from the memory device must be increased. The present invention has been made in view of these drawbacks.
It is an object of the present invention to provide a reduction method that can sequentially read data at a constant processing speed regardless of the reduction ratio. Means for Solving the Problems In order to solve the above problems, the present invention reduces the reduction rate M/2 ⁿ (1≦M≦2 ⁿ ) to the sum of 1/2 ⁱ (M/2= _o 〓 ^{i= 0} a _i
2 ^-i ; a _i = 0or1), and the original data is 1/2 ⁱ
The data reduced to N= ^2k bits is read out from a memory device that can be read in parallel at each reduction rate 1/2 ⁱ so that the sampling position of the original data is different, and the data read out at each reduction rate 1/2 ⁱ is arranged. exchange. Effect In the present invention, with the above configuration, when the reduction rate M/2 ⁿ is expanded into the form of the sum of 1/2 ⁱ , 1/2 ⁱ of each term is
N-bit data can be read out in parallel, and by sampling the original data so that the sample position differs depending on each term and rearranging the data read out for each term, the reduction rate M/
2 Data can be read at a constant processing speed regardless of ⁱ . Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a memory device that can read N = 2 ^k bits of data in parallel, which is the original data reduced to 1/2 ⁱ , 2 is a buffer memory for once storing the data read from the memory device 1, and 3 is a buffer memory for once storing the data read from the memory device 1. 4 is a data rearrangement circuit that rearranges the data from the buffer memory 2 in the order of the original data; 4 is a data advice and sample position to be read from the memory device 1 according to the data reduction rate M/2 ⁿ ; This is a control circuit that takes out the data and controls the order of sorting in the data sorting circuit 3. The configuration of the memory device 1 capable of reading N bits of data in parallel, which is obtained by reducing the original data to 1/2 ⁱ , is disclosed in, for example, Japanese Patent Application No. 189722/1982 (Japanese Patent Application Laid-Open No. 81661/1983).
The configuration described in . (In other words, in the embodiment described in Japanese Patent Application No. 189722/1984, reduction by 1/2 is explained as an example. In this case, for example, if 8 bits is the readout unit, an 8 x 8 bit image is generated. is defined as a sub-block, and the adjacent 2x2 sub-blocks are defined as blocks, and the 8 independently readable and writable 1-bit x N address memories are replaced and written (this replacement is performed in the lower order of the 8 independently readable and writable memories). (Achieved by wiring 3-bit address lines).The replacement method is 1/1, 1/2 8 in the row direction and column direction.
A predetermined substitution is performed as shown in FIG. 9 so that the data required for bit reading is always written to a different memory. Japanese Patent Application No. 58-189722 describes the configuration and operation up to 1/2 as an example. For example, to achieve a reduction of up to 1/4, an 8 x 8 bit sub-block is made up of 4 x 4, and to achieve a reduction of up to 1/8, it is made up of 8 x 8. , controls the replacement performed during writing so that the 8-bit data required during reading is written to a different memory. For example, when reducing the size to 1/4, the result will be as shown in Fig. 10. The configuration of the memory device used in this application is the same as that of Japanese Patent Application No. 189722/1982, and the replacement and shuffle, which are data rearrangement regulations after reading, are also the same. Furthermore, a description of the apparatus and method necessary for reading out 1/2 ⁿ is already known and is disclosed in Japanese Patent Application No. 189722/1983 and is explained in detail. The apparatus shown in Japanese Patent Application No. 189722/1980 is capable of performing a reduction of 1/2 ⁿ by one readout. ) The case where data is read from the memory device 1 in 8-bit parallel and the reduction ratio is M/8 (1≦M≦8) will be explained in more detail. Memory device 1 has 256 bits in the row direction and 256 bits in the column direction.
Assume that 256 bits of data are stored. Second
The figure shows this data numbered. This 256×256 bit data is stored in the memory device 1 in parallel in rows of 8 bits each. For data reduced to 1/2, sample 2j + 1st data, for data reduced to 1/4, sample 4j + 2nd data, and for data reduced to 1/8, sample 2j + 1st data.
Sample 8j+4th data and read each 8 bits in parallel. Figure 3 a, b, and c are each 1/
It is a figure which shows a part of data which were reduced and extracted by 2, 1/4, and 1/8. If the sample positions are set as shown above, the data extracted for reductions of 1/2, 1/4, and 1/8 are all different. A case will be described in which 24 bits of data stored in the memory device 1 are sampled from the first data in the row direction for each reduction ratio M/8. Figures 4a to 4h show the memory device 1 for each reduction ratio.
Data read from and data rearrangement circuit 3
FIG. 2 is a diagram showing 24-bit data sorted by . For 1/8 reduction, it is sufficient to sample the 8j+4th data, read each 8-bit data three times in parallel, and arrange them in order (Figure 4a). When reducing by 2/8 (= 1/4), sample 4j + 2nd data and 3
It is sufficient to read them out twice and arrange them in order (Fig. 4b). When reducing by 3/8, it is expanded to the form 3/8 = 1/4 + 1/8, and the data obtained by sampling 4j + 2nd data is 8-bit parallel twice, and the data obtained by sampling 8j + 4th data is The bits are read out once in parallel, and the data is rearranged by the data rearrangement circuit 3 (FIG. 4c). When reducing by 4/8 (=1/2), it is sufficient to sample the 2j+1st data, read each 8-bit data in parallel three times, and arrange them in order (FIG. 4d). When reducing 5/8, it is expanded to the form 5/8 = 1/2 + 1/8, and the data obtained by sampling the 2j + 1st data is 8-bit parallel 3 times, and the data obtained by sampling the 8j + 4th data is The bits are read out once in parallel, the data is rearranged by the data rearrangement circuit 3, and 24 bits of the data are extracted (Fig. 4e). When reducing 6/8 (= 3/4), it is expanded to the form 3/4 = 1/2 + 1/4, and the 2j + 1st data is sampled twice in 8-bit parallel, and the 4j + 2nd data is The sampled data is read once in 8-bit parallel fashion, and the data is rearranged by the data rearrangement circuit 3 (FIG. 4f). When reducing 7/8, it is expanded to the form 7/8 = 1/2 + 1/4 + 1/8, and the 2j + 1st data is sampled twice in 8-bit parallel, and the 4j + 2nd data is sampled twice. 1 in 8-bit parallel
The data obtained by sampling the 8j+4th data is read once in 8-bit parallel fashion, the data is rearranged by the data rearrangement circuit 3, and 24 bits of the data are extracted (FIG. 4g). 8/8 (=1/1), without reduction, the original data can be read out twice in 8-bit parallel and arranged in order (Fig. 4h). Here, the means for rearranging the above data will be described in detail as follows. The data after reading out the standard 1/2, 1/4, and 1/8 is subjected to data rearrangement/replacement and shuffle operation as shown in Japanese Patent Application No. 189722/1983. Thereafter, the data of the plurality of words that have been processed are exchanged to form a regular data string, and this circuit configuration can be easily realized by a combination of a shift register and a selector. For example, when obtaining 24 bits with 6/8 = 3/4, the 3 words of data shown in Figure 4 f and Figure 6 are output alternately by the shift register as shown in Figures 7 and 8. and has a fixed length of 24-bit data. In addition, in this application, in order to make arbitrary reduction of M/2 ⁿ possible, the number of times of reading is set to be multiple times, and this number of times is smoothed regardless of M. However, since the number of reads cannot be made constant and the number of final output data should be kept constant, a buffer memory is used in the embodiment of the present application. This is part of the data reordering circuit. If the above-described operation is performed while sampling in the column direction according to the reduction ratio, rectangular data reduced to an arbitrary size of M/8 can be extracted. As explained above, when extracting 24 bits of arbitrary M/8 reduced data, it can be extracted only by reading 8 bits in parallel a maximum of four times. When the amount of data to be retrieved increases, the data reordering circuit 3
Since the amount of data to be saved is extremely small compared to the amount of data to be extracted, data can be read out at almost the same processing speed regardless of the reduction ratio. In the above example, the sample positions are 2j+1 for data reduced to 1/2, 4j+2 for data reduced to 1/4, and 4j+2 for data reduced to 1/8.
Although 8j+4th is sampled, it does not have to be this sample position. That is, in this application, since it is realized by M/2n,
The feature is that M/2n is expanded to the sum of 1/ ²ⁱ and read out. In Japanese Patent Application No. 189722, the read data position (sampling position) during reduced reading
Since M is 1/2 ⁿ , it can be set arbitrarily, but in this application, since M/2 ⁿ is expressed as the sum of 1/2 ⁱ , the combination of the sums (for example, for 3/8 readout, 1 /8 and 2/8 = 1/4 readout position combination), it is necessary to specify the sampling position so that different data can be read out. For example, in the case of 3/8 above, as shown in Table 1,
A combination is required in which the 1/8 read position and the 1/4 read position do not overlap. In this way, M/8 (1≦
In order to prevent data from overlapping in all reads when M≦8), the standard 1/2, 1/
4. The 1/8 reading position must be set to one of the combinations (eight ways) shown in Table 2.

【table】

[Table] The combinations shown in Table 2 are stored in the control circuit, and which sampling position combination A to H is selected can generally be selected based on evaluation of image quality and the like. Once the sampling combination is determined, reading is actually performed by controlling the lower addresses of eight independently readable and writable memories. Effects of the Invention As described above, according to the present invention, data can be read at the same processing speed regardless of the reduction ratio, and the refresh memory of a CRT display device that requires a zoom function is used. This allows high-speed zoom processing and is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a data reduction method according to an embodiment of the present invention, Fig. 2 is a state diagram showing a state in which 256 x 256 bit data is numbered, and Fig. 3 is a 1/2, 1/2 Figure 4 is a state diagram showing part of the data to be extracted after being reduced to /4 and 1/8.
8) is a state diagram showing the data read from the memory device 1 and the 24-bit data after the data is rearranged by the data rearranging circuit 3. Figure 5 is a principle diagram showing the conventional reduction method. Figure 6 is a diagram showing the principle of the conventional reduction method. is an explanatory diagram of one embodiment of the present invention, FIG. 7 is an explanatory diagram of one embodiment of the present invention, FIG. 8 is an explanatory diagram of one embodiment of the present invention, and FIG. 9 is an explanatory diagram of one embodiment of the present invention. Explanatory diagram of the memory device used, 1st
FIG. 0 is an explanatory diagram of a memory device used in an embodiment of the present invention. 1...Memory device, 2...Buffer memory, 3
...Data sorting circuit, 4...Control circuit.

Claims (1)

[Scope of Claims] 1. A memory device capable of reading N=2 ^k bits of data sampled from the original data every 2 ⁱ bits in parallel when the reduction rate is 1/2 ⁱ (0≦i≦n); Means for changing the sample position of original data when read at a reduction rate of 1/2 ⁱ , and means for changing the sample position of original data when the reduction rate is M/2 ⁿ (1≦M
≦2 ⁿ ), M/2 ⁿ is the sum of 1/2 ⁱ (M/2 ⁿ = _o 〓 ⁱ⁼⁰
a _i 2 ^-i ; a _i = 0 or 1) and read out a predetermined amount of N bits in parallel at each reduction ratio, and a means for rearranging the read data to read the sequentially reduced data. A data reduction method characterized by