JPS59128586A - Vertically/horizontally readable memory array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Application) The present invention stores character patterns for vertical writing and character patterns for horizontal writing as the same character pattern in a storage device, and generates character patterns for both vertical and horizontal writing from the storage device. The present invention relates to a memory array that can be read both vertically and horizontally, and is suitable for use in a device such as the above.

(Prior Art) A conventional vertical and horizontal character pattern generation device that outputs a character pattern for vertical writing and a character pattern for horizontal writing will be described. In addition, as used in this specification, "vertical writing" and "
``Horizontal writing'' refers to the writing style shown in FIG. In other words, horizontal writing is written by arranging each character horizontally as shown in Figure 1 (al), and vertical writing is written by arranging each character horizontally at an angle of 90 degrees as shown in the same figure (bl).
This means rotating counterclockwise and arranging them horizontally.

One of the conventional character pattern generation devices for vertical and horizontal writing that outputs character patterns for vertical writing and character patterns for horizontal writing stores fonts for vertical writing and horizontal writing in general general-purpose memory. This is a method that allows

In this system, for example, in the case of 32 x 32 bits, 7 onts, as shown in FIGS. 2 and 3, 32 bits are treated as one word, and data is handled in units of rows. Therefore, when reading this from memory, the data is output line by line, so fonts for both vertical and horizontal writing are stored in separate general-purpose memories as shown in Figures 2 and 3. It has the disadvantage that it needs to be memorized and the memory capacity becomes large. There is also a method of handling data in columns with 32 bits as one word, but
Similarly to the above method, this method also requires storing both fonts for vertical writing and horizontal writing in separate memories.

Another conventional character pattern generator that outputs character patterns for vertical writing and character patterns for horizontal writing is one that outputs fonts stored in row units and column by column, for example. be.

In other words, using general-purpose memory, two types of character patterns (for vertical writing and horizontal writing) are created from one type of character pattern (for vertical writing or horizontal writing).
It is designed to create different types of fonts.1 For example,
Consider a case where a 32 x 32 bit horizontal writing font pattern shown in FIG. 3 is stored.

(1) When writing vertically, first read out one word (32 bits) at the top according to the pattern shown in FIG. 3, shift it one bit to the right, and store the two shifted out bits in a buffer. Next, for the 2nd to 32nd lines, each read word is shifted to the right by 1 bit, and the shifted out bits are sequentially put into the buffer.

By the above operations, a font bit pattern for one scan line is obtained.

For the next scan line, one word (32 bits) at the top is read out and shifted to the right by two bits in the same manner as above. Then, the second bit that has been shifted out is put into the buffer. Subsequently, for the 2nd to 32nd rows, one word at a time is similarly read out and shifted to the right by 2 bits. Then, the shifted out second focus is placed in the buffer. In this way, the font bit pattern of the second scan line is obtained. Repeat the following operations to create a font for vertical writing.

(2) When writing horizontally, one word is read out line by line in the same way as described in the first conventional method.

This conventional method requires only half the memory capacity of the first conventional method, but as mentioned above, when creating a font for vertical writing from a 7-ont pattern for horizontal writing, it takes 32 bits to create a bit pattern for one scan line. In the case of a ×32-bit font, it is necessary to access memory 32 times.

For this reason, the processing time is significantly increased, which is disadvantageous for the rask scan method, which requires high-speed processing.

(Objective) An object of the present invention is to provide a memory that can read data from memory in both row and column directions, thereby enabling vertical and horizontal writing output with a small capacity memory. It is in. Another object of the present invention is to provide a memory for generating character patterns for both vertical and horizontal use, which shortens processing time and is suitable for the rask scan method which requires high-speed processing.

(Overview) The present invention is characterized by a plurality of memory chips arranged in a matrix, a memory array address means that allows access to a common address of each of the memory chips at once, and an output line for transmitting data stored at an address; a row data selector connected to each of the output line bundles of the memory chips arranged in the column direction among the plurality of memory chips; It has a column data selector connected to each of the output line bundles of the memory chips arranged in the row direction, making it possible to read data in both the vertical and horizontal directions.

(Example) The present invention will be explained below using examples. First, the principle of generating a horizontal and vertical character pattern using the memory array of the present invention will be explained with reference to FIG. Assume that a character pattern rAJ is stored in an n-bit×n-bit memory. In the present invention, this n-bit x n-bit memory is divided into blocks consisting of m-bit x m-bit (where m is a divisor of n) memory, and as shown in the figure, one
(however, i = n), total of 1 in the column direction! Formed by 2 pieces. For each block, the character pattern data stored in the memo IJ can be read out from both the row and column directions.

When reading out the character pattern "rAJ" in horizontal writing from the memory having such a configuration, first, the data in the first row of the first block is read out.

Next, the first line of the second block is read, and then the first line of the third block is read.

Similarly, read the first row of each block one after another, and
Read up to the first line of the block.

The read data of the first row is temporarily stored in, for example, a line buffer. The data is then used as the first line of data when printed or displayed on a printing device or display.

When the reading of the data of the first row of the first to first blocks is completed, the next step is to read the data of the second row of the first to first blocks.

After reading the second line data, it is input to the line buffer and used as the second line data to be printed or displayed. In this way, data in the third, fourth, . . . mth rows of the first to first blocks are read.

When the data reading of the m-th row of the 1st to 1st blocks is completed, this time, the 11th + 1)th to 21st
The th block is sequentially read from the first row to the mth row. Similarly, the (l+2)th to 31st blocks, the n+1)th to 41st blocks,
・・・・・・・・・Read the data from block <71!2-l+1) to the 12th block, temporarily store the read data in the line buffer, and print or display it. Data for each line.

As described above, by reading data from the memory, the character pattern rAJ for horizontal writing can be read.

Next, a method of reading out the vertical writing character pattern "<" from the memory shown in FIG. 4 will be explained. In this case, first, data in the rightmost column (first column from the right) of the first block is read. When this is finished, the next (ko, 21st
Read the data in the rightmost column of the block. Similarly, number 31.

Data in the rightmost column of the 41st, . . . , 12th blocks are read out in sequence. The read data in the rightmost column is stored in a temporary line buffer and used as the first line data of the printing device or display.

7th, 2/, 31... After reading the data in the rightmost column of the 12th block, the next step is to read the data in the second column from the right in each of the above blocks. . That is, No. 1.27! , 371. ......, 1
Data in the second column from the right of the second block is read out one after another. These read data are temporarily stored in the line buffer in the same manner as above, and are used as the second line data of the printing device or display.

In this way, the 1st, 21st, 31st . ......, 1
After reading the data from the right end of the second block to the mth column, next
>.

(3Al-1) , ..., the data of the (l''-1)th block is read in order from the leftmost column of each block.Then, each of these blocks After reading the data from column m to column m,
Next is the <l-2) t (2 no 2), (34'-2).

. . ., the data of the (7!2-2)th block S, ffk are read out sequentially from the right column to the m-th column.

Data reading in this order is carried out in the same manner, and finally, the first... No.(l+1).

The data is read up to the leftmost column of the (2/+1)th, . . . , (J"-l+1)th blocks.

These read data are printed or displayed on the printing device or the soba display from the first line to the nth line. This printed or displayed character pattern becomes "he", which is a character for vertical writing.

To summarize the above, the order of reading from the memory shown in Figure 4(a) is as follows when reading character pattern data for horizontal writing as shown in Figure 4(bj). l This is the solid line arrow ■, ■.

■, ...... in that order. On the other hand, if you want to read data of a character pattern for vertical writing, click the dotted arrow ■.

The order is ■, ■, etc.

Next, one embodiment of the present invention will be explained with reference to FIG. In this embodiment, one block of memory array is composed of 4 bits x 4 bits.

The memory array 1 includes memory chips m arranged in rows and columns,
l l m, 2* m1s r m1a r ”211
It consists of 16 pieces, m221 """"44. Each of these memory chips is, for example, 16 pins), 64 pins
It is composed of a MOS memory having a storage capacity of K bits or the like. Each of these memory chips m11 #”+4
? ..., m44 is a common memory array address line. are connected so that all of the same addresses in these memory chips can be specified at once by specifying one address.

For example, each memory chip m11 r m11 t...
..."If 44 is a 16KMOS memory, a 14-bit address signal is sent using the memory address line 7o. Therefore, for example, an address of 00000000000001 is sent from the address line io. Sometimes each memory chip m11' m12
+...The address of address 1 of m44 is specified. Similarly, address line l. From 0000000000
When the address of 0010 is sent, each memory chip m11゜ml! l...The address at address 2 of m44 is specified.

Below is the same address line! . Each memory chip "11F"1□ by the address sent through.

. . . A common address of 1m44 is specified.

That is, each memory chip m11. ml, ＋・・・・・・
...If a 16K MOS memory is used as the 2m44, a 16K 4-bit x 4-bit memory array will be realized.

Memory chip mllt ”12 +・・・・・・2
The output line for transmitting the read signal of m44 is the first. Second.
Third. Fourth row data selector 2a, 2b, 2c
, 2d and the first, second . Third. 4th column data selector 3
a.

Connected to 3b, 3c, and 3d.

Specifically, the memory chip mm11112 in the first row
Output line of m181"14'+11'If "Il
l + '14 are connected to the first column data selector 3a, and each of the first column data selector 3a is connected to the first column data selector 3a. Second. Third. Fourth row data selector 2a, 2b, 2c, 2
It is also connected to each of d.

Second row memory chip m2. , m229m281
Fat output line 124. It2□, ~, 124 are each connected to the second column data selector 3b, and the first, @2. Third. Fourth row data selector 2a.

]), 2c, and 2d (these are also sold closely.

Similarly, the memory chips m8□, m,, 1 in the third row
m.

m114 output line 'Rk l '82 "Hl '8
4 are connected to the third column data selector 3C, and each of the first . Second. Third. Fourth row data selector 2a
.

It is connected to each of 2b, 2c, and 2d.

Furthermore, the memory chip m41 j m4□ in the fourth row,
m4g+m44 output line '411 '42 1 '4
11 1 '44 are connected to the fourth column data selector 3d, and the first . Second. Third. Fourth row data selector 2a.

2b, 2c, and 2d.

In the memory array 1 configured as described above, a certain address
is selected, all memory chips mIf #”
+2 1 ``-,''-・1m44 From the address X, the information stored in these addresses X is output to the output lines '111' 121 of the respective memory chips.

Output in '44.

Next, when a row selection signal, for example, is sent from the control circuit via the row selection signal line 11, the row data selectors 2a, 2b, 2c, and 2d first select the first set of output lines '11f'u l Select '181'+4. And memory chip "II I"l□,m,,.

”Output the row data stored at address X of 14.

After reading out these row data, the row data selectors 2a, 2b, 2e, 2d select the second set of output lines 12++12□l'281'24.

As a result, the memory chip m21r m2g r m
oh .

"The row data written at address X of 24 is read out. Similarly, the row data selector 2 a + 2
b r2c, 2d are the third set of output lines 7I81 + '
82+'181184 is selected, and then the fourth set of output lines 141114□11g17!44 is selected. B, 1821 B, and 7B in the figure represent row data output through row data selectors 2a, 2b, 2c, and 2d.

In this embodiment, for example, 2 lines are used as the row selection signal line e1.
Prepare real wires and send 0″ 1″ signals to them.

This allows four types of signals to be sent to the row data selectors 2a, 2
b , 2c , 2d , and according to these four types of signals,
The row data selector may sequentially select the first to fourth sets of output lines.

On the other hand, when the control circuit sends a column selection signal via the column selection signal line 12, the column selectors 3a, 3
b, 3c, and 3d are each initially connected to the first set of output lines'
14 + '24 j '84 1 '44, then select the second set of output lines '1g + '2811ul ''4
Select 8. Next, the third set of output lines '121 '2
141 'Select 8□14□ and finally the 4th set of output lines'
Select 11 ” 21 1”Ill 1 '41. Therefore, first the memory chip "+4 #m241"
841 "The column data stored at address X of 44 is read out and sequentially m18r m2B rmgg t mg
; m12 * m22 r lTl52 p lT
14z; mHr m2tm,,y m4. Φ address X
The column data stored in is read out. c in the figure,
c,,c,,c4 are sad data selectors 3a, 3b, 3c + 3
The column data output through d is shown.

Note that two lines are prepared as the column selection signal line 12.
Create four types of signals using bit signals, and use them to select the column selector.
Controlling the connections of 3a, 3b, 3c r 3d is the same as the selection of the output line of the row data selector.

The above explanation of the memory array 1 according to the present embodiment has been made using an example having a plurality of 4-bit x 4-bit blocks.
This is for the purpose of simplifying the explanation; in reality, a memory array in which one block is approximately 8 bits x 8 bits is suitable. Therefore, the preferred memory array 1 according to the first embodiment
can be expressed as shown in FIG. In the figure, A
1, ~A8g represent memory chips consisting of, for example, 16K MOS memory, Ila ~ llh are row data selectors configured with 8→1 selectors, and 12a ~ 12h are 8
→Represents a column selector composed of 1 selector. Also,
No.1 and 12 indicate row selection signal lines and column selection signal lines, respectively, B1 to B8 indicate row data selected by row data selectors lla to 11h, and cl to C8 indicate row data selected by column data selectors 12a to 12h. shows the column data.

Note that each of the row data selectors lla to llh is
It goes without saying that the output lines of the eight memory chips can be used as row selection signals to sequentially select one line at a time. The same applies to the column data selectors 12a to 12h. Here, in this embodiment, the row selection signal line! 1 and column selection signal line 12,
Each consists of 3 wires and receives a 3-bit signal.
Create 8 types of signals.

Table 1 shows memory chips selected from memory array 1 in FIG. 6 by row selection signals and column selection signals.

Next, a vertical and horizontal character pattern generation device using the vertically and horizontally readable memory array of the present invention will be described with reference to FIG. This will be explained with reference to FIG. 8, taking a memory with n=4 as an example. In the figure, reference numeral 1 denotes a memory array comprising a plurality of 8-bit x 8-bit blocks of the memory shown in FIG. 7, that is, the memory array shown in FIG. 6. 2 and 3 indicate a row data selector and a column data selector, respectively; the former is used when outputting characters for horizontal writing, and the latter is used when outputting characters for vertical writing. Row data selector 2
selects row data to be read out in response to a row selection signal from the control circuit 4, while column data selector 3 selects column data to be read out in accordance with a column selection signal also sent from the control circuit 4.

5 is a row/column selector; when outputting characters for horizontal writing, a row is selected; when outputting characters for vertical writing, a column is selected. This selection is controlled by a row/column data switching signal output from the control circuit 4. Reference numeral 6 denotes a buffer register in which the character information sent through the row/column selector 5 is processed based on the buffer control signal output from the control circuit 4.
Memorized temporarily. This buffer register 6 usually contains
Character information for one line of a display or printing means (not shown) is stored. The buffer register 6 outputs display data or print data.

l in Figure 8. is a memory array address line, 11° is a row selection signal line, 12 is a column selection signal line, 18 is a row/column data switching signal line, 14 is a buffer control signal line, ! ,
is a column data line, and 16 is a row data line. Note that, as will be clear from the reasons described later, the memory address line l. The number of chips corresponds to the storage capacity of each memory chip constituting the memory array 1. Also, row selection signal line 4□
The column select signal lines 1 and 16 are each composed of three lines, and the column data line 1, the column data line 1, and the row data line 16 are each composed of eight lines.

Next, as shown in FIG. 7, rAJ and rB
Assuming that the letter J is divided into 16 blocks of 8 bits x 8 bits each, and each of these letters is stored at consecutive addresses in the memory array for one block, the following is shown in Figure 6. The operation of this embodiment will be explained.

Here, the memory array 1 includes the first to eight bits of the 8-bit x 8-bit memory array of the letter rAJ shown in FIG.
The 16th block and the 1st to 16th blocks of the 8-bit x 8-bit memory array of the character rBJ are included, and each of these blocks stores character information as shown in FIG. It is clear that there is.

As a condition, it is assumed that each of the blocks storing the characters A and B is assigned a memory array address as shown in Table 2.

Table 2 It is also assumed that the row selection signals with numbers 1 to 8 and the column selection signals with numbers 1 to 8 select the rows or columns of the memory array as shown in Table 3.

The operation of the block diagram in FIG. 8 when obtaining the output of the character pattern rABJ for horizontal writing in Table 3 will be described below with reference to the flowchart in FIG. 9 for explaining the functions of the control circuit 4.

The control circuit 4 is formed of, for example, a microcomputer, and starts when a command to output a character pattern rABJ for horizontal writing is received from an input device (not shown). Then, processing of the following steps is started.

Step S1...Substitute the first address [001J of character A1 to address a, and substitute the first address [101J of character B] to address b.

Step S2...The row/column data switching signal is set to row, and the row/column selector selects a row.

Step S3...The row selection signal is set to "1", and the row data selector 2 selects the memory chip A11rA1□ at the top of the memory array of the first block.
r Select Al1 (see Figure 6).

Step S4: rOJ is assigned to addresses α and β.

Step S5...Memory array address ra+α"
Set to . This selects the first block of memory array for letter A.

Step S6...The above memory chip A, 1. A1□
,...

The data is read from Al1 and stored in the buffer register 6.

This completes the reading of data from the uppermost memory chips AI1, AI2, . . . , A18 of the first block containing characters.

Step S7: Determine whether α=3, and if no, proceed to step S8.

Step S8: Add "1" to the α.

As a result, in step S5, the memory address is
” &+IJ, and the top memory chip of the second block with characters A s 7 AI, +01...
.

l.

Data is read from AI, 16. Subsequently, in step S6, the read memory chip A I
, 9+ AI, 10'..., A data is stored in buffer l, 16 register 6. Then, in step S7, α=
A determination is made as to whether or not the number has reached 3.

As described above, the third . Data is read from the memory chip located at the top of the fourth block, and the read data is stored in the buffer register 6.

In step S7, when α=3, step S9... sets the memory address to "b+β". This selects the memory array of the first block of letter B. Also, since the row selection signal is "1",
The data at the top of the first block of character B is output.

Step SIO...The read data is stored in the buffer register 6 and φ.

Step Sll... It is determined whether ρ=3 or not. If no, the process proceeds to step S12.

Step S12... "l" is added to β.

Next, the process advances to step S9, where the address of the second block of character B is set, and the data stored in the topmost memory chip of this block is read out. This data is stored in the buffer register 6 in step S10. This operation continues until β=3, and the letter B, J
3. The data at the top of the g4 block is stored in the buffer register 6 one after another. When β-3 is reached, step 8
Proceed to step 13.

Step S13: The data at the top of each of the first to fourth blocks of characters A and B stored in the buffer register 6 as described above is outputted as print data from the buffer register 6 by the buffer control signal. printed.

Step S14... It is determined whether the row selection signal is 8 or not,
If no, the process advances to step S15.

Step S15: 1 is added to the row selection signal.

Next, the process advances to step S4. Subsequently, the above-mentioned step S
4. S5. S6.87.88 are executed sequentially. As a result, the data written in the memory chip in the second row from the top of the memory array of the 1st + 2 r 3 t4 block of character A is read out.

Once this is completed, steps 89, 810, 811°8
Proceed to step 12. And the first of the letter B. The data stored in the memory chip in the second stage from the top of the 2,3°4 block memory array is read out.

The second of the 1.2, 3.4 blocks of these letters A, B
The data in the row is stored in the buffer register 6 in step S13.
It is then read out and printed.

By repeating the above operations, when the operation progresses until the line selection signal reaches 8 in step S14, reading of the data of the first to fourth blocks of each of characters A and B is completed.
Also, these data are printed out. When the row selection signal is equal to 8, the process proceeds to step S16.

Step 816...A determination is made as to whether (a+α) has become 16. That is, the letter A.

Regarding B, it is determined whether reading of data up to the 16th block has been completed or not. If no,
Proceed to step S17.

Step 517-a has (a+α+1), b has (b+β+
1) is assigned.

The operations are then repeated sequentially from step S3. In one cycle after step 817, the data stored in the memory arrays of the 5.6th and 7.8th blocks of characters A and B are sequentially read from the top of each block and printed out. . When this is completed, a+α in step S14 becomes 8. Therefore, the process advances to step S16.

It is clear that when the above steps are performed in sequence, the character pattern rABJ for horizontal writing is printed out.

Next, the operation of this embodiment when outputting the character pattern "<Y" for vertical writing will be explained with reference to chart 70- in FIG.

When the control circuit 4 receives a command from an input device (not shown) to output a character pattern "<," for vertical writing, the control circuit 4 starts. and,
Begin processing steps such as:

Step S20...Substitute the starting address 004 of character A to address a. Further, the starting address 104 of character B is assigned to address btζ.

Step S21...The row/column switching signal is set to a column, and the column of the row/column selector 5 is selected.

Step S22...The column selection signal is set to "1" and the row selection signal is set to "O" (1ζ).

Step S23...Substitute O for both α and βJ.

Step S24--Set the memory address a+αlζ. Here, since a+α is 004, the memory array of the fourth block of memory storing the character A is selected.

Step S25...In step S22, the column selection signal is
1'', the data stored in the rightmost memory chip of the memory array of the fourth block is read out and stored in the buffer register 6.

Step S26... It is determined whether α=12, and if no, the process proceeds to step 827.

Step 827...4 is added to α.

As a result, the memory array address is a+α=008
The memory array of the eighth block containing blank and characters is selected. Then, the data stored in the rightmost memory chip of the eighth block is stored in the buffer register 6.

In step 827, when 4 is further added to α, the memory array address a+α becomes 012.

Therefore, the twelfth block containing characters is selected, and the data stored in the memory chip in the rightmost column of this block is read out to the buffer register 6 in the same manner as described above.

Subsequently, the data in the rightmost column of the 16th block is read out.

When the above steps are completed, α=12, and the process proceeds to step 828.

Step 828...Memory array address b+βζ
Set ζ. Here, since b+β is 104ζζ, the memory array of the fourth block of letter B is selected. Since the column selection signal is rlJ, the data in the rightmost column of the memory array of the fourth block of character B is read out.

Step S29...The data read from the memory is stored in the pan 7 register 6.

Step S30... It is determined whether β=12, and if not, the process advances to step S31.

Step S31...4 is added to β.

Therefore, the memory address b+β is 108, and the data in the rightmost column of the eighth block of character B is read out. Similarly, the 12th of letter B. The data in the rightmost column of the 16th block is read out and stored in the buffer register 6, respectively.

When the above steps are completed, the process proceeds to β-12 and fi h, and the process proceeds to the next step S32.

Step S32...The 4th, 8th and 12th memories of the characters A and B stored in the buffer register
．． The data in the rightmost column of 16 blocks is read out from the buffer register 6 and printed out.

Step 833: It is determined whether the column selection signal has reached 8. If no, the process proceeds to step 834.

Step 834: Increment the column selection signal by 1.

The same processing as above is performed. This process is performed under the condition that the column selection signal is "2", so the 4.8th and 12th columns of the memory that stores the character A and the memory that stores the character B
．． The second data from the right of the 16th block is printed out.

In the same way as above, the same process as above is repeated until the column selection signal becomes "8". As a result, the data of blocks @4, 8, 12, and 16 of the memory for characters A and B are sequentially read out from the rightmost column and printed out. When the column selection signal becomes "8", the process advances to step S35.

Step S35... It is determined whether a+α=13 holds. If no, proceed to step 836.

Step S36... a-1, that is, 003, is substituted for a, and b-1, that is, 103, is substituted for b. Then, steps 822 to S34 described above are executed. By this, the 3.7 of letters A and B
, 11.15 blocks of the memory array are read out sequentially from the rightmost column to the right column.

When the reading of the 3.7th and 11.15th blocks of characters A and B is completed, a+α in step 835 becomes 15 and r
xD, proceed to step S36 again.

In step 836, a is set to 002. 102 is assigned to b, and through the subsequent steps 822 to S34),
The memory array of the 2nd, 6th, 10.14th blocks of letters A and B are read out sequentially from the rightmost column to the leftmost column.

When this is completed, a+α in step 835 becomes 14, and the process proceeds to step 836 again. Then, the memory arrays of the 1.5th and 9.13th blocks of characters A and B are read out through the processing of steps 822 to S34 that follow.

In this way, the vertical writing character pattern for letters A and B is
<-" is read out and printed out, a+α=13 in step 835. Therefore, the processing of the controller circuit 4 ends.

As described above, in the vertical and horizontal character pattern generator using the memory array of the present invention, data can be arbitrarily read in rows or columns in the horizontal or vertical direction from the memory chips arranged in a matrix. Because you can
Output characters for horizontal writing and characters for vertical writing arbitrarily,
This can be printed out or displayed on a display.

In addition, in the master's example, it is assumed that the memory that stores one character is 32 bits x 32 bits) and that these are formed from a collection υ of 8 bits x 8 bits blocks. has been limited in this way to simplify the explanation. Therefore, it is needless to say that the value is not limited to this value, and as described in FIG. 4, it may be formed into a film.

(Effects) As is clear from the above description, according to the present invention, it is possible to provide a memory with a small capacity that can generate character patterns for vertical writing and horizontal writing. Moreover,
Using the memory of the present invention, the processing time required to generate character patterns for vertical and horizontal writing can be reduced to the same amount of processing time as generating character patterns for both vertical and horizontal writing using the same memory capacity as the memory of the present invention. The conventional method (
This has the effect of significantly shortening the time compared to the second method (described in the prior art section). For example, as explained in the previous embodiment, if a 32 bit x 32 bit memory is formed from the ends of an 8 bit x 8 bit block,
It can be shortened to about 1/8. Therefore, it can be said that the vertical and horizontal character pattern generating device using the memory array that can be read both vertically and horizontally according to the present invention is suitable for the rask scan type that requires high-speed processing.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram of horizontal writing and vertical writing character patterns,
Figures 2 and 3 are conceptual diagrams of the character pattern rAJ stored in a 32x32 bit memory, Figure 4 is a conceptual diagram of the character pattern rAJ stored in the memory applied to the present invention, and the side diagram is a bit diagram. FIG. 6 is a detailed block diagram of a memory array according to an embodiment of the present invention, which has been explained in detail with a reduced number.
Figure 7 is a concept of character patterns rAJ and rBJ stored in a memory array according to an embodiment of the present invention. Figure 9 is a flowchart for explaining the function of the control circuit in Figure 8 when outputting the character pattern rABJ for horizontal writing, and Figure 10 shows the control circuit when outputting the character pattern "<bacteria" for vertical writing. It is a flowchart for explaining the function of the circuit. 1...Memory array (memory block), 2...Row data selector, 3...Column data selector, 4...Control circuit, 5...Row/column selector, 6...Buffer register agent Patent attorney Michihito Hiraki and 1 other person Figure 1 (Q) (shi) 2'・g) 32 Birth
32 bits Figure 2 32 bits Figure 3 32 bits

Claims (1)

[Claims] (1) A plurality of memory chips arranged in a matrix, a memory array address means that allows access to common addresses of each of the memory chips at once, and transmits data stored at each address of the memory chips. a row data selector connected to each of the output line bundles of the memory chips arranged in the column direction among the plurality of memory chips; and a memory arranged in the row direction among the plurality of memory chips. 1. A memory array that can be read in both vertical and horizontal directions, comprising a column data selector connected to each of the output line bundles of a chip, thereby making it possible to read data in both vertical and horizontal directions.