JPH0461154A - Thin-film transistor device - Google Patents

Abstract

PURPOSE:To equalize the effective channel length of both FETs approximately by mutually making gate electrode length differ in thin-film semiconductors formed to a common semiconductor base body and setting the gate electrode length of the P channel type FET at a value smaller than that of the N channel type FET. CONSTITUTION:In a thin-film transistor device in which a P channel type field- effect transistor FETP and an N channel type field-effect transistor FETN are formed to a thin-film semiconductor 2 formed onto a common base body 1, the gate electrode length LGP of the gate electrode GP of the P channel FETP is selected at a value smaller than that LGN of the gate electrode GN of the N channel FETN. Each source region and drain region 3SP and 3DP, 3Sn and 3DN of the P channel FETP and the N channel FETN are formed in mutually approximately equal channel length LPCH=LNCH by introducing B as a Ptype impurity and As as an N-type impurity while using each gate electrode GP and GN as masks. Accordingly, a C-MOS having approximately equal effective channel length LPCH and LNCH can be acquired.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a thin film transistor device, particularly a p-channel type MO
The present invention relates to a thin film transistor device having a so-called 6MO3 etc. formed by a 3-FET (field effect transistor) and an n-channel MO5-FET.

Overview of the two-shot Hu] The present invention provides thin film semiconductors formed on a common semiconductor substrate with different gate electrode lengths, and the gate electrode length of a p-channel FET is set smaller than that of an n-channel FET. so that the effective channel lengths of both FETs are approximately equal.

[Background Art] When obtaining an MO3-FET insulated gate field effect transistor with a short channel length, the source and drain regions are usually formed by implanting impurity ions and annealing on both sides of the gate electrode using the gate electrode as a mask. .

And p-channel type MO5-FE on the common semiconductor substrate.
Complementary type MO3- of T and n-channel type MO5-FET
When forming a FET, that is, a C-MOS, if the semiconductor substrate is silicon (Sl), the n-type impurity forming the source and drain of the n-channel MO3-FET, e.g., p-channel type MO3F, is preferable to S.
p-channel type F that constitutes the source and drain of ET
Since ET impurities such as B and BF have a larger diffusion constant and a larger amount of side diffusion, that is, a larger amount of penetrating under the gate electrode, for both p-channel MO5-FET and n-channel MO3-FET, If the lengths of the gate electrodes used as masks for forming the source and drain are made equal, the channel lengths L1 and LPCI of both the n-channel and p-channel will be the same.
is LIIC+1>'LPCM. For this reason, a method is adopted in which the process reduces side diffusion, but it is difficult to actually control it. Therefore, generally, the respective gate electrode lengths Lcp and LGK of p-channel and n-channel are set such that LGP>LGK,
By compensating for the difference in side diffusion, the effective channel length L of both channel type MOS-FETs is reduced as a result.
Efforts are being made to equalize NCI+ and Lpca.

However, when obtaining a C-MOS in a thin film transistor, when selecting such a gate length relationship, it is not possible to obtain the same channel length for both the n-channel FET and the p-channel FET.

[Problem to be solved by the invention]

In the present invention, in a thin film transistor device including a p-channel FET and an n-channel FET, such as C-MOS, having mutually different conductivity types in a common thin film semiconductor, the lengths of both channels are made uniform.

[A means to solve problems]

That is, in the present invention, for example, when a gate electrode, for example, a polycrystalline silicon structure doped with an impurity, is used for a thin film semiconductor formed on a quartz (S102) substrate through SiO□ as a gate insulating layer, that is, channel formation. The thin film semiconductor of the part is 310. It was discovered that when adopting an aspect in which the side diffusion is sandwiched by to be able to obtain That is, in the present invention, n
The type impurity, for example arsenic^S, has a smaller segregation coefficient for S10□ than the p-type impurity boron B, so in the thin film semiconductor sandwiched by this 3102, it is different from that in the case of a Si wafer. We will investigate the fact that they exhibit different properties, and based on this, we will try to make the channel length uniform.

That is, in the present invention, as shown in FIG. 1, which is an example of a cross-sectional view, a p-channel field effect transistor FETp and an n-channel In a thin film transistor device formed with a type field effect transistor FET*, the gate electrode Gp of the p-channel FET is
The gate electrode G of the n-channel F E TH has a gate electrode length LGp. The gate electrode length LGN is selected to be smaller than the gate electrode length LGN. and source and drain regions (3S, ) and (3DP) of a p-channel FET and an n-channel FET, respectively.

(33N) and (3[1,), respectively, using the gate electrodes Gp and GK as masks to form p-type impurities such as B.
and n-type impurities such as As are introduced to make the channel lengths approximately equal to each other. Set as H-SL +I C11.

[Effect]

According to the configuration of the present invention described above, each p-channel FE
The gate length of T and n-channel FET is LGF < LG
By setting it to N, it is possible to compensate for the difference in the amount of impurities introduced due to the difference in the segregation coefficient, and as a result, the effective channel length LPC! It is possible to construct a thin film transistor device having, for example, a C-MOS, that is, a combinational type FET, in which I and LWCH are approximately equal.

〔Example〕

An embodiment of a thin film transistor according to the present invention will be described.

First, as shown in Fig. 2, on a common substrate (for example, a quartz 5i02 substrate), polycrystalline silicon is first formed to a thickness of, for example, 40 mm by CVD (chemical vapor deposition). . This polycrystalline silicon is completely covered with Si.
Ion implantation is performed to form an amorphous thin film semiconductor. For example, 620℃ for 10 hours or 6C1O℃3
An annealing process is performed for 0 hours to perform polycrystallization and form a silicon thin film semiconductor (2). Then, a gate insulating layer (4) of S+02 is formed on this thin film semiconductor (2) by, for example, thermal oxidation of its surface or CVD method, and on this is doped with impurities at a high concentration to have a low specific resistance (E
A gate electrode layer (5) made of a polycrystalline silicon layer is formed.

Thereafter, as shown in the second WB, this polycrystalline silicon layer and the gate insulating layer below it are patterned by etching using IJ lithography to form a p-channel F.
Gate electrodes Cyp and G8 of the ET and n-channel FET are formed. In this case, the length of the gate part L
cp and or respectively Lap<1. ,,Select. Thereafter, the formation area of the negative FET, for example, the formation area of the p-channel FET, is covered with an ion implantation mask, such as a photoresist (6), and the formation area of the other FET is covered with the gate electrode 1. .

Impurity As is ion-implanted on both sides using the mask as a mask.

Next, although not shown, the photoresist on the p-channel FET formation part is removed, and the p-channel FET formation part is covered with photoresist, and the p-channel FET,
Impurities B, BF, are applied on both sides of the gate electrode G, using the gate electrode G as a mask.

Perform ion implantation.

Thereafter, each impurity is activated by annealing at, for example, 900 to 1000°C. At this time, each impurity B and As are diffused under the formation of the gate electrode G and G, I by so-called side diffusion. However, the amount of side diffusion, that is, the amount of penetration under each gate is different. In the present invention, the gate lengths LGP and LGN of the gate electrodes Gp and GN are determined in advance by taking into consideration the difference in the amount of penetration, and the gate lengths LGP and LGN of the gate electrodes Gp and GN are
< LGN, and in this way, the distance between the source and drain, that is, the effective channel length LPCI! is finally selected as shown in the first country. and LNC
11 are selected to be approximately equal. That is, in FIG. 3, curves (31) and (32) have B and As, respectively.
As shown in the figure, the difference in diffusion length between p-type impurity and n-type impurity depending on the annealing time can be expressed as gate length LGp and LGMO. Compensate by difference.

FIG. 1 is an enlarged cross-sectional view of an example of a thin film transistor device according to the present invention, FIG. 2 is a manufacturing process diagram thereof, and FIG. 3 is a characteristic diagram of diffusion length versus diffusion time.

(1) is the base, (2) is the thin film semiconductor layer, Gp and G,
is the gate electrode.

〔Effect of the invention〕

As described above, according to the present invention, the p-channel FET and the n-channel FET can be formed with a common and almost equal channel length in the S1 thin film transistor, which exhibits properties different from those in a normal S1 wafer. For example, the present invention can be applied to a C-MOS type thin film transistor device having a channel length of 5 μm or less, and its complementary characteristics can be reliably obtained.

[Brief explanation of drawings]

representative person Hide Matsukuma

Claims (1)

[Scope of Claims] A thin film transistor device in which a p-channel field effect transistor and an n-channel field effect transistor are formed on a thin film semiconductor formed on a common substrate, wherein the p-channel field effect transistor is The gate electrode length is selected to be smaller than the gate electrode length of the n-channel field effect transistor, and the source region and drain region of the p-channel field effect transistor and the n-channel field effect transistor are respectively A thin film transistor device characterized in that a p-type impurity and an n-type impurity are introduced using a gate electrode as a mask so that channel lengths are approximately equal to each other.