JPH03265143A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a gate electrode having a small surface roughness and a gate insulating film and to obtain a bottom gate type thin film transistor having a superior dielectric breakdown strength by a method wherein an impurity doping to a polycrystalline silicon film for gate electrode use is performed by an ion implantation method. CONSTITUTION:A wet thermal oxidation treatment is performed on an Si substrate 11, a thick SiO2 film 12 is generated on the substrate 11, a thin polycrystalline Si film 13 is generated on this film 12 by a low pressure CVD method, phosphorus ions are implanted in here to reduce the resistance of the film 13 and an annealing is performed in an N2 atmosphere for the purpose of activation. Then, a polycrystalline Si film 14 obtained in such a way is patterned into an insular form to form a gate electrode and a thin gate oxide film 15 is applied on this gate electrode. After that, a polycrystalline Si film 16 is deposited on the whole surface including this film 15, is patterned into an insular form, boron ions are implanted using a resist mask 17 and thereafter, an annealing treatment is performed and P<+> source and drain regions 18 and 19 are formed. Then, the mask 17 is removed, the whole surface is covered with an interlayer insulating film 20, openings are bored and Al wirings 21 are respectively mounted to the regions 18 and 19.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates in particular to a method for manufacturing thin film transistors in which the gate is located below the active region.

2. Description of the Related Art In recent years, thin film transistors have been actively researched for application to active matrix elements in liquid crystal displays and load elements in SRAM cells. In particular, so-called bottom-gate thin film transistors, in which the gate is located below the active region, can be latched without increasing the cell area by stacking a bottom-gate P-channel thin film transistor on top of a bulk n-channel MOS transistor. Up-free and low power consumption commercials
It can be used to realize O8-8RAM. For this reason, various approaches have been taken to improve the characteristics of bottom-gate thin film transistors.

Hereinafter, a conventional method for manufacturing a bottom gate thin film transistor will be described with reference to the drawings.

5(a) to 5(f) are cross-sectional views in the order of manufacturing steps of a conventional bottom-gate thin film transistor, and FIG. 6 shows the gate electrode, gate oxide film, and FIG. 3 is a cross-sectional view of a local area including an active area polysilicon thin film.

5 and 6, 51 is a silicon substrate;
2 is a thick silicon oxide film, 53 is a polysilicon film, 54
55 is a phosphorus-doped polysilicon film, 55 is a gate oxide film,
56 is a polysilicon film, 57 is a resist mask, 58 is a source region, 59 is a drain region, 60 is an interlayer insulating film,
61 is an AQ wiring.

In the conventional manufacturing method of bottom-gate thin film transistors, impurities are added to lower the resistance of the polysilicon film 53 used as the gate electrode using, for example, Hoffin (PH).
The method was carried out by thermal diffusion of phosphorus in an oxygen atmosphere at 1000°C using s).

Problems to be Solved by the Invention However, in the above manufacturing method, during the step of thermally diffusing phosphorus into the polysilicon film 53, the self-diffusion coefficient of silicon increases as the concentration of phosphorus increases, resulting in As a result of rapid grain growth, the surface of the phosphorus-doped polysilicon film 54 becomes highly uneven, as shown in FIG. The gate oxide film of a bottom gate type thin transistor is formed by thermally oxidizing the surface of this phosphorus-doped polysilicon gate electrode, so as shown in FIG.
It is greatly affected by the surface shape of the polysilicon 54 doped with phosphorus, and the surface becomes extremely uneven. As a result, in manufactured thin film transistors, the applied gate electric field tends to be locally concentrated, and the dielectric breakdown voltage of the gate oxide film is low.

In view of the above drawbacks, the present invention provides a method for manufacturing a thin film transistor having a gate insulating film with a high dielectric strength by forming an impurity-doped polysilicon film having a surface with small irregularities.

Means for Solving the Problems In order to solve the above problems, in the method for manufacturing a thin film transistor of the present invention, impurities are added to the polysilicon film used for the gate electrode by ion implantation.

Effects According to the above manufacturing method, activation of the implanted impurity species is sufficient at a low temperature of 900°C or less. Rapid grain growth is suppressed, and the surface of the resulting impurity-doped polysilicon film has very small irregularities. The surface unevenness of the gate oxide film, which is formed by thermally oxidizing the impurity-doped polysilicon film with small surface unevenness, is also very small, and local concentration of the gate electric field due to the unevenness is suppressed. the result,
A bottom gate type N-film transistor with excellent gate oxide film breakdown voltage can be manufactured.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

1(a) to 1(f) are cross-sectional views of the bottom gate type thin film transistor according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a gate sectional view of the bottom gate type thin film transistor manufactured in this embodiment FIG. 3 is a cross-sectional view including an electrode, a gate oxide film, and an active region polysilicon film. FIG. 3 shows the relationship between the size of surface irregularities and the concentration of added impurities for a polysilicon film doped with impurities by ion implantation in an embodiment of the present invention and a polysilicon film doped with impurities by conventional thermal diffusion. be. FIG. 4 shows dielectric breakdown of a gate oxide film formed on a polysilicon film doped with impurities by ion implantation in one embodiment of the present invention and a gate oxide film formed on a polysilicon film doped with impurities by conventional thermal diffusion. This shows the electric field strength.

In FIG. 1, 11 is a silicon substrate, 12 is a thick silicon oxide film, 13 is a polysilicon film, 14 is a polysilicon film into which phosphorous is ion-implanted, 15 is a gate oxide film, 1
6 is a polysilicon film, 17 is a resist mask, 18 is a lease region, 19 is a drain region, 20 is an interlayer insulating film, 2
1 is the Ae wiring.

A method for manufacturing a bottom gate type P-channel thin film transistor according to an embodiment of the present invention will be explained in the order of each step with reference to FIGS. 1(a) to 1(f).

(a) As shown in FIG. 1(a), a silicon oxide film 12 having a thickness of about 0.8 to 1.0 μm is formed on a silicon substrate 11 by wet thermal oxidation at 1000° C. for about 4 to 6 hours, for example. Next, for example, low pressure CVD (thickness 1500 mm
A polysilicon film 13 of ~1700 layers is deposited.

(b) As shown in FIG. 1(b), the polysilicon film 13
In order to lower the resistance, for example, ion implantation of phosphorus is carried out at an acceleration voltage of 50 to 100 Kev at a rate of about 1 to 3 x 1015 cIl''2.The activation of the implanted phosphorus is carried out at 900 Kev in a nitrogen atmosphere.
This is done by annealing at ℃ for about 30 minutes.

(C) As shown in FIG. 1(C), the polysilicon film 14 doped with phosphorus is patterned into an island shape to form a gate electrode. Subsequently, the surface of the phosphorus-doped polysilicon film 14 is dry or wet oxidized at 900°C to a thickness of 40°C.
A gate oxide film 15 having a thickness of about 0 to 800 A is formed.

(d) As shown in FIG. 1(d), a polysilicon film 16 having a thickness of 400 to 100 OA is formed by, for example, low pressure CVD, and then patterned into an island shape.

(e) As shown in FIG. 1(e), resist mask 17
For example, boron ion implantation is performed using an accelerating voltage of 30K.
eV at about 1 to 3 x 1015 cIl-2. Annealing is performed at 900° C. for about 30 minutes in a nitrogen atmosphere to form a P+ type lease region 18 and a drain region 19.

(f) As shown in FIG. 1(f), resist mask 17
After removal, the glabella insulating film 20 is made of, for example, NSC with a thickness of 60 mm.
After forming contact holes with the source region 18, drain region 19, and gate electrode 14, the Ae film is deposited to a thickness of 1.0 to 1.0 μm by sputtering, for example.
Ae wiring 21 is formed by forming a layer with a thickness of about 5 μm and patterning it.

Finally, the AQ wiring 21 and source region 1 are heated in a hydrogen atmosphere at 400 to 450°C for about 30 to 60 minutes.
8. Obtain ohmic contact with the drain region 19 and gate electrode 14, and terminate the dangling bonds in the polysilicon film 16, completing the thin film transistor.

As shown in FIG. 2, the thin film transistor manufactured in the above manner has a surface that is almost flat or has very small irregularities. It has a gate electrode 14 and a gate oxide film 15. Further, as shown in FIG. 3, even when the impurity concentration is increased in order to lower the resistance of the gate electrode, if the impurity is added by ion implantation, the surface unevenness will hardly increase. Furthermore, as shown in Figure 4,
The dielectric breakdown field strength of the gate oxide film of the thin film transistor according to embodiments of the present invention is approximately 3 MV/Cl11
This is an increase of about three times compared to the conventional example, and very good characteristics are obtained.

Although this embodiment has been described using a P-channel thin film transistor as an example, it goes without saying that similar effects can be obtained in the case of an N-channel thin film transistor. In addition, the gate oxide film can be formed not only by thermal oxidation method, but also by
It goes without saying that similar effects can be obtained when the film is formed using the CVD method.

Effects of the Invention As described above, according to the manufacturing method of the present invention, if impurities are added to the polysilicon film for the gate electrode by ion implantation, a gate electrode and a gate oxide film with small surface irregularities can be obtained, and the gate electrode A bottom-gate thin film transistor with excellent dielectric strength can be obtained, and its practical effects are significant.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a thin film transistor according to an example of the present invention in the order of manufacturing steps, Fig. 2 is a partial cross-sectional view of a device formed in the same embodiment, and Fig. 3 is a diagram showing the size of irregularities on the surface of a gate oxide film. FIG. 4 is a characteristic diagram showing the dielectric breakdown field strength of the gate oxide film, and FIGS. 5 and 6 are cross-sectional views of conventional thin film transistors in the manufacturing process, respectively, and the characteristics formed therefrom. FIG. 11...Silicon substrate, 12...Thick silicon oxide film, 13...Polysilicon film, 1
4...Polysilicon film doped with impurities, 15
... Gate oxide film, 16 ... Polysilicon film, 17 ... Resist mask, 18 ...
... Source region, 19 ... Drain region, 2
0... Interlayer insulating film, 21... Ae wiring.

Claims (1)

[Claims] A thin film transistor comprising a source region, a channel region, and a drain region in a semiconductor thin film located above a polysilicon gate electrode with a gate insulating film interposed therebetween, and in which impurities are added to the polysilicon gate electrode by ion implantation. manufacturing method.