JPH04332040A - Wait generator - Google Patents

Abstract

PURPOSE:To make it possible to change a wait cycle without correcting a pattern of a base by providing this wait generator with a binary counter capable of optionally setting up preset data, counting down clock signals by the counter and using a borrow output as a wait signal. CONSTITUTION:A chip select signal CS* from a microprocessor to a memory is inputted to a monostable multivibrator(MMV) 3 to obtain one pulse. An output pulse from the MMV 3 is inputted to the binary counter 6 as a load signal. An OR result between a clock CLK and the chip select signal is inputted to the counter 6 as a clock signal. At the time of inputting the load signal and the clock signal to the counter 6, data set up in a register 1 are loaded to the preset terminals P0 to P3 of the counter 6 to start down-counting. Then a borrow output from the counter 6 is sent to the microprocessor as a wait signal WAIT.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wait generator for generating wait signals for devices such as memory and I/O which require wait cycles due to slow access speeds in microprocessor systems.

0002

[Prior Art] In a microprocessor system,
When accessing devices such as memory and I/O that have different access speeds, the optimum access speed is obtained by generating a wait cycle for the microprocessor that is appropriate for each device. A conventional weight generator is shown in FIG. The shift register 7 generates wait signals W1 to Wn suitable for respective access speeds from the strobe signal S and the clock CLK. These signals and the chip select signals C1 to Cn of each device are input to the AND element 8 to calculate the AND. This determines the access speed of each device. This AND signal is input to the OR element 9, and by taking the OR, the wait signal WAI of the microprocessor system is
T is obtained. In this way, in the conventional wait cycle, the structure of the wait cycle was determined in a fixed manner in order to logically AND the wait signal suitable for each access speed and the chip select signal of each memory or I/O (in this paper). Patent application No. 2-320020 proposed earlier by the applicant
reference).

0003

[Problems to be Solved by the Invention] However, in the conventional method, the wait cycle is fixedly determined on the board pattern, so when determining the optimal wait signal during debugging, pattern modification is required. When using a device with an access speed different from that originally designed, there is a problem in that the wait cycle changes significantly and is not easy to correct. Therefore, an object of the present invention is to make it possible to easily change any weight cycle without modifying the substrate pattern.

0004

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a wait generator for generating wait signals for a microprocessor in a microprocessor system including devices with different access speeds such as memory and I/O. , a register circuit for sending data for generating a wait signal for each device, an OR circuit for calculating the logical sum of the chip select signal from the CPU and the clock CLK, and a monolithic circuit for generating pulses from the chip select signal. This device is characterized by comprising a table multivibrator circuit, a capacitor and a resistor for adjusting the output pulse width of the monostable multivibrator, and a binary counter circuit that outputs a wait signal for each device.

[0005]

[Operation] By the above means, data is set so that the maximum wait signal is generated at the register output when starting up the microprocessor system, and by changing the register data, the wait cycles are gradually reduced, and the memory This is to set the optimum wait cycle for each device, such as I/O and I/O.

[0006]

[Embodiment] A specific embodiment of the present invention will be described below with reference to FIG. Here, * in the signal name indicates negative logic. Further, in this embodiment, the device will be explained limited to a memory. First, a reset signal Reset* at startup of the microprocessor system is input to the preset terminal of register 1, and register outputs Q0 to Q3 are set to High. At that time, hexadecimal data Fh is output to the register outputs Q0 to Q3. This becomes the initial setting value of the wait signal generation data for the memory at the time of starting up the microprocessor system.

Next, the chip select signal CS* from the microprocessor to the memory is input to the monostable multivibrator 3 to obtain one pulse. that time,
The pulse width is determined by a capacitor 4 and a resistor 5. The output pulse is input to the binary counter 6 as a load signal. Further, the clock is controlled by ORing the chip select signal from the microprocessor and the clock CLK. The OR output signal is inputted to the binary counter as a clock signal. Here, when the load signal and the clock signal are input to the binary counter 6, P0 of the binary counter
~P3, hexadecimal data Fh is loaded from the register and starts counting down. One cycle is completed by sending the borrow output of the binary counter 6 to the microprocessor as a wait signal WAIT.

Here, the data signal lines D0 to D3 of the microprocessor are input to register 1, and the chip select signal RS* from the microprocessor to register 1 is input to the clock terminal of register 1. do. Now, the mechanism for actually generating the optimal weight signal will be described. First, the microprocessor writes certain data to memory,
Next, a read process is executed for that memory. If the data at that time match, it is assumed that the cycles for the microprocessor's memory are sufficiently satisfied.
Eh, which is 1 less than the previous hexadecimal data Fh, is set in the register 1. Similarly, data is written to and read from the memory, and if the data match, the register data is decremented by 1. By repeating this series of operations, the wait cycles for the microprocessor's memory gradually decrease. At this point, the data written to the memory and the data read out do not match.
The previous register setting data value becomes the optimum wait signal generation data for this memory. Thereafter, the memory is accessed by referring to the optimal data. Although the above description has been made with the device limited to memory, the same weight generator as shown in FIG. 1 can be configured for various I/Os.

[0009]

As described above, according to the present invention, it is possible to obtain optimum weights for memory, I/O, etc. of a microprocessor system, and it is easy to change the wait cycle. Furthermore, there is an effect that it is possible to easily change devices such as memories and I/Os having different access speeds.

[Brief explanation of drawings]

FIG. 1: Example of the present invention

[Figure 2] Conventional example

[Explanation of symbols]

1 Registers 2, 9 OR circuit 3 Monostable multivibrator 4 Capacitor 5 Resistor 6 Binary counter

Claims (1)

[Claims] Claims: 1. A wait generator for generating wait signals for a microprocessor in a microprocessor system including devices with different access speeds such as memory and I/O; a register circuit,
A logical sum circuit for calculating the logical sum of the chip select signal from the CPU and the clock CLK, a monostable multivibrator circuit for generating pulses from the chip select signal, and a circuit for adjusting the output pulse width of the monostable multivibrator. A weight generator circuit comprising a capacitor, a resistor, and a binary counter circuit that outputs a weight signal for each device.