JPH0581445A - Microcomputer lsi - Google Patents

Abstract

PURPOSE:To improve the degree of margin of the time required for input of data from the external in a microcomputer LSI. CONSTITUTION:A read control signal 121 which requests data read from the external to a microcomputer LSI 100 is directly inputted to the data hold indication input of a data holding circuit 111. Since the data hold indication input to the data holding circuit 111 is delayed by the output delay of the read control signal 121, the degree of margin of the data read time is improved by this output delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microcomputer L.
The present invention relates to SI, and more particularly to improving the margin of time required for inputting data from the outside.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional microcomputer LS.
The configuration of I, its timing diagram is shown in FIG.

In FIG. 2, a microcomputer LS
The I main body 100 includes an issue processing unit 101, a data holding circuit 111, a read control signal generation circuit 122, a data bus terminal group 110, a read control terminal 120, and a clock input terminal 102.

Now, the microcomputer LSI main body 1
To operate 00, a clock (a signal that changes periodically that determines the reference for the operation of the microcomputer) as shown in FIG. 4 is input from the clock input terminal 102.
The clock is a clock having a cycle indicated by a cycle (T _cy ) 200, and the execution processing unit 10 receives the clock signal 103.
1, the data holding circuit 111, and the read control signal generation circuit 122.

That is, all of these circuits operate in synchronization with the clock.

When the execution processing unit 101 executes a data read instruction, a data read request is input to the read signal generation circuit 122 through the read request signal 123. Then, the read signal generation circuit 122
Outputs a data read request to the read control control terminal 120 through the read control signal line 121. The data read request output from the read control terminal 120 is output as a low level signal in the timing chart of FIG.

Since this data read request is output in synchronization with the clock, it changes with some delay from the change of the clock. This is the clock transmission delay until the clock input from the clock input terminal 102 enters the read signal generating circuit 122 through the clock signal line 103, and the read signal generating circuit 122 reads the read request signal 123 from the execution processing unit 101. This is because the processing time required to generate a low-level signal in response to a data read request through the read control signal line 121 and the transmission delay until output from the read control terminal 120 through the read control signal line 121 are delayed by the delay time. (T _d ), indicated by 202 in FIG.

When the external input / output device, the storage device, or the like receives the data read request, it receives the data bus terminal group 110.
Output the data to. The time required at this time is called the access time ( _Ta ) and is shown by 201 in FIG. The time required for the data holding circuit 111 to hold the data input from the data bus terminal group 110 is called the setup time (T _s ) and is indicated by 203 in FIG. The data held in the data holding circuit 111 is input to the execution processing unit 101 through the read data bus signal line group 113,
It is processed.

Normally, assuming that the cycle in which the data read request is output is n clocks, the time that the external input / output device, the storage device, etc. can spend on the process of receiving the data read request and outputting the data (hereinafter referred to as access Described as allowable time) Tc Is as follows:

T _c = _{nT cy-} (T _d + T _s ) If this access allowable time T _c is shorter than the access time (T _a ) 201 of each external device, correct data cannot be delivered.

In this conventional microcomputer LSI, the read control signal line 121 is connected to the holding instruction input of the data holding circuit 111, and the data is held at the changing timing of the clock signal 103. Therefore, the setup necessary for holding the data is set. Time (T _s ) 203 is clock synchronized.

Therefore, the delay from the clock (T _d ) 2
When an external device is accessed by a read request having 02, the read request delay (T _d ) 202 and the data hold circuit 111 setup time (T _s ) 203 even if the data hold circuit 111 holds the data. And the access time ( _Ta ) 201 of each external device are required.

[0013]

In such a conventional microcomputer LSI, since the timing of holding the data in the data holding circuit 111 is synchronized with the clock, the delay (T
_{The d} ) 202 and the setup time (T _s ) 203 of the data holding circuit reduce the access allowable time (T _c ) of the external input / output device, the storage device and the like.

Normally, the period (T _cy ) 200 is 100 nanoseconds and the number of clocks n is 2 as standard. On the other hand, the delay time (T _d ) 202 is 70 nanoseconds and the setup time (T _a ) 203 is. In 10 nanoseconds, the allowable access time (T _c ) of the external input / output device and the storage device becomes 120 nanoseconds, which is only about one clock cycle.

Therefore, _a high-speed device having a short access time (T _a ) 201 must be used for an external input / output device, a storage device, etc., resulting in an expensive microcomputer system and a high-speed circuit design. There was a problem that it had to be.

It is an object of the present invention to provide a microcomputer which solves the above problems and improves the margin of access time.

[0017]

SUMMARY OF THE INVENTION According to the present invention, a clock is input, control signal terminals necessary for reading and writing to an external input / output device or a storage device, and input / output of information with the device. And a data bus terminal group for carrying out the above, and a microcomputer LSI internally having a read data holding circuit for reading data from an external input / output device or a storage device through the data bus terminal group and temporarily storing the data. A read data holding circuit for directly inputting a read control signal output to a read control terminal for requesting reading of data into the microcomputer LSI among the control signal terminals to a data holding instruction input. ..

[0018]

The present invention will be described below with reference to the drawings. FIG. 1 shows a microcomputer L according to an embodiment of the present invention.
FIG. 3 is a block diagram of SI, and FIG. 3 is a read timing diagram of FIG.

In FIG. 1 and FIG. 3, in this embodiment, the clock signal line 103 for determining the data holding timing of the data holding circuit 111 is eliminated and the read control signal line 121 is connected instead. By this change, the holding timing of the data holding circuit 111 is changed from the clock synchronization to the output timing of the read request, and the setup time (T _s ) 203 is set for the read request.

In FIG. 3, the period (T _d ) from the clock
The output of the read control terminal 120 delayed by 202 reads data from an external input / output device, a storage device, or the like. Each external device has an access time (T _a ) of 2
After 01, the data is output to the data bus terminal group 110. The data input from the data bus terminal group 110 is held by the data holding circuit 111.

The data holding timing is the timing when the read request is canceled, that is, the timing when the output of the read control terminal changes from the low level to the high level. Therefore, the setup time (T _a ) 203 of the data holding circuit 111 is added to this. Data is held at the timing.

At this time, since the data is held by the signal delayed by (T _a ) 202 from the clock, the margin of each external device is increased by the time indicated by (T _m ) 204 from the conventional circuit. The time (T _m ) 204 is a margin time when each external device is accessed when the microcomputer LSI of this embodiment is used.

[0023]

As described above, according to the present invention, the read holding control signal is connected to the holding instruction input of the data holding circuit inside the microcomputer LSI, so that the data holding circuit is at the timing when the read controlling signal becomes high level. Since it holds data, it has the effect of being able to hold data without being affected by the delay time for the clock of the read control signal itself, which improves the margin of access time for external input / output devices and storage devices. There is also an effect that you can.

[Brief description of drawings]

FIG. 1 is a microcomputer LS according to an embodiment of the present invention.
It is a block diagram which shows I.

FIG. 2 is a block diagram showing a conventional microcomputer LSI.

FIG. 3 is a timing diagram showing the operation of FIG.

FIG. 4 is a timing diagram showing the operation of FIG.

[Explanation of symbols]

 100 microcomputer LSI main body 101 execution processing unit 102 clock input terminal 103 clock signal line 110 data bus terminal group 111 data holding circuit 112 data bus signal line group 113 read data bus signal line group 120 read control terminal 122 read signal generation circuit 123 read Request signal line

Claims (2)

[Claims] 1. A control signal terminal for inputting a clock to read and write to the outside, and a data bus terminal group for inputting and outputting information to and from the outside. In a microcomputer LSI internally having a read data holding circuit for reading data from the outside and temporarily storing the data, output to a read control terminal requesting reading of data to the microcomputer LSI main body among the control signal terminals. The read control signal is directly input to the holding instruction input of the data holding circuit. 2. The microcomputer LSI according to claim 1, wherein the data holding circuit is a circuit to which a clock is not input.