JPH0432397B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic performance device that corrects the progress of an automatic performance in accordance with the timing of key operation and that allows easy tempo setting. Conventional automatic performance devices include those that automatically play melody sounds, obbligato sounds, bass sounds, chord sounds, and rhythm sounds based on reading musical score data, or those that automatically play a combination of these as appropriate. When you first set a tempo and start playing, this initial tempo is maintained until the end and automatic performance is performed. Therefore, when playing by pressing the keys in accordance with the automatic performance from such an automatic performance device, automatic performance always progresses at a constant tempo for both difficult and easy performance parts, making it difficult for beginners to perform. The key timing and automatic performance were out of sync, causing problems in practicing keystrokes on the keyboard. Furthermore, the tempo of automatic performance is set by operating the tempo adjustment volume, etc., but in order to set the tempo that matches the image, for example, you must operate the tempo adjustment volume while actually playing the automatic rhythm sound. However, it took time to set the tempo, and unnecessary automatic performance was required. This invention was made in view of the above circumstances.
If the timing of the performer's key presses is different from the timing when the keys should be pressed, the automatic performance is paused to ensure that the progress of the keyboard performance matches the automatic performance, and the tempo can be easily set and changed. The purpose of the present invention is to provide an automatic performance device that can perform the following functions. According to this invention, a tempo clock is generated to advance the automatic performance in relation to the timing at which the tempo setting switch is pressed, and the timing at which the operation should be performed is compared with the timing at which the operation should be performed. In this case, the generation of the tempo clock is prohibited from the timing of the operation to the timing of the operation, and the progress of the automatic performance is temporarily stopped. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a magnetic tape 1a formed on a musical score 1.
The data reading device 2 reads the recorded data, and the accompaniment keyboard 3 has an automatic melody sound performance function that automatically plays melody sounds based on this read data, and an automatic obbligato sound performance function that automatically plays obbligado sounds. Accompaniment tone automatic performance function that forms accompaniment tones such as automatic chord tones and automatic bass tones based on key presses and automatically plays these accompaniment tones, and automatically plays rhythm tones corresponding to the rhythm specified by appropriate means. This figure shows an embodiment in which the present invention is applied to an electronic musical instrument equipped with an automatic rhythm tone performance function. This electronic musical instrument also has a key display function that displays the next key to be pressed on the melody keyboard 4 based on the data read by the data reading device 2 for melody performance practice. The data reading device 2 reads obbligado data and melody data corresponding to an obbligado performance and a melody performance from the magnetic tape 1a of the musical score 1, and transfers the read data to an obbligado data memory 5 and a melody data memory 6, respectively. Note that when reading data, the data write/read control circuits 7 and 8 each enter a write mode, designate the write address of each memory 5 and 6, and write obligate data and melody data to each memory 5 and 6. Here, Table 1 shows an example of the data format corresponding to the obligate data and melody data.

[Table] That is, each data Di (i=1...n) consists of pitch data TL1 and note length data TL2, and pitch data TL1 is, for example, a 4-bit note code NC indicating a note and a 3-bit octave indicating an octave. The code OC is composed of a total of 7 bits of data, and the code length data is composed of, for example, 8 bits of data. An example of note length data is the second
It will look like a table.

[Table] Also, for rests, all bits of pitch data are set to “0”.
End data Dn indicating the end of data is represented by setting all bits of pitch data TL1 and note length data TL2 to "1". Reading of each data from obbrigade data memory 5 and melody data memory 6 is performed by data write/read control circuits 7 and 8, respectively. First, to start automatic performance, turn on the start switch 9 and turn on the standby flip-flop.
At the same time as setting FF1, the performance flip-flop FF2 is reset. When standby flip-flop FF1 is set, its output terminal Q
A signal "1" is applied to the differentiating circuit 10 and the delay flip-flop DF1. As a result, the differentiating circuit 10 outputs a preset signal ΔPR (one pulse), and the delay flip-flop DF1
After delaying this signal "1" for a predetermined time, it is added to the AND circuit A1 to enable the AND circuit A1. The preset signal ΔPR is applied to the data write/read control circuits 7 and 8 to put each circuit 7 and 8 into the read mode and set the internal address counter to the initial address. As a result, the first stored data is read out from the obligate data memory 5 and the melody data memory 6. Also, the preset signal △PR is an OR circuit.
Latch circuit L1, L via OR1 and OR2
2, L3, and L4, the latch circuit L1 latches the first obbliged data, and the latch circuit L3 latches the first melody data. On the other hand, since the performance flip-flop FF2 has been reset, it does not output the play signal PL ("1") and applies the signal "0" to the inverters IN1 to IN5. Inverter IN1 inverts the signal “0”,
In addition to the signal “1” via the OR circuit OR3 to the reset terminal R of the note length counter 11, the inverter
IN2 inverts the signal "0" and applies the signal "1" to the reset terminal R of the note length counter 11 via the OR circuit OR4, and also inverts the inverters IN3 and IN4.
each inverts the signal "0", applies the signal "1" to each reset terminal R of flip-flops FF3 and FF4 via OR circuits OR5 and OR6, and inverter IN5 inverts the signal "0",
A signal "1" is added to the address counter 13. Therefore, the performance flip-flop FF2
If the data has been reset, the mark length counters 11 and 12, flip-flops FF3 and FF4, and address counter 13 are all reset. Further, pitch data TL1 of the melody data latched by the latch circuit L3 is applied to the key display device 14, the comparator 15 and the rest detection circuit 16, and the key display device 14 is the key of the first note of the melody performance. (the key to be pressed first) is displayed by lighting up the indicator lamp disposed on that key. In this state, if you press a key on the melody keyboard 4 whose display lamp is lit, a key code KC (consisting of a 4-bit node code NC and a 3-bit octave code OC) indicating the pressed key will be output. be done. This key code KC is applied to the melody tone forming circuit 17. The melody sound forming circuit 17 forms a musical sound signal corresponding to the melody sound indicated by this key code KC, and sends this to the amplifier 18.
is added to the speaker 19 via the melody, and is generated as a melody sound. Further, the key code KC output from the melody keyboard 4 is added to the B input of the comparator 15. The comparator 15 has pitch data TL1 of the data latched in the latch circuit L3 added to its A input, and the pitch data TL1 added to this A input.
(indicating the sound to be pressed) and the key code KC added to the B input (indicating the sound to be pressed) match,
A match signal is output from the match terminal EQ. This coincidence signal is applied to AND circuit A2. AND circuit A2 is an OR circuit that takes the OR condition of the key code KC output from the melody keyboard 3 to other inputs.
Any key-on signal AKON output from OR7
(Signal that becomes “1” when any key is pressed)
A signal differentiated by a differentiating circuit 20 is added, and on condition that a key whose display lamp is lit is pressed, a pulse (key press coincidence signal) KEQ synchronized with the press of the key is output. This key press coincidence signal KEQ
is connected to AND circuit A3 via select switch 2,
A4, A5, and AND circuit A
1 and the OR circuit OR8 to the reset terminal R of the standby flip-flop FF1. AND circuit A1 is a delay flip-flop
Since it is enabled to operate by DF1, it outputs a pulse signal ΔPL upon input of the key press coincidence signal KEQ, and also applies this pulse signal ΔPL to the set terminal S of the performance flip-flop FF2. The performance flip-flop FF2 uses this pulse signal △PL
is set by PL, and outputs the play signal PL.
On the other hand, the standby flip-flop FF1 is reset and the AND circuit A1 is made inactive thereafter. Pulse signal △ output from AND circuit A1
PL is applied to data write/read control circuits 7 and 8 via OR circuits OR9 and OR10, respectively, and advances the internal address counter by one step. As a result, the obligate data memory 5
Then, the second data is read out from the melody data memory 6. In addition, the pulse signal △PL is passed through the OR circuits OR9 and OR1 to the latch circuit L1.
Since the data is applied to the load terminal LD of L2, the latch circuit L1 latches the second read obbligor data, and the latch circuit L2 latches the first obbrigade data latched by the latch circuit L1. Similarly, the pulse signal △PL is an OR circuit
Latch circuit L3 and L via OR10 and OR2
Since it is added to the load terminal LD of No. 4, the latch circuit L
3 latches the second read melody data, and latch circuit L4 latches the first melody data latched by latch circuit L3. The obligated data latched by the latch circuit L2 is applied to the end detection circuit 22, and
Of the obbligard data, pitch data TL1 is applied to the obbligado tone forming circuit 23, and note length data TL2 is applied to the A input of the comparator 24. The end detection circuit 22 detects the end of the data when all bits of the obbligard data (pitch data TL1 + note length data TL2) are "1", and outputs an end signal.
Output F1N. This end signal F1N is applied to the reset terminals R of the standby flip-flop FF1 and performance flip-flop FF2 via OR circuits OR8 and OR11, respectively, and resets the standby flip-flop FF1 and performance flip-flop FF2. This ends the automatic performance. The obbligado sound forming circuit 23 forms a musical sound signal corresponding to the obbligado sound indicated by the input pitch data TL1, and applies this to the speaker 19 via the amplifier 18 to generate the obbligado sound. Of the second melody data latched by the latch circuit L3, the pitch data TL1 is the key display device 1.
4, the key display device 14 lights up and displays the key of the second note of the melody performance. Note that this lighting display is performed in the same manner as in the case described above. Of the first melody data latched by the latch circuit L4, pitch data TL1 is applied to the melody tone forming circuit 25, and note length data TL2 is applied to the A input of the comparator 26. The melody sound forming circuit 25 forms a musical sound signal corresponding to the melody sound indicated by the input pitch data TL1, and applies this signal to the speaker 19 via the amplifier 18 to generate an automatic melody sound. Note that the key code KC is added to the melody sound forming circuit 17 based on the key pressed on the melody keyboard 4, and the pitch data TL1 is latched by the latch circuit L4 and added to the melody sound forming circuit 25 based on this key pressed. Of course, these are the same data. Therefore, it is preferable to make the manual melody sound and the automatic melody sound different tones, or to reduce the volume of the automatic melody sound. In addition, the play signal PL generated from the performance flip-flop FF2 is transferred to the inverters IN1 to IN5.
added to. As a result, the reset of the note length counters 11 and 12 and the address counter 13 is released and they can be counted. Also, flip-flop
There is no reset input from inverters IN3 and IN4 to each reset terminal R of FF3 and FF4. A tempo clock TCL is applied to each clock terminal CK of note length counters 11 and 12 and address counter 13 from a tempo pulse generating circuit 27 via an AND circuit A6. Note that the AND circuit A6 has the output signal (“0” in this case) from the flip-flop FF4 as the other input to the inverter IN.
6 is inverted and added, making it operable. Further, the tempo pulse generating circuit 27 generates a tempo clock TCL of an appropriate frequency to determine the tempo of automatic performance, the details of which will be explained later. The address counter 13 is connected to the tempo clock.
Count TCL and store the counted value in pattern memory 2
Pattern memory 2 as address signal for 8
Add to 8. The pattern memory 28 stores a plurality of bass patterns, chord patterns, and rhythm patterns for each rhythm. In this pattern memory 28, the above-mentioned pattern to be read is designated in advance in accordance with the rhythm selected by a rhythm selection switch (not shown), and the base pattern signal BP and the base pattern signal Read out the sound generation timing signal BT, chord tone generation timing signal CT, and rhythm pattern signal RP.
Here, the bass pattern signal BP is information indicating the pitch relationship to the root note of the automatic bass note to be produced (this root note is specified in relation to the keys pressed on the accompaniment keyboard 4), and timing signal
BT is a signal indicating the generation timing of the automatic bass tone, and the chord tone generation timing signal CT indicates the generation timing of the automatic chord tone (this chord tone is specified in relation to the keys pressed on the accompaniment keyboard 4). The rhythm pattern signal RP is information indicating the type of rhythm sound to be generated and the timing of its generation. The accompaniment sound forming circuit 29 adds the key code representing the root note of the automatic bass sound output from the accompaniment keyboard 3 and the bass pattern signal BP to form a key code representing the automatic bass sound, and adds this key code to the base pattern signal BP. to automatically form a musical tone signal corresponding to the bass tone,
This musical tone signal is used as the bass tone generation timing signal.
Open/close envelope control and output according to BT,
Also, a musical tone signal corresponding to the automatic chord tone is formed from the key code indicating the automatic chord tone outputted from the accompaniment keyboard 4, and this musical tone signal is outputted after being subjected to opening/closing envelope control according to the chord tone generation timing signal CT. . Musical tone signals representing these automatic accompaniment tones are applied to a speaker 19 via an amplifier 18, and are emitted as automatic accompaniment tones. Further, the rhythm pattern signal RP output from the pattern memory 28 is applied to the rhythm sound source circuit 30. The rhythm sound source circuit 30 generates rhythm sound signals representing various rhythm instrument sounds in accordance with the input rhythm pattern signal RP, and applies the signals to the speaker 19 via the amplifier 18 to generate automatic rhythm sounds. On the other hand, the note length counters 11 and 12 count the tempo clock TCL applied from the tempo pulse generation circuit 27 via the AND circuit 46, and use the counted value as note length data for the respective comparators 24 and 24.
and 26 to the B input. The comparator 24 has the code length data TL2 of the obligate data latched by the latch circuit L2 applied to its A input. In this case, the note length data TL2 applied to the A input of the comparator 24 is the note length data regarding the first note of the obbligado note, as is clear from the above explanation. The comparator 24 compares the note length data TL2 added to the A input with the count value of the note length counter 11 which started counting from the timing of the first key press, and when both data match and A=B, line l1 A pulse signal of signal “1” is output. This pulse signal is applied to the data write/read control circuit 7 via the OR circuit OR9, and advances the internal address counter by one step. As a result, the third data is read out from the obligate memory 5. In addition, this pulse signal is passed through OR circuits OR9 and OR1 to the load terminals of latch circuits L1 and L2.
In order to be added to the LD, the latch circuit L1 latches the third obbligor data read out, and the latch circuit L2 latches the second obbligate data latched by the latch circuit L1. Further, this pulse signal is applied to the reset terminal R of the note length counter 11 via the OR circuit OR3, and resets the note length counter 11. In this way, the obligate data is read out sequentially, and automatic obbligado performance is performed. In addition, when the melody data is read out, if the key press timing is earlier than the key press timing, the melody data is read out at the key press timing,
If the key press timing is later than the key press timing, reading is performed at the key press timing. Hereinafter, operations will be described when the key press timing for the second tone is earlier than the key press timing, when they match, and when the key press timing is later than the key press timing. (1) When the key press timing is earlier than the key press timing When the key press timing is earlier than the note length data TL2 latched by the latch circuit L4,
The count value of note length counter 12 is the above note length data.
The key press coincidence signal KEQ is generated before reaching TL2. Therefore, at the timing when the key press coincidence signal KEQ is generated, the line l is output from the comparator 26.
A signal “1” is generated at A 3 (the comparator 26
If the B input is smaller than the input, a signal “1” is output to line l3), key press coincidence signal
KEQ, the signal on line l3 and the rest detection signal RD from the rest detection circuit 16 are transferred to the inverter IN7.
(in this case, the rest detection signal RD
is assumed to be "0"), the output of the AND circuit A3 becomes "1". The output signal "1" of this AND circuit A3 is a flip-flop FF.
It is added to the set terminal S of 3, and the flip-flop
Set FF3. As a result, flip-flop FF3 applies a signal "1" from output terminal Q to AND circuit A7 via delay flip-flop DF2, thereby enabling AND circuit A7. The other input of the AND circuit A7 is a note length match obtained by differentiating the signal on line l2 output from the comparator 26 by the differentiating circuit 31 when the timing to press the key matches the timing to press the key (A=B). Signal LEQ is now added.
Therefore, the AND condition is satisfied at the time when A=B is established in the comparator 26 and the code length match signal LEQ is generated, and the AND circuit A7 outputs a signal "1" (pulse signal). This signal is applied to the data write/read control circuit 8 via the OR circuit OR10 and to the latch circuits L3 and L4 via the OR circuits OR10 and OR2 to read out the next melody data. Furthermore, the reset terminal R of the flip-flop FF3 has an OR circuit OR which takes the OR condition of the output of the AND circuit A7 and the output of the inverter IN3 which inverts the play signal PL.
In this case, the output of flip-flop FF is added by the output of AND circuit A7.
3 is reset. (2) When the key press timing matches the key press timing When the key press timing matches the note length data TL2 latched in the latch circuit L4,
At the same time as the key press coincidence signal KEQ, A=B is established in the comparator 26, and a signal "1" is generated on the line 12. This signal "1" is differentiated by the differentiating circuit 31 and outputted to the AND circuit A as the code length matching signal LEQ.
Added to 4. AND circuit A4 has an inverter IN8 which inverts the rest detection signal RD to the other input.
output and a key press coincidence signal KEQ are added. Therefore, the AND condition of the AND circuit A4 is satisfied, and a signal "1" (pulse signal) is outputted via the OR circuit OR10. This signal "1" causes the next melody data to be read. (3) When the key press timing is later than the key press timing When the key press timing is later than the note length data TL2 latched in the latch circuit L4,
Alternatively, if accurate key presses are delayed due to a mistouch, the counted value of the note length counter 12 reaches the above note length data before the key press coincidence signal KEQ is generated.
The comparator 26 establishes A=B, and the differentiation circuit 31 generates a code length match signal LEQ. This code length match signal LEQ is applied to AND circuit A8. AND circuit A8 connects inverter IN9 to the other input.
The output signal of the AND circuit A4 and the signal obtained by inverting the output of the AND circuit A4 by the inverter IN10 are added. In this case, the rest detection signal RD is "0" and the output of the AND circuit A4 is "0", so the AND circuit A8 The AND condition is satisfied and a signal "1" is output. The output of this AND circuit A8 is connected to the other input as the inverted output Q of the flip-flop FF3.
(in this case, it is "1") is applied to the set terminal S of the flip-flop FF4 via the AND circuit A9, which is enabled to operate. As a result, flip-flop FF4 is set and outputs a stop signal ST from output terminal Q. This stop signal ST is inverted by the inverter IN6 and applied to the AND circuit A6, which disables the AND circuit A6 and stops the output of the tempo clock TCL generated from the tempo pulse generation circuit 27, thereby temporarily halting the progress of the automatic performance. . Also, the stop signal ST output from flip-flop FF4 is output from delay flip-flop DF.
3 to the AND circuit A5. The AND circuit A5 is configured such that a key press coincidence signal KEQ is added to other inputs. Therefore, the AND condition of the AND circuit A5 is satisfied at the timing of the key press coincidence signal KEQ, and outputs a signal "1" (pulse signal) via the OR circuit OR10.
This signal "1" causes the next melody data to be read. Note that the output of the AND circuit A5 and the play signal are connected to the reset terminal R of the flip-flop FF4 which outputs the stop signal ST.
The output of the OR circuit OR6 which takes the OR condition of the output of the inverter IN4 which inverts PL is added. In this case, the flip-flop FF4 is reset by the output of the AND circuit A5, and the stop signal becomes "0". In the above operation description, it is assumed that the rest detection signal RD output from the rest detection circuit 16 is "0". However, if the rest detection signal RD is "1", the rest detection signal RD is The AND circuit A10, which takes an AND condition with the length match signal LEQ, outputs the code length data TL2, which is the counted value of the code length counter 12 latched in the latch circuit L4, at the timing when the code length match signal LEQ occurs, that is, in the comparison in the comparator 26. When it matches, OR circuit the signal “1” (pulse signal)
Output via OR10. This signal "1" causes the next melody data to be read. In this way, the melody data is sequentially read out, the keys to be pressed are displayed, and an automatic melody performance is performed. Furthermore, when the select switch 21 is switched and used, as long as a key is pressed on the melody keyboard 3, even if there is a mistouch (the key to be pressed and the pressed key do not match), the key press coincidence signal KEQ can be output.
Automatic performance can proceed. Next, the tempo pulse generation circuit 27 will be explained. The tempo pulse generating circuit 27 generates a tempo clock TCL of an appropriate frequency based on the interval at which the tempo setting switch 32 is pressed. first,
When setting the tempo, turn the tempo setting switch 3 at desired intervals, for example, for each beat, which is the unit of time signature.
Press 2. In addition, this tempo setting switch 3
2 consists of a self-resetting switch. When the tempo setting switch 32 is pressed, a signal "1" is applied to the differentiation circuit 33 each time the tempo setting switch 32 is pressed. The differentiating circuit 33 takes the rising edge differential of the input signal "1" and outputs it as the signal TSW to the tempo pulse generating circuit 27.
Add to. FIG. 2 is a block diagram showing one embodiment of the tempo pulse generating circuit 27, in which the signal TSW is applied to delay flip-flops DF4 and DF8. When the first signal TSW is input, all bits of the counter 34 are "1", and the NAND circuit NA, which takes the NAND condition of each bit output of the counter 34, outputs a signal "0". As a result, AND circuits A11 to A14 are rendered inoperative. Delay flip-flops DF4 and DF8 each convert input signal TWS into high-speed clock pulse φ.
The delay flip-flops DF5 and DF9 of the next stage are outputted with a delay of a time interval of
10, delay flip-flop DF6 and
Each DF10 is a day-lay flip-flop DF.
7 and the reset terminal R of the counter 34, the signal TSW is delayed by the time interval of the high speed clock pulse φ and output. Counter 35 is a delay flip-flop DF
It is reset by the signal TSW applied from 10,
Counter 34 is a delay flip-flop DF7
Then, it is reset by the signal TSW which is further delayed by a time interval of one clock pulse φ. When the counter 34 is reset, the NAND circuit NA which takes the NAND condition of each bit output of the counter 34 outputs a signal "1", thereby enabling the AND circuits A11 to A14. Here, when the second signal TSW is applied based on the depression of the tempo setting switch 32, this signal TSW is applied to the delay flip-flops DF4 and DF8, and is also applied to the load of the latch circuit L5 via the AND circuit A12. Added to terminal LD. As a result, the latch circuit L5 becomes the latch circuit L5.
6 and outputs this information to the average value calculation circuit 36. Similarly,
The latch circuit L6 is a delay flip-flop
The signal TSW delayed by the time interval of one clock pulse in DF8 is input to the load terminal LD via the AND circuit A13, the information latched in the latch circuit L7 is latched, and this information is sent to the average value calculation circuit 36. and latch circuit L7.
are delay flip-flops DF8 and DF9
The signal TSW delayed by a time interval of two clock pulses is inputted to the load terminal LD via the AND circuit A14, and the counted value of the counter 35 (indicating the time interval between the first signal TSW and the second signal TSW) is input to the load terminal LD of the AND circuit A14. information) and outputs this information to the average value calculation circuit 36. Note that the counters 34 and 35 are reset in the same manner as described above. In addition, the counter 34
This is to prevent information corresponding to the time interval from being captured when the time interval of the signal TSW exceeds a predetermined time (the longest beat interval that can be considered short). That is, as described above, all bit outputs of the counter 34 become "1" in the above case, and the AND circuits A11 to A14 are rendered inoperable. The average value calculation circuit 36 includes latch circuits L5, L6,
The average value of the numerical information added from L7 is calculated, and this average value is output to the variable frequency divider 37. The variable frequency divider 37 generates a tempo clock TCL by frequency-dividing the high speed clock pulse φ using the input average value as frequency division ratio data. Therefore, the tempo clock TCL that occurs when the pressing interval of the tempo setting switch 32 becomes longer.
The frequency of the tempo clock TCL may become lower, and the frequency of the generated tempo clock TCL may become higher as the press interval becomes shorter. That is, the tempo clock is set at an appropriate frequency based on the interval at which the tempo setting switch 32 is pressed.
It can generate TCL, which allows you to control the tempo of automatic performance. In this embodiment, the average value of three pieces of numerical information is calculated, and the tempo clock is set based on this average value.
Since the TCL frequency is determined, if you want to set the tempo before playing, use the tempo setting switch 32.
It is preferable to press at least four times or more.
It is also possible to change the tempo at any point during the performance, and the tempo can be changed by pressing the tempo setting switch 32 two or more times. FIG. 3 is a block diagram showing another embodiment of the tempo pulse generation circuit 27.
Before playing, the tempo is determined based on the operation on the tempo setting device 38, and during the performance, when the pitch of the melody changes (when the note length matching signal LEQ is output), the tempo setting switch 32 (see Fig. ) from the pressing timing to the note length match signal LEQ and tempo setting switch 3
Measure the deviation from the signal TSW based on the pressure in step 2,
The tempo is corrected based on this measured value. As shown in FIG. 1, when the code length data TL2 and the counted value of the note length counter 12 match in the comparator 26 (A=B), the code length match signal LEQ is output from the differentiating circuit 31 to a line l4 shown by a broken line. The signal TSW is applied to the tempo pulse generation circuit 27 via the differential circuit 33 when the tempo setting switch 32 is pressed.
is applied to the tempo pulse generation circuit 27. In FIG. 3, the operation will be described when the code length matching signal LEQ is input as a pulse train shown in FIG. 4a, and the signal TSW is input as a pulse train shown in FIG. 4d. The one-shot circuit 39 is a note length match signal.
By inputting LEQ, a pulse signal with a pulse width T is output to line l6 (Fig. 4c), and the inverter IN
11 is the inverted output of the output of line l6 to line l5
(Figure 4b). Similarly, the one-shot circuit 40 receives the signal TSW to generate a pulse width T.
A pulse signal of is outputted to line l8 (Fig. 4 f),
Inverter IN12 outputs the inverted output of line l8 to line l7 (FIG. 4e). The AND circuit A15 takes an AND condition between the code length match signal LEQ and the signal generated on the line 17, and in this case, outputs a pulse signal "1" at the time the code length match signal LEQ1 is output (Fig. 4g). . The AND circuit A16 takes an AND condition between the signal TSW and the signal generated on the line 15, and in this case,
A pulse signal "1" is output at the time when the signal TSW2 is output (Fig. 4h). Also, the AND circuit A17 outputs the code length match signal LEQ.
In this case, a pulse signal "1" is output at the time when the note length match signal LEQ2 is output (FIG. 4i).
The AND circuit A18 takes the AND condition of the signal TSW and the signal generated on the line l6, and in this case, the pulse signal "1" is output when the signal TSW1 is output.
(Fig. 4 j). The outputs of AND circuits A15 and A16 are applied to reset terminal R of counter 41 via OR circuit OR11 to reset counter 40. The outputs of AND circuits A17 and A18 are applied to latch circuit L8 and delay flip-flop DF11 via OR circuit OR12, and the output of AND circuit A18 is applied to delay flip-flop DF11.
It is also becoming possible to add it to DF13. When a pulse signal is applied to the latch circuit L8 through the OR circuit OR12 to its load terminal LD,
The information latched in the latch circuit L9 is latched and this information is added to the A input of the average value calculation circuit 42. The latch circuit L9 inputs the pulse signal delayed by the time interval of one clock pulse by the delay flip-flop DF11 to its load terminal LD, latches the information latched in the latch circuit L10, and averages this information. It is added to the B input of the arithmetic circuit 42. The latch circuit L10 inputs the pulse signal delayed by the time interval of two clock pulses by the delay flip-flops DF11 and DF12 to its load terminal LD,
(information indicating the time interval from when the counter 41 is reset by the output of the AND circuit A15 or A16 to when the latch circuit is activated by the output of the AND circuit A17 or A18), and the delay is flip flop
The output of the AND circuit A18, which is delayed by a time interval of two clock pulses by DF13 and DF14 and inverted by the inverter IN13, is latched as sign information, and this information is added to the C input of the average value calculation circuit 42. Note that when the code information is "0" (when the output of the AND circuit A18 is "1"), the deviation of the signal TSW from the code matching signal LEQ is "negative", that is, from the output timing of the code length matching signal LEQ. also indicates that the output timing of the signal TSW is delayed, and when the code information is "1", it indicates that the deviation of the signal TSW with respect to the code length matching signal LEQ is "positive". Therefore, the note length match signal LEQ and the signal
When TSW is input at the timing shown in FIG. 4a and FIG. 4d, the latch circuit L10 first latches the information corresponding to the negative deviation _t1 , and then the information corresponding to the positive deviation _t2. Latch. The average value calculation circuit 42 includes latch circuits L8, L9,
The average value of the numerical information added from L10 is calculated, and this average value is output to the tempo oscillator 42 as correction data for the frequency of the tempo clock TCL. The tempo oscillator 43 has a variable frequency divider, and before performance, frequency division ratio data corresponding to the tempo set by the tempo setting device 38 is inputted from the tempo setting device 38, and based on this frequency division ratio data, high speed A tempo clock TCL is generated by frequency dividing the clock pulse, and when the correction data is added from the average value calculation circuit 42 based on the pressing timing of the tempo setting switch 32 during performance, the correction data is generated from the frequency division ratio data. The tempo clock TCL is generated by subtracting , and using this as new frequency division ratio data to divide the high speed clock pulse. Therefore, when the correction data is positive (when the average value of the deviations is positive), the frequency of the tempo clock TCL becomes higher and the tempo of automatic performance becomes faster. If the correction data is negative, the frequency of the tempo clock TTCL will be lower, and the tempo of automatic performance will be slower. As explained above, according to the present invention, when the operation timing is delayed with respect to the timing when the operation should be performed, the automatic performance is temporarily stopped, thereby making it possible to match the progress of the keyboard performance and the automatic performance.
It is also possible to temporarily stop the automatic performance if you hit a key incorrectly, which can be expected to be very effective for practicing keystrokes on the keyboard. Further, since the tempo can be set or changed by the timing of pressing the tempo setting switch, the tempo of automatic performance can be easily set to a desired tempo.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the tempo pulse generating circuit according to the present invention, and FIG. 3 is a block diagram showing an embodiment of the tempo pulse generating circuit according to the present invention. FIG. 4 is a timing chart used to explain the operation of FIG. 3. 1...Score, 2...Data reading device, 3...Accompaniment keyboard, 4...Melody keyboard, 5...Obligado data memory, 6...Melody data memory, 7, 8...Data writing/reading control circuit, 11,
12... Note length counter, 13... Address counter, 14... Key display device, 15, 24, 26...
Comparator, 17, 25... Melody sound forming circuit, 2
3...Obligado sound forming circuit, 27...Tempo pulse generation circuit, 28...Pattern memory, 29
... Accompaniment sound formation circuit, 30 ... Rhythm sound source circuit,
32...Tempo setting switch, 34, 35, 41
... Counter, 36, 42 ... Average value calculation circuit,
37... Variable frequency divider, 38... Tempo setter, 4
3... Tempo oscillator.

Claims (1)

[Scope of Claims] 1. A keyboard, storage means for storing at least note length data, tempo clock generation means for generating a tempo clock for advancing automatic performance, reading means for sequentially reading out the note length data from the storage means, and the above. The timing at which the keyboard should be operated, which is indicated by the note length data read by the reading means, is compared with the operation timing of the keyboard, and if the operation timing is earlier than the timing at which the keyboard should be operated, the operation is performed. The reading means is controlled so as to wait until the desired timing and then read out the note length data from the storage means, and if it is too late, the progress of the automatic performance is temporarily stopped from the desired timing to the operating timing, and an automatic performance device comprising: control means for controlling the reading means to read note length data from the storage means in synchronization with operation timing. 2. The tempo clock generating means comprises: a tempo setting switch; and means for generating a tempo clock at a frequency corresponding to the reference interval, using the pressing interval of the tempo setting switch as a reference interval. Automatic performance device. 3. The tempo clock generation means includes a tempo setting switch, a tempo setting means, and a tempo oscillator, and the tempo oscillator determines the oscillation frequency of the initial tempo clock based on the output of the tempo setting means, and 2. The automatic performance apparatus according to claim 1, wherein the oscillation frequency of the initial tempo clock is corrected based on the difference between the timing at which the tempo setting switch should be pressed and the timing at which the tempo setting switch is pressed. 4. The storage means stores pitch data together with the note length data, and the pitch data is read out by the readout means and added to a pressed key display device to display the key to be pressed. An automatic performance device according to claim 1. 5. The automatic performance device according to claim 1, wherein the control means temporarily stops the progress of the automatic performance by prohibiting generation of the tempo clock from the timing at which the operation is to be performed to the operation timing. 6. The automatic performance device according to claim 1, wherein the automatic performance includes at least one of automatic rhythm performance, automatic chord performance, automatic bass performance, automatic rhythm performance, and automatic obbligato performance.