JPH0157917B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument that controls the tempo of automatic performance. Conventionally, music data such as a melody is stored, and the music data is sequentially read out by counting the tempo clock that advances automatic performance, and the performance timing of the read music data and the keyboard of the key corresponding to the music data are determined. When the key press timing is later than the performance timing, generation of the tempo clock is stopped, and the frequency of the tempo clock is controlled by tempo correction data related to the earlier or later key press timing. An electronic musical instrument in which the progression of musical performance and automatic performance are matched by key depression is known from Patent Application No. 78784 filed in 1981. However, with such conventional electronic musical instruments, if the key press timing deviates significantly due to a key press error or the like during a performance, the subsequent tempo changes too much, and it takes a very long time to recover. It took a while. This invention was made in view of the above circumstances.
To provide an electronic musical instrument that can restore the tempo in a short time when the tempo is delayed and is easy for beginners to use. Therefore, the present invention detects when the performance operation means is playing quickly, and when the tempo is rising, the tempo correction data is adjusted according to the tempo correction data measured in response to the performance operation using the performance operation means. The degree of tempo correction (tempo correction contribution rate) is made high. The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument to which the present invention is applied. In FIG. 1, a keyboard 1 has a key switch for each key that is linked to key operations, and depending on the pressed key, the key switch corresponding to that key is turned on. The pressed key detection circuit 2 scans the key switch, detects a key switch that is turned on, that is, a pressed key, and outputs key information (key code) KC representing that key in a time-division manner, and also detects that the key is pressed. Outputs the key-on signal KON of the binary level shown. The key code KC is, for example, as shown in Table 1, 2-bit octave codes B ₂ , B ₁ representing the octave range, and 4-bit note codes N ₄ , N ₃ , N representing the 12 note names within one octave. It is a 6-bit binary coded signal consisting of ₂ and _N1 .

【table】

[Table] Key code KC output from key press detection circuit 2
The key-on signal KON is applied to the sound generation channel assignment circuit 3 and the melody pitch data extraction circuit 4. The pronunciation channel allocation circuit 3 receives, as other inputs, obbligado pitch data ON outputted from a chord/obligado data extraction circuit 200, which will be described later, and a plurality of key codes indicating chord constituent tones outputted from the subordinate tone forming circuit 5. CKC and bass sound forming circuit 6
Key code BKC indicating the bass sound output from
is added. The subordinate tone forming circuit 5 receives the chord name data CH output from the chord/obligado data extraction circuit 200.
Multiple key codes indicating chord constituent notes based on
Form CKC. Note that the chord name data CH is a 6-bit binary code consisting of 4-bit data indicating the note name of the root note of the chord (see Table 1) and 2-bit data indicating the type of chord (major, minor, seventh). be. To show an example of key code CKC formation in the subordinate tone forming circuit 5, when the chord type is major, the key code CKC indicating the pitch relationship of perfect 1st, major 3rd, and perfect 5th to the root note is given. When the chord type is minor, the key code CKC is formed, which indicates a note that has an interval relationship of perfect 1st, minor 3rd, or perfect 5th to the root note, and when the chord type is 7th, the key code CKC is formed. A key code CKC is formed that indicates the pitch relationship of a perfect 1st, a major 3rd, and a minor 7th. The bass tone forming circuit 6 receives chord name data output from the chord/obligado data extraction circuit 200.
A key code BKC indicating a bass tone is formed based on the CH and the bass pattern signal BP output from the automatic accompaniment pattern signal generation circuit 7. The automatic accompaniment pattern signal generation circuit 7 will now be explained. The automatic accompaniment pattern signal generation circuit 7 generates a chord sound generation timing signal CT, a bass sound sound generation timing signal BT, and a rhythm pattern signal corresponding to the rhythm selected by a rhythm selection switch (not shown).
A tempo clock output from a tempo control circuit 300, which will be described later, includes RP and base pattern signal BP.
It is generated by TCL and consists of a pattern memory and an address counter. The pattern memory stores a plurality of chord sound generation timing patterns, bass sound sound generation timing patterns, rhythm patterns, and bass patterns for each rhythm. The patterns for each rhythm stored in this pattern memory are selected by a rhythm selection switch, and each of the selected patterns is sequentially read out using the count value of an address counter that counts the tempo clock TCL as an address signal. In addition, the chord pronunciation timing signal CT
and bass sound generation timing signal BT are signals indicating the generation timing of automatic chord sound and automatic bass sound, respectively, and rhythm pattern signal RP
is a signal indicating the type of rhythm tone to be generated and its generation timing, and the base pattern signal BP is a signal indicating the pitch relationship corresponding to the root tone of the automatic bass tone to be generated. The bass tone forming circuit 6 inputs chord name data.
By adding the key code indicating the root note of the chord among the CHs and the base pattern signal BP, a key code BKC indicating the base note having a predetermined interval relationship with the root note is formed. In addition, when the base pattern signal BP corresponds to the interval of a major third, and the chord type of the chord name data CH is minor, the base tone forming circuit 6 makes the base pattern signal BP correspond to the interval of a minor third. Correct and add as follows. The sound generation channel assignment circuit 3 is connected to the key press detection circuit 2.
A channel to which the key code KC outputted from is exclusively assigned, and obbligado pitch data outputted from the chord/obligado data extraction circuit 200.
A channel to which ON is exclusively assigned, and a key code indicating the chord constituent notes output from the subordinate tone forming circuit 5.
It has a predetermined number of sound generation channels consisting of a channel exclusively assigned to CKC and a channel exclusively assigned to key code BKC indicating the bass sound output from the bass sound forming circuit 6, and each of the above key codes is assigned to these sound generation channels. The key code KC ^* assigned to each channel and stored as appropriate is outputted to the musical tone forming circuit 8 in a time-sharing manner. The musical tone forming circuit 8 forms musical tone signals based on the key code KC ^* applied from the sound generation channel allocation circuit 3 in a time-sharing manner. Note that the musical tone signal formed based on the key code KC output from the key press detection circuit 2 is subjected to opening/closing envelope control by the key-on signal KON output from the key press detection circuit 2.
Furthermore, the musical tone signals formed based on the key code CKC indicating the chord component tones and the key code BKC indicating the bass tone are respectively a chord generation timing signal CT and a bass tone generation timing generated from the automatic accompaniment pattern signal generation circuit 7. signal BT
The opening/closing envelope is controlled based on The musical tone signal formed by the musical tone forming circuit 8 is amplified by an amplifier 9 and applied to a speaker 10, where it is produced as a melody tone, chord, bass tone, or obbligato tone. Further, the rhythm sound source circuit 11 generates rhythm sound signals indicating various rhythm sounds according to the rhythm pattern signal RP generated from the automatic accompaniment pattern signal generation circuit 7, and transmits the rhythm sound signals to the speaker 1 via the amplifier 9.
In addition to 0, make it sound as a rhythm sound. Next, tempo control for automatic performance of an electronic musical instrument will be explained. First, the data format of the automatic performance data output from the external recording means 12 will be explained. The external recording means 14 is a magnetic card/tape, a punch card, a bar code, etc., and as shown in FIG. The data is recorded in the form of serial data in the order in which it is written. Note that mark data DM ₁ to _{DM 5} for identifying each data is recorded at the head of each data. The melody pitch data and obbligado pitch data each indicate pitch, and are composed of 6-bit binary codes (see Table 1).
The melody note length data and obbligado note length data each indicate the length of a note or rest, that is, the note length, and are composed of 6-bit binary codes. An example of note length data is shown in Table 2.

[Table] The chord data includes chord name data indicating the name of the chord to be generated and timing data indicating the chord generation timing, and is composed of 6-bit and 10-bit binary codes, respectively. Note that the chord name data is read out in conjunction with the reading of the obbligado pitch data, and the timing data is used when the obbligado pitch data of the obbligado notes to be sounded at the same time is transferred to the data memory 14, which will be described later. This corresponds to the storage address in the data memory 14 after the above. Each of the above data recorded in the external recording means 12 is read by the music data input device 13 in the form of serial data. The music data input device 13 converts the read serial data into parallel data, and outputs melody pitch data, melody note length data,
Obrigado pitch data, obbrigado note length data, and chord data are supplied to the data memory 14, and write control data including mark data DM ₁ to _{DM 5} is supplied to a RAM (random access memory) write control circuit 15. supply to. The data memory 14 has a storage area for each data group, and writing to and reading from the corresponding storage area of each data group is performed by five counters 16a to 16a that output address signals corresponding to each storage area.
This is done by the address counter 16 consisting of 16e. The RAM write control circuit 15 controls writing of each data group supplied from the music data input device 13 to the data memory 14 for each storage area corresponding to each data in the data memory 14. When the mark data DM ₄ is input, the counter 16a of the address counter 16 corresponding to the storage area of the melody pitch data is enabled, and the counter 16a is activated every time the melody pitch data is sent from the music data input device 13.
Count up a. The counter 16a uses the counted value as an address signal to the data memory 14.
and writes the melody pitch data to the address indicated by the address signal. Incidentally, the RAM write control circuit 15 initializes the counter 16a at the same time as inputting the mark data _DM1 so that the address signal of the counter 16a indicates the first address of the storage area of the melody pitch data. When all the melody pitch data has been written in this way, the RAM write control circuit 15 inputs the mark data DM ₂ and stores it in the storage area corresponding to the melody note length data in the data memory in the same manner as described above. Melody note length data is written from the first address of the storage area. Below, RAM write control circuit 1
5 writes obbligado pitch data, obbligado note length data, and chord data to the storage area corresponding to the mark data from the first address of the storage area every time mark data DM ₃ , DM ₄ , DM ₅ is input. . Next, a case will be described in which the start switch 17 is turned on after all automatic performance data has been written into the data memory 14. When the start switch 17 is turned on, the RAM
The read control circuit 18 initially resets the address counter 16 so that each counter in the address counter 16 indicates the start address of the corresponding storage area, and then reads the first and second notes of the melody from the data memory 14. The address counter 16 is controlled to sequentially read out the melody pitch data and melody note length data corresponding to the first note of the obbligado, and the obbligado pitch data and obbligado note length data corresponding to the first note of the obbligado. That is, the RAM read control circuit 18 reads the counter 1 of the address counter 16 corresponding to the storage area of the melody pitch data and the melody note length data.
6a and 16b are enabled, and each counter 16 is
Based on the address signals of melody a and 16b, melody pitch data and melody note length data corresponding to the first note of the melody are read from the data memory 14, and then each counter 16a and 16b is counted up to read the melody pitch data and melody note length data corresponding to the first note of the melody. The melody pitch data and melody note length data corresponding to are read out. Similarly, the counters 16c and 16d of the address counter 16 corresponding to the storage areas of the obbligado pitch data and the obbligado note length data are made operable, and the counters 16c and 16d are incremented.
Read obbligado pitch data and obbligado note length data corresponding to the note. Note that the RAM read control circuit 18 outputs the next melody read request signal every time the counters 16a and 16b of the address counter 16 are counted up.
MNR is output, and each time the counters 16c and 16d of the address counter 16 are counted up, the next obligate read request signal ONR is output.
Further, the RAM read control circuit 18 drives the counter 16e of the address counter 16 corresponding to the storage area of the chord data at high speed, and reads out all the chord data from the data memory 14 when reading the obbligado pitch data and obbligado note length data. Read out. The data output circuit 19 includes a chord search circuit 19a, and outputs obbligado pitch data ON1, obbligado note length OL1, and chord name data CH1 out of each data read from the data memory 14 to a chord/obbligado extraction circuit 200. The melody pitch data MN2 and melody note length data ML2 are output to the melody data extraction circuit 100. Note that the chord search circuit 19a uses the address counter 1 when reading the obligado pitch data.
Based on the address signal output from the counter 16c of 6, the timing data of the chord data indicating the same address as the address signal is searched from among the chord data read out at high speed from the data memory 14, and the timing data of the chord data indicating the same address as the address signal is searched. Output chord name data CH1. Melody data retrieval circuit 100 receives melody pitch data MN2 and melody note length data ML2 from data output circuit 19, receives next melody read request signal MNR from RAM read control circuit 18, and receives tempo clock from tempo control circuit 300, which will be described later. TCL is added, and the melody pitch data MN of the melody note (melody note leading by one note) to be played based on these signals.
1. The melody note length data ML of the melody note being played, the stop command signal MP used to stop the output of the tempo clock from the tempo control circuit 300, and the melody data (melody pitch data and This is to extract the read command signal MLU of the melody note length data). FIG. 3 shows a detailed configuration example of the melody data retrieval circuit 100. When the next melody read request signal MNR is applied from the RAM read control circuit 18 in conjunction with reading melody data, the latch circuits 101 and 102 latches the melody pitch data MN2 and melody note length data ML2 that are added from the data output circuit 19, respectively, and the latch circuit 104 latches the melody note length data ML1 that was previously latched by the latch circuit 102, and outputs the melody note length. Counter 105 is reset. Immediately after the start switch 17 is turned on, the signal MNR is output once as two pieces of melody data are read, so the melody pitch data MN1 and the melody note length data latched by the latch circuits 101 and 102 are
ML1 corresponds to the first note of the melody that is about to be played, and the latch circuit 104 latches non-note length data (all "0"). The melody pitch data MN1 latched by the latch circuit 101 is applied to the tempo control circuit 300 and the display device 20, and the melody note length data ML1 latched by the latch circuit 102 is applied to the tempo control circuit 300 and the display device 20.
04 and latched by the latch circuit 104 is applied to the B input of the comparator 106 and the tempo control circuit 300. The display device 20 is composed of lamps arranged for each key, and displays the key to be pressed by lighting the lamp corresponding to the input melody pitch data MN1. Therefore, the display device 20 displays the first part of the melody based on the melody pitch data MN1.
The keys corresponding to the notes are displayed by lighting. The comparator 106 has the parallel output of the upper bits excluding the lower 2 bits from the melody note length counter 105 that counts the tempo clock TCL added to the A input as note length data, and each note length added to the A and B inputs. The data are compared, and when they match, a melody note length matching signal MLEQ is output. In this case, since the melody note length counter 105 is reset by the signal MNR and outputs non-note length data (after being reset, three tempo clocks TCL are added to the melody note length counter 105, but the fourth tempo clock TCL is stopped by a stop command signal MP (see FIG. 4 d) to be described later), the comparator 106 applies a coincidence signal MLEQ (“1”) (see FIG. 4 c) to the AND circuit 107, The AND circuit 107 is enabled. The melody note length counter 105 inputs three tempo clocks TCL after being reset (see FIG. Outputs signal “1”. Therefore, the AND circuit 107 is the melody note length counter 1
The command signal MP to stop the signal "1" until the fourth tempo clock TCL is applied to 05 (Fig. 4d)
It is outputted to the tempo control circuit 300 as (see) and also outputted to the AND circuit 109. Here, the melody performance for the first note of the melody is performed at the performance time t _KON (see Figure 4b),
When the fourth tempo clock TCL is output from the tempo control circuit 300 after resetting the note length counter 105, the AND circuit 109 converts this tempo clock TCL into a melody data read command signal MLU.
(See FIG. 4e) as the RAM read control circuit 18.
Output to. The RAM read control circuit 18 receives a read command signal MLU
When the address counter 16 is inputted, the counters 16a and 16b of the address counter 16 are immediately counted up, the melody data corresponding to the third note of the melody is read out from the data memory 14, and the next melody read request signal MNR (see Fig. 4 f) is issued. Output. As a result, the latch circuits 101 and 102 respectively output melody pitch data MN1 and melody note length data ML corresponding to the second note of the melody.
1, and the latch circuit 104 outputs the first melody.
Outputs melody note length data ML corresponding to the note. The display device 20 illuminates the key to be pressed next based on melody pitch data MN1 corresponding to the second note of the melody output from the latch circuit 101, and the comparator 106 connects the B input to the latch circuit 104.
The melody note length data ML corresponding to the first note of the melody output from the melody is input. The comparator 106 has note length data corresponding to the time after the melody performance time t _KON added to the A input from the melody note length counter 105, and from the time t ₀ when these note length data match, the process starts as described above. Outputs the melody note length matching signal MLEQ (5th
(see figure c). Then, the AND circuit 107 outputs the signal
After MLEQ is output, the tempo control circuit 300
When the third tempo clock TCL is output to the melody note length counter 105, a stop command signal MP is output.
(see FIG. 5d), and when the fourth tempo clock TCL is output, the AND circuit 109 outputs a read command signal MLU (see FIG. 5e). In addition, as shown in FIG. 5b, if the performance time _tKON is earlier than the coincidence time _t0 , the melody coincidence signal
MKEQ prevents the fourth and subsequent tempo clocks TCL after the coincidence time _t0 from being stopped. In this way, the melody data extraction circuit 100
extracts, for each melody performance, melody pitch data MN1 of the melody note that precedes by one note, melody note length data ML of the melody note being played, a stop command signal MP, and a melody read command signal MLU. The chord/obligado data extraction circuit 200 is
Obligado pitch data from data output circuit 19
ON1, obbligard note length data OL1, and chord name data CH1 are added, the next obbligard read request signal ONR is added from the RAM read control circuit 18, and a tempo clock TCL is added from the tempo control circuit 30, which will be described later. The melody data retrieval circuit 100 based on the signal of
Obbligado pitch data ON of automatically played obbligado notes in the same way as above, chord name data CH corresponding to automatically played chords and bass notes, and obbligado data (obligado pitch data) from data memory 14 and obbligard code length data). FIG. 6 shows a detailed configuration example of the above-mentioned chord/obligard data retrieval circuit 200. When the next obbligard read request signal ONR is applied from the RAM read control circuit 18 in conjunction with reading of obbligard data, the latch circuit 201, 202 and 2
03 are obbligado pitch data ON1 and chord name data added from the data output circuit 19, respectively.
CH1 and obbligard code length data OL1 are latched, and obbligate code length counter 204 is reset by this signal ONR. In addition, immediately after the start switch 17 is turned on, the signal
Since ONR is not output, latch circuit 20
1 and 203, the obbligado pitch data ON1 and obbligado note length data OL1 corresponding to the first note of obbligado are not latched,
In addition, the latch circuit 202 uses chord name data indicating the chord to be sounded together with the first note of the obbligado.
CH1 is also not latched. Latch circuit 203
In this case, unsigned length data (all "0") is latched. The obligate code length data OL (unsign length data) latched by the latch circuit 203 is sent to the comparator 205.
is added to the B input of To the A input of the comparator 205, the parallel output of the upper bits excluding the lower 2 bits from the obligate mark length counter 204 for counting the tempo clock TCL is added as mark length data. Comparator 205 compares each code length data applied to A input and B input, and outputs an obligate match signal OLEQ when they match. Since the obbrigade note length counter 204 outputs non-note length data similarly to the melody note length counter 105, the comparator 205 applies the coincidence signal OLEQ to the AND circuit 206 to enable the AND circuit 206. . The obbrigade mark length counter 204 inputs three tempo clocks TCL after being reset, and the outputs of the lower two bits are both "1", so the AND circuit 207 outputs the signal "1" via the AND circuit 206. Output. Here, when the melody corresponding to the first note of the melody is played and the fourth tempo clock TCL is output from the tempo control circuit 300 after resetting the note length counter 204, the AND circuit 208
outputs this tempo clock TCL to the RAM read control circuit 18 as an obligate data read command signal OLU. When the RAM read control circuit 18 receives the read command signal OLU, the counter 1 of the address counter 18
Immediately count up 8c and 18d and read the obbligado data corresponding to the second note of obbligado from the data memory 14,
Outputs the next obligate read request signal ONR. In response to this signal ONR, the latch circuit 201 latches obbligado pitch data ON1 corresponding to the first note of obbligard, and outputs this as obbligado pitch data ON. This obligate pitch data ON is added to the aforementioned sound channel assignment circuit 3 (Figure 1), so the speaker 1
At 0, the first obbligado sound is produced.
The latch circuit 202 also contains chord name data indicating the chord to be sounded with the first note of the obbligado.
CH1 is latched, and this is output as chord name data CH to the subtone forming circuit 5 and base tone forming circuit 6, and the latch circuit 203 latches obbligado note length data OL1 corresponding to the first note of the obbligado. , this is output to the B input of the comparator 205 as the note length data OL of the currently played obbligado note. Further, the obligatory code length counter 204 is reset by the signal ONR. The comparator 205 has the note length data OL added to its B input, and the obligate note length counter 204 to its A input.
The note length data corresponding to the time after the reset is added from , and when these note length data match, the obligate note length match signal OLEQ is sent as before.
Output. Then, the AND circuit 206 outputs the signal
After OLEQ is output, when the third tempo clock TCL is output from the tempo control circuit 300 to the obligate note length counter 204, the AND circuit 208 is enabled, and the AND circuit 208 outputs the fourth tempo clock TCL. Then, this tempo clock TCL is output as a read command signal OLU. In this way, when the tempo clock TCL is output from the tempo control circuit 300 where the melody performance was performed, the chord/obligado data retrieval circuit 200 receives the obbligado pitch data.
ON, chord name data CH, and obligate data read command signal OLU are taken out. The tempo control circuit 300 receives the melody pitch data MN1, melody note length data ML, and stop command signal MP from the melody data retrieval circuit 100, receives the next melody read request signal MNR from the RAM read control circuit 18, and further receives the melody pitch data MN1, melody note length data ML, and stop command signal MP from the melody data retrieval circuit 100. Melody pitch data MMN based on the keys pressed on the keyboard 1 is added from the pitch data extraction circuit 4, and based on these signals, the generation of the tempo clock TCL is controlled to be stopped, and the tempo clock is
This controls the TCL frequency. Note that the melody pitch data extraction circuit 4 is connected to the key press detection circuit 2.
Of the key codes KC input in a time-sharing manner from
Only the key code KC input at the rising edge of the key-on signal KON is extracted as melody pitch data MMN. FIG. 7 shows a detailed configuration example of the tempo control circuit 300. The selection switch 301 selects a melody matching signal.
It selects the rising condition of MKEQ, and the contacts 301a, 301b, and 301c of the selection switch 301 have the output of the OR circuit 303, respectively.
The output of comparator 304 and the output of differentiator circuit 306 are added. Since the OR circuit 303 takes the OR condition of the melody pitch data MMN (6-bit binary code (see Table 1)), when any key on keyboard 1 is pressed (any key on), a signal is generated at the time of the key press. Outputs “1”. In addition,
The key range of keyboard 1 does not include keys corresponding to key codes in which all 6 bits are "0". Comparator 30
4 is the melody pitch data of the note that precedes it by one note.
Melody pitch data MMN indicating the pressed key on MN1 and keyboard 1 is now added.
When these pitch data match, that is, when a proper key is pressed on the keyboard 1, a signal "1" is output. When the self-resetting switch 305, which is a key switch other than the keyboard 1, is turned on and a signal "1" is input, the differentiating circuit 306 takes the differential of the rising edge of this signal "1" and outputs it to the contact 501c.
Note that the self-resetting switch 305 is used during one-key play. Therefore, when the selection switch 301 is connected to the movable contact piece 301d and the contact 301a, the keyboard 1
When any key is pressed, a signal "1" is output. When connected to the contact 301b, a signal "1" is output when a key press matches. When connected to the contact 301c, the self-resetting switch 305 is turned on. outputs a signal “1” at times. Signal “1” output from selection switch 301
is applied to the AND circuit 308 via the OR circuit 307. Other inputs of the AND circuit 308 include
The output of an inverter 309 that inverts the next melody read request signal MNR is added, but the next melody read request signal MNR is output immediately after the melody read command signal MLU as shown in FIGS. 4f and 5f. Therefore, the AND circuit 308 is enabled to operate when a melody match is detected. Therefore, the signal "1" output from the selection switch 301 is applied to the D flip-flop 310 via the OR circuit 307 and the AND circuit 308. The D flip-flop 310 delays the input signal "1" by a predetermined time and outputs it as a melody coincidence signal MKEQ ("1"). This melody match signal MKEQ is fed back to the D flip-flop 310 via the OR circuit 307 and the AND circuit 308, so it is held until the next melody read request signal MNR is output ((Fig. 4b and 5). (see b).Next, the operation of the tempo control circuit 300 will be explained.Before starting automatic performance, the latch circuit 31
3, 314 and 315 each latch the frequency information (tempo data) of the reference tempo clock. Further, the counter 323 is preset so that the counted value matches the tempo data. The tempo data latched by the latch circuits 314 and 313 are applied to the A and B inputs of the arithmetic circuit 312 and the A and B inputs of the tempo increase detection circuit 311, respectively. The tempo rise detection circuit 311 compares the tempo data added to the A input with the tempo data added to the B input, and depending on the magnitude, the calculation circuit 31
2. If the data added to the A input is A and the data added to the B input is B, a signal "1" is output to the calculation circuit 312 when A<B is detected, and the next calculation is performed. , 3A+B/4...(1), and when A≧B is detected, a signal "0" is output to the calculation circuit 312, and the next calculation, A+B/2...(2) is instructed. Note that the tempo data added to the A input is tempo correction data measured by key presses or switch 305 presses during performance;
The tempo data added to the input corresponds to the tempo of the current performance. That is, the tempo increase detection circuit 311 instructs the above-mentioned (1) calculation when A<B is detected (when a tempo increase is detected), and the tempo correction data in the new tempo data calculated by the calculation circuit 312 is Increase the degree of tempo correction (tempo correction contribution rate). The arithmetic circuit 312 is connected to the tempo increase detection circuit 31.
The two inputs are processed based on the calculation indicated by 1. In this case, no matter which calculation is performed, the calculated value matches the tempo data of the reference tempo clock. Tempo data output from arithmetic circuit 312 is applied to latch circuits 313 and 315 via limiter 316. Here, the limiter 316 is connected to the arithmetic circuit 312.
This limits the maximum and minimum values of tempo data output from the tempo data. As described above, the latch circuit 315 latches the tempo data of the reference tempo clock in advance and applies it to the comparator 317. A count value from a counter 318 that counts high-speed clock pulses φ is added to the other input of the comparator 317 as tempo data, and when the two input data match, the comparator 317 sends a signal "1" to the AND circuit 319. Output to. Since the AND circuit 319 has a high-speed clock pulse φ applied to another input, this clock pulse φ is applied to the load input of the latch circuit 315 only when a match signal "1" is applied from the comparator 317.
LD, the reset terminal _R1 of the counter 318, and the AND circuit 320. As a result, the latch circuit 315 is connected to the limiter 31.
The counter 318 is reset, counts the high speed clock pulses φ again, and outputs this counted value to the comparator 317. Therefore, the comparator 317 outputs a coincidence signal "1" at a period corresponding to the tempo data applied from the latch circuit 315. AND circuit 320 connects other inputs to OR circuit 32
1 output is added. The OR circuit 321 takes the OR condition of the melody match signal MKEQ and the output of the inverter 322 that inverts the stop command signal MP, and always when the signal MKEQ and the signal MP are as shown in FIG. 5b and FIG. 5d, respectively. Signal “1”
The signal MKEQ and the signal MP are shown in Fig. 4b.
In the case of FIG. 4d, the signal "1" is output except for the time from the rise of the signal MP to the rise of the MKEQ. That is, the OR circuit 321 always outputs a signal "1" when the actual performance time _tKON is earlier than the regular performance time _t0 ,
If it is late, the signal "0" is output from the rise of the signal MP (the time when the third tempo clock is output from the normal performance time _t0 ) to the actual performance time _tKON . AND circuit 320 becomes operational when the OR condition of OR circuit 321 is satisfied, and outputs the high-speed clock pulses periodically applied from AND circuit 319 as tempo clock TCL. Mochi theory,
When the OR circuit 321 is outputting the signal "0", generation of the tempo clock TCL is stopped. That is, the output of the OR circuit 321 controls the generation of the tempo clock TCL to be stopped. Here, when a performance corresponding to the first note of the melody is performed and a melody matching signal MKEQ is output, the differentiation circuit 324 differentiates this signal MKEQ,
The latch circuit 31 latches the pulse signal at the rising edge.
3 and 314 load terminal LD. Latch circuit 313 latches tempo data applied from limiter 316, and latch circuit 314 latches tempo correction data applied from counter 323. Note that the counter 323 is preset with the tempo data of the reference tempo clock, as described above. Therefore, the tempo data latched in latch circuits 313 and 314 are both the tempo data of the reference tempo clock. On the other hand, the melody match signal MKEQ is OR circuit 3
21 to the AND circuit 20, and when the tempo clock TCL is output from the AND circuit 320, the melody data retrieval circuit 100 immediately outputs the melody data read command signal MLU.
The RAM read control circuit 18 outputs a next melody read request signal MNR. This signal MNR is
It is applied to the reset terminal R of the inverter 309 and the counter 323. This allows the signal
MKEQ becomes "0" and counter 323 is reset. In addition, the melody data extraction circuit 10
From 0 onwards, melody note length data ML corresponding to the first note of the melody is output to the variable frequency divider 325. The variable frequency divider 325 generates a high-speed clock pulse φ at a frequency division ratio corresponding to the input melody code length data ML.
The period of the clock frequency-divided and output from the variable frequency divider 325 is proportional to the note length indicated by the input melody note length data ML. For example, the period of the clock that is divided and output based on the note length data ML corresponding to a quarter note is twice the period of the clock that is divided and output based on the note length data ML that corresponds to an eighth note. Become. The clock output from variable frequency divider 325 is applied to clock input CK of counter 323 via AND circuit 326. The output of the NAND circuit 327 is added to the other input of the AND circuit 326. The NAND circuit 327 takes the count value (binary code NAND condition) output from the counter 23 to the latch circuit 314, and outputs a normal signal "1" to enable the AND circuit 326 and all bits of the counter 323. When the output becomes "1", a signal "0" is output to the AND circuit 326 to block the output of the clock from the AND circuit 326. Here, the performance corresponding to the second note of the melody is performed, and the melody matches. When signal MKEQ is output, latch circuits 313 and 314
Latch the tempo data input at the rise of MKEQ. At this time, the tempo data latched by the latch circuit 314 is the count value of the counter 323, and the value becomes a small value when the performance time is earlier than the normal performance time, and a large value when it is later. The tempo data latched by the latch circuit 314 is applied as tempo correction data to the A inputs of the tempo increase detection circuit 311 and the arithmetic circuit 312, respectively. The arithmetic circuit 312 performs arithmetic processing on two input data based on the arithmetic operation instructed by the tempo increase detection circuit 311 as described above. Now, a case will be described in which the previous performance was significantly delayed due to a performance operation (key press) error, and the current performance was performed at the normal performance operation timing. In this case, the tempo increase detection circuit 311 detects a tempo increase (A<B) and instructs the calculation circuit 312 to perform the (1) calculation. As a result, the arithmetic circuit 3
The new tempo data played in step 12 has a higher tempo correction contribution rate due to the tempo correction data based on the current performance, and quickly returns to the tempo data corresponding to the original tempo. In other words, for beginners, mistakes in performance operations,
The performance time may be significantly delayed from the original performance time due to difficult parts of the performance, but even in this case, the tempo correction data will have a high contribution rate when the tempo correction data is based on the next performance. This allows you to quickly return to the original tempo. In this example, past control tempo data and current measured tempo data (tempo correction data)
, new control tempo data was formed, but
New control tempo data may be created based on tempo data measured a plurality of times in the past and tempo data measured this time, as in Patent No. 78784 of 1980. In this case, the contribution rate of the currently measured tempo data is controlled by comparing the average of the past measured tempo data with the reference tempo data. Furthermore, in this embodiment, when a tempo increase is detected, the contribution rate is controlled using a constant value 3A+B/4, but the contribution rate may also be changed depending on the tempo increase rate (difference between two input data). If the tempo increase rate is very high, the tempo correction data may be output as is as new tempo data. As explained above, according to the present invention, when the tempo is controlled in an upward direction, the tempo can be quickly returned to the original tempo. As a result, even if the performance timing is significantly delayed due to an error in performance operation, a difficult part of the performance, etc., the original tempo can be quickly returned to, and extremely effective tempo control can be realized, especially for beginners.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an electronic musical instrument to which the present invention is applied, FIG. 2 is a data format showing an example of automatic performance data used in the present invention, and FIG. 3 is a block diagram showing an example of automatic performance data used in the present invention. A block diagram showing a detailed example of a melody data retrieval circuit, FIGS. 4 and 5 are timing charts of each signal according to the present invention, and FIG. 6 is a detailed example of a chord/obligado data retrieval circuit according to the present invention. FIG. 7 is a block diagram showing a detailed example of the tempo control circuit according to the present invention. DESCRIPTION OF SYMBOLS 1...Keyboard, 8...Music tone forming circuit, 10...Speaker, 13...Music data input device, 14...Data memory, 15...RAM write control circuit, 16...Address counter, 17...Start switch, 18...
RAM read control circuit, 19...data output circuit, 2
0... Display device, 100... Melody data extraction circuit, 200... Chord/obligado data extraction circuit, 300... Tempo control circuit.

Claims (1)

[Scope of Claims] 1. A performance operation means, a storage means for storing at least timing information of musical tones to be played by the performance operation means, and a reading means for reading out stored data from the storage means in accordance with the progress of the music piece. , forming tempo correction data from the operation timing of the performance operation means based on the timing information read by the reading means, and adjusting the read tempo of the reading means based on the tempo correction data. a tempo control means that automatically performs follow-up control in accordance with the performance tempo of the operating means; and a tempo control means that detects a fast performance in which the operation timing of the performance operation means is earlier than the previous operation timing based on the tempo correction data. performance detection means, and when a fast performance is detected by the fast performance detection means, the degree of read tempo correction by the tempo correction data in the tempo control means is changed to be greater than when the fast performance is not detected. and a tempo change control means for controlling the electronic musical instrument. 2. The electronic musical instrument according to claim 1, wherein the performance operation means is a keyboard. 3. The electronic musical instrument according to claim 1, wherein the performance operation means is a key switch other than a keyboard. 4. The electronic musical instrument according to claim 1, wherein the fast performance detection means detects fast performance by comparing the current read tempo with corrected data corresponding to the read tempo. 5. Performance operation means; Storage means for storing sound information and timing information corresponding to musical tones to be played by the performance operation means; Reading means for reading out stored data from the storage means in accordance with the progress of the music; and the reading means. tempo correction data is formed from the operation timing of the performance operation means based on the timing information read by the means, and the read tempo of the reading means is adjusted by the performance operation means based on the tempo correction data tempo control means for automatically following control according to the performance tempo of; and fast performance detection means for detecting a fast performance in which the operation timing of the performance operation means is earlier than the previous operation timing based on the tempo correction data. and, when a fast performance is detected by the fast performance detection means, change control is performed so that the degree of correction of the read tempo by the tempo correction data in the tempo control means is greater than when the fast performance is not detected. An electronic musical instrument comprising: tempo change control means; and an automatic performance device that produces automatic performance sounds based on stored information read from the storage means. 6. The electronic musical instrument according to claim 5, wherein the sound information is pitch data or chord data. 7. A keyboard, a storage means for storing at least timing information and key information of musical tones to be played on the keyboard, a readout means for reading out stored data from the storage means in accordance with the progress of a piece of music, and by the readout means. a display device that displays a key to be pressed based on the read key information; and tempo correction data is formed from the key press timing on the keyboard based on the timing information read by the reading means. tempo control means for automatically controlling the reading tempo of the reading means to follow the playing tempo on the keyboard based on the tempo correction data; a fast performance detection means for detecting a fast performance that becomes fast based on the tempo correction data; and when a fast performance is detected by the fast performance detection means, the degree of readout tempo correction based on the tempo correction data in the tempo control means is adjusted to match the fast performance according to the tempo correction data; An electronic musical instrument comprising: a tempo change control means for changing the tempo so that the play is louder than when no performance is detected. 8. The electronic musical instrument according to claim 7, wherein the reading means displays key information that precedes the key by one note on the display device.