JPS58172697A - Automatic performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic performance device that corrects the progress of an automatic performance in accordance with the timing of operating keys, etc., and that allows easy tempo setting.

Conventional automatic performance 1 [includes automatic performance of melody sounds, oprigado sounds, bass sounds, chord sounds, and rhythm sounds based on reading of instrument data, or automatic performance of a combination of these as appropriate. However, if you start by setting the tempo, this initial tempo will be maintained until the end, and the automatic performance will continue.

Therefore, when playing by pressing the keys according to the automatic performance from such an automatic performance device, the automatic performance always progresses at the same tempo for both difficult and easy performance parts, so it is difficult for beginners to understand the key press timing and automatic performance. The key is out of alignment, and the key pressed on the keyboard is 1M! It was causing a hindrance to learning.

Furthermore, the tempo of automatic performance is set by operating the tempo adjustment volume, etc., but to set the tempo that matches the image, for example, you must operate the tempo adjustment volume while actually playing the automatic rhythm sound. However, it took time to set the tempo and required automatic performance.

This invention has been made in view of the above-mentioned circumstances, and if the timing of the performer's pressing operation is delayed compared to the timing when the key should be swept, the automatic performance is temporarily stopped, so that the keyboard performance and automatic performance can be changed. An object of the present invention is to provide an automatic performance device that can match the progression of the music and easily set and change the tempo.

According to this invention, a tempo clock that advances automatic performance is generated in relation to the suppression timing of the tempo setting switch, and the timing at which the operation should be performed is compared with the operation timing, so that the operation timing is If it is too late, the generation of the tempo clock is prohibited from the operation timing to the operation timing O, and the progress of the automatic performance is temporarily stopped.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a melody sound automatic performance function that reads recorded data on a magnetic tape 1a formed on a musical score 1 with a data storage device #2, and automatically plays a melody sound based on this read data, and an automatic playback function that automatically plays an oprigade sound. It has an automatic accompaniment sound performance function, as well as an automatic accompaniment sound performance function that forms accompaniment sounds such as automatic chord sounds and automatic bass sounds based on the keys pressed on the accompaniment keyboard 3, and automatically plays these accompaniment sounds. This embodiment shows an embodiment in which the present invention is applied to an electronic musical instrument equipped with an automatic rhythm playing basket that automatically plays rhythm tones corresponding to a designated rhythm. This I4c child instrument also has a non-display function for displaying the next key to be pressed on the melody keyboard 4 based on the data received by the data reading device 1F2 for melody performance practice.

The data reading device 2 reads and extracts opligado data and melody data corresponding to the obbligado performance and melody@committee from the magnetic tape 1a of the musical score 1, and transfers the read data to the opligado data memory 5 and melody data memory 6, respectively. . Note that when reading data, the data write/read control circuits 7 and 8 each enter a write mode, designate the write address of each memory 5 and 6, and write oprigard data and melody data to each memory 5 and 6.

Here, Table 1 shows an example of the data format corresponding to Oprigade data and melody data.

In Table 1, each data Di (i=1...n) consists of pitch data TLI and note length TL2, and pitch data TLI includes, for example, a 4-bit note code NC indicating a note and an octave. The symbol length data is composed of #t7 bit data of a 3-bit octave code OC indicating, for example, 8-bit data. An example of note length data is shown in Table 2.

Essay 2 Tables and rests are created by setting all the bits of the note data to @0'', and the end data L that takes away the leverage of the data.
)n is tSi data Tl, 1 and attached, tSi data TL2
It is represented by setting all bits to "1".

Oprigard data memory 5j? Reading of each data from melody data memory 6 and melody data memory 6 is performed by data write/read control circuits 7 and 8, respectively.

1. To start automatic operation, press start switch 9.
is turned on, the standby flip-flop FF1 is checked, and the performance flip-flop FF2 is reset. When F1 (standby flip-flop) is set, a signal 11'' is applied from its output terminal Q to the differentiating circuit 10 and the delay flip-flop DPI.As a result, the differentiating circuit IO outputs the preset signal ΔPR (one pulse). The delay flip-flop DPI delays this M number 11'' for a predetermined time and then outputs it to the AND circuit AI.
In addition to this, the AND (b) path A1 is activated and the aT function is activated.

The preset signal ΔPR is applied to the data write/read control circuits 7 and 8 to put the respective lPl paths 7 and 8 into the read mode and set the internal address counter to the initial address. As a result, the first stored data is read out from the Oprigade data memory 5 and the melody data memory 6. In addition, the preset signal ΔPR
is connected to latch circuit Ll via OR circuits ORI and OR2.
, L2 and L3. Since the signal is applied to each load terminal LD of L4, the latch circuit L1 latches the first oppriguard data, and the latch circuit L3 latches the first melody data.

On the other hand, the performance flip-flop FF2 does not output the reset round and play signal PL ("1#"), but applies a signal "0" to the inverters INI-INS. The inverter IN11141'''0'' is inverted and applied to the reset terminal H of the note length counter 11 via the signal "1" OR circuit OR3, and the inverter IN2 similarly inverts the signal @O# [,
The signal ``1'' is sent to the note length counter 1 via the OR circuit OR4.
In addition to the reset terminal R of No. 1, inverters IN3 and N4 each invert ↑g@O'' and connect No. 400.
1'' is applied to the set terminals R of flip-flops FF3 and F'F4 through OR circuits OR5 and OR6, and the inverter INS inverts the signal 10'' and applies the signal @11 to the address counter I3. . Therefore, when the performance flip-flop F2 is reset, the note length counters 11 and 12, the flip 70 knobs FF3 and FF'4, and the address counter 13 are all reset.

Further, the pitch data TLI of the melody data added by the latch circuit L3 is added to the key display device 14, - comparator 15 and rest detection circuit 16, and the key display device [
14 is # of the first note of the melody performance (# that should be pressed first)
) is displayed on the key by lighting the next indicator lamp.

In this state, if you press a key on the melody keyboard 4 whose display lamp is lit, a key code KC indicating the pressed key will be displayed.
(consisting of a 4-bit note code NC and a 3-bit octave code OC) is output. This key code KC is added to the melody sound formation time w+17. The melody tone generating circuit 17 forms a musical tone signal corresponding to the melody tone indicated by the key FK'C, and applies this signal to the speaker 19 via the amplifier I8 to generate the melody tone.

In addition, the key 21-key K output from the melody keyboard 4
C is applied to the comparator 150B input. In the pitcher t5, the pitch data TLI of the t8 data is added to the latch +0+ path L3 to the A input, and the pitch data TLI is added to the input A.

When the pitch data TLI added to this input (indicating the note to be pressed) matches the key code KC added to the input input (indicating the note to be pressed), the - scattered terminal E (outputs a matching signal) Ru. This coincidence signal is applied to AND circuit A2. AND circuit A2 has Nm for melody as the other input.
Any key on times MAKON output from the OR circuit OR7 which takes the OR condition of the key code KC output from 3.
A signal obtained by differentiating (tgs which becomes l" when any 〇- is pressed) using a differentiator circuit is added, and on the condition that the pot whose display lamp is lit is pressed, it is synchronized with the pressing of -. The pressed pulses (key press coincidence signals) Kh, t, and J are output.This press coincidence whistle signal KEQ is sent via the left switch 2 and l0JW!rA3.A.
4, is added to A5, and is also connected to the standby 7 lip-flop FFI via AND circuit A1 and OR circuit OR8.
is applied to the reset terminal R of.

Since the AND circuit A1 is enabled to operate by the delay flip-flop DFl, it outputs the pulse number 11M ΔPL upon input of the push match signal KEQ, and also sends this pulse signal ΔPL to the flip 70 knob FF for 'o4#.
Add to set terminal S of 2. Flip-flop F for transshipment
F2 is set by this pulse No. 1g Ml-L and outputs the play No. 100 PL. On the other hand, the standby flip-flop F F' 1 is already turned off, and the AND circuit A1 is made inoperative thereafter.

Pulse 16 Δl'L output from the AND circuit A1 is applied to the data pledge succession control circuits 7 and 8 via the OR circuit OR9 and (JRIO, respectively), and advances the internal address counter by one step.

As a result, the second data is read from the obligate data memory 5 and the melody data memory 6. In addition, each pulse number Δl'L is OR circuit OR9, ORI
is applied to the load terminals LD of latch circuits L1 and L2 via the latch circuit L1, so the latch circuit L1 latches the opli-guard data read out in the second scan, and the latch circuit L2 latches the opli-guard data read out in the second scan, and the latch circuit L2 Latch data. Similarly, the pulse signal △PL is OR circuit 0R
Since it is applied to the load terminals I and D of latch circuits L3 and L4 via IO and OR2, latch circuit L3 latches the melody data read out in the second scan, and latch circuit L4
latches the first melody data latched by latch circle wIrL3.

The opli-guard data latched by the latch circuit L2 is applied to the end detection circuit 4, the tone sieve data TLI of the opli-guard data is applied to the opli-guard tone forming circuit c, and the note length data 1'L2 is applied to the comparator 24. Added to A input. The end detection circuit 22 detects the end of the data when all bits of the obbligard data (pitch data TLI+note length data TL2) are @1'', and outputs the end signal DOIN. The standby flip-flop FF'1 and the performance flip-flop FF are connected via OR circuits OR8 and 0RII.
2, the standby flip-flop i'h' i and the performance flip-flop F' F
Reset 2. This ends the automatic performance.

The ozoli guard sound forming circuit 23 forms a musical sound signal corresponding to the obbligado level indicated by the input pitch data 1゛1.1, and increases this to Ill! It is added to the speaker 19 via the device 18 and is generated as an oprigade sound.

Of the second melody data latched by the latch circuit L3, the tone data TLI is added to the health display w14,
The key display device fl14 lights up and displays - of the second note of the melody performance. Note that this lighting display is performed in the same manner as in the case described above.

Also, among the first melody data latched by the latch circuit L4, the pitch data TLI is stored in the melody sound forming circuit δ.
The code length data TL2 is added to the A input of the comparator 26. The melody sound forming circuit 25 forms a musical sound signal corresponding to the melody sound produced by the input pitch data TLI, and applies this signal to the speaker 19 via the amplifier 181 to generate an automatic melody sound. Note that the key code KC is added to the melody sound forming circuit 17 based on a key press on the melody keyboard 4, and the pitch data is latched by the latch circuit L4 and added to the melody sound forming circuit 25 based on this press. Of course, the data is the same as the TLI. Therefore, 7
It is preferable to use a kt4 tone for the near meliday sound and the automatic melody sound, or to narrow down the ff of the automatic melody sound.

9. The play signal PL generated from the performance flip-flop/FF"2 is applied to the inverters INI to INS. As a result, the note length counters 11 and 12 and the address counter 13 are unset. i number is possible.Also, flip-flops F3 and FF4
(Each reset) P and JR receive input from inverters IN3 and IN4 to 1.

A tempo pulse is generated at each clock terminal CK of note length counter 11 and Lz, and address counter I3.
A tempo clock TCL is added from the AND circuit A6Q. Note that AND circuit A6 has 7 inputs to other inputs.
The output signal from the flip-flop F' F4 (10# in this case) is inverted by the inverter INS and added, making it operational.

Furthermore, the tempo pulse generating circuit n generates a tempo clock TCL of an appropriate number of waves in order to determine the tempo of automatic performance, and I will explain the details to him.

The address counter 13 counts the previous tempo clock TCL by 6 and outputs the counted value to the pattern memory as an address fg-Q for the pattern memory. Pattern memory allows you to store multiple bass patterns, chord patterns and rhythm patterns for each rhythm.
are doing. This pattern memory recommendation is selected in advance by a rhythm selection switch (not shown), and the above-mentioned patterns to be read out corresponding to nine rhythms are specified, and the base putter No. 71g BP is selected in accordance with the address signal output from the address counter 13. Then, the bass sound generation timing signal B'1'', the chord sound generation timing signal cT, and the rhythm pattern signal IRPe are read out. Here, the bass pattern signal BP is information indicating the pitch relationship to the root note of the automatic bass note to be produced (this root note is specified in relation to the keys pressed on the accompaniment keyboard 4), and The timing signal BT is a signal indicating the generation timing of the automatic bass tone, and the chord tone generation timing signal CT is the emission timing of the automatic chord tone (this chord tone is specified in relation to the key pressed on the accompaniment keyboard 4). The rhythm pattern signal RP is information indicating the type of pronunciation sukuki rhythm and its pronunciation timing.

The accompaniment sound forming circuit 29 adds the key code representing the root note of the automatic bass sound outputted from the accompaniment keyboard 3 and the bass pattern signal BP to form a key code representing the automatic bass sound, and adds this key code to the base pattern signal BP. A musical tone No. 1g corresponding to the automatic bass tone is formed from , and this musical tone signal is outputted by controlling the opening/closing envelope according to the bass tone generation timing signal BT, and also shows an automatic chord tone output from the accompaniment keyboard 4. A musical tone signal corresponding to an automatic chord tone is formed from the key code, and this musical tone signal is controlled in an opening/closing envelope according to the chord tone generation timing signal CT and output.

Musical tones I and C indicating these automatic accompaniment tones are applied to the speaker 9 via the amplifier 18, and are emitted as automatic accompaniment tones.

Further, the rhythm pattern signal HP output from the pattern memory A is applied to the rhythm sound source circuit 30. The rhythm sound source circuit (source) generates rhythm sound signals indicating various rhythm instrument sounds according to the input rhythm pattern 1l-HP,
This is added to the speaker 9 via the amplifier 18, and is emitted as an automatic rhythm sound.

On the other hand, the note length counters l and 12 count the tempo clock TCL written in iIJ applied from the tempo pulse generation circuit n via the AND circuit 46, and use the counted value as note length data to input B to the comparators 24 and 26, respectively. Add to. The comparator 24 has the code length data T L2 of the obligate data latched by the latch circuit L2 applied to its A input. In this case, the mark length data TL2 added to the input of the comparator 11:24 is f3.
iJ As is clear from the above explanation, this is note length data regarding the first note of the opligado note. The comparator 24 compares the note length data TL2 added to the input with the counted value of the note length counter 11 which started counting from the timing of the first key press, and when both data match and A=B, line t1 A pulse signal of signal ""1" is output to the data write/read control circuit 7 via the OR circuit OR9, and advances the internal address counter by one step. The third data is read from .Furthermore, the pulse signal of
, 1 latches the third read out Opliguard data, and latch circuit L2: latches the second Opliguard data latched by the latch circuit Ll. Also,
This pulse number 1M is applied to the reset terminal R of the note length counter 11 via the OR circuit OR3, and is applied to the reset terminal R of the note length counter 11.
Reset.

In this way, obbligado data is sequentially played out, and automatic obbligato performance is performed.

Furthermore, when the key press timing is earlier than the key press timing, the melody data is read out at the key press timing, and when the key press timing is later than the key press timing, the melody data is read out at the key press timing. Reading is performed at key timing.

Hereinafter, operations will be described when the key press timing for the second tone is earlier than the key press timing, when they match, and when the key press timing is later than the key press timing.

1) When the key press timing is earlier than the key press timing If the key press timing is earlier than the note length data TL2 latched by the latch circuit L4, the note length counter 12
The key press coincidence signal KEQ is generated before the count value reaches the note length data TL2. Therefore, the key press coincidence signal KEQ
When a tie occurs, the line t is output from the comparator 26.
A signal ""1" is generated at line t3 (if the B input is smaller than the comparator input A, the signal @1# is output to line t3), and the key press coincidence signal KEQ, the signal on line t3, and The rest detection signal RD from the rest detection circuit 16 is inverted by the inverter IN7 and a good signal (in this case, the rest detection signal R
AND circuit A3 that takes the AND condition (D is "0")
The output of the AND circuit A3 becomes 11''. The output signal @1'' of the AND circuit A3 is applied to the set terminal S of the flip-flop FF3, and sets the flip-flop FFS. As a result, the flip-flop FF3 applies the signal 11' from the output terminal Q to the AND circuit A7 via the delay flip-flop Dk'2, thereby enabling the AND circuit A7. The other input of the AND circuit A7 is a differentiating circuit 3 which receives a signal on line t2 outputted from the comparator 26 when the key depression timing and the key depression timing match (A=B).
A nine-note length differential signal LEQ is added after being differentiated by 1. Therefore, in the AND circuit A7, A=B holds true in the comparison 64, and the AND condition is satisfied at the time when the code length match signal LEQ is generated, and the signal @l# (pulse signal) is satisfied.
Output. This signal is transmitted to the data write/read control circuit 8 and the OR circuits 0RIO and OR2 via the OR circuit 0RIO.
latch circuit L3. It joins L4 and reads the next melody data. In addition, flip-flop F
Ant 1 to F3 set terminal R! 'The output of the J circuit A7 and the output of the OR circuit OR5 which takes the OR condition of the output of the inverter IN3 which inverts the play signal PL are added. be done.

2) When the key press timing matches the key press timing When the key press timing matches the note length data TL2 latched in the latch circuit L4, the press match signal KEQ is sent.
At the same time, AmB is established in the comparator 26, and the line t
A signal @1'' is generated at the differential circuit 3.
1, and the AND circuit A is used as the ladle length match signal LEQ.
Added to 4.

The other inputs of the AND circuit A4 include the output of the inverter INS which is the inversion of the rest detection signal RLI, and the input signal KEQ. Therefore, the AND condition of 4 is satisfied for the AND circuit, and the signal 111 (pulse signal) is outputted via the OR circuit 0RIO. This signal @
1'' causes the next melody data to be read.

3) When the key press timing is later than the key press timing When the key press timing is later than the note length data TL2 latched in the latch circuit L4, or when the correct key press is delayed due to a mistouch, Before the key pressed match signal KEQ is generated, the counted value of the note length counter 2 reaches the above note length data, the comparator 26 establishes A=B, and the differentiating circuit 31 outputs the note length match signal LJ! ;Q occurs. This code length match signal LEQ is applied to AND circuit A8. AND circuit A8 has the output signal of inverter IN9 and the output of AND circuit A4 inverted by inverter INI (J), and in this case, a rest detection signal RD is added to other inputs.
is "0" and the output of the AND circuit A4 is @O#, so the AND condition of the AND circuit A8 is satisfied and the signal "1" is output. The output of this AND circuit A8 is transmitted to the flip-flop FF4 through the AND circuit A9, which is operable by adding the inverted output Q (in this case, "1") of the flip-flop FF'3 to the other input. It is added to the set terminal S. As a result, the flip-flop FF4 is set and outputs the stop signal ST from the output terminal Q. This stop signal S
T is inverted by inverter IN6 and applied to AND circuit A6, which disables AND circuit A6 and stops the output of tempo clock 'I'CL generated from tempo pulse generation circuit n, thereby temporarily halting the progress of automatic performance. do.

Further, the stop signal ST output from the flip-flop FF4 is applied to the AND circuit A5 via the delay flip-flop L)F3. The AND circuit A5 is configured such that a key press matching symbol flQ is added to other human inputs. Therefore, the AND condition of the AND circuit A5 is satisfied at the timing of the key press coincidence signal KEQ, and the signal ""1" (
A pulse signal) is outputted via OR circuit 0R10. This signal 111 causes the next melody data to be read. Note that the output of the AND circuit A5, PLAY!, is connected to the reset terminal R of the flip-flop FF4, which outputs the stop signal ST. The output of OR times %OR6 which takes the OR condition of the output of the inverter IN4 which inverts gPL is added, and in this case, the output of the AND circuit A5 causes the 7 lip-flop FF4 to be turned off, and the stop signal becomes @θ''. Become.

In the above operation perspective, it is assumed that the rest detection signal R1) output from the rest detection circuit 16 is @0'', but when the rest detection signal RD is @1'', the rest detection signal 11 ) and the note length match signal LEQ.
is the timing at which the code length match signal LEQ is generated, that is, the count value of the code length counter 12 is the code length data TL2 latched in the latch circuit L4 during the comparison in the comparator 20.
When the signal @1# matches, a signal ""1" (pulse signal) is outputted via the OR circuit 0RIO. The next melody data is read out by this signal @1#.

In this way, the melody data is sequentially read out, the keys to be pressed are displayed, and an automatic melody performance is performed.

In addition, when the select switch 21 is switched and used, as long as a key is pressed on the melody middle keyboard 3, even if there is a mistouch (the pressed petill and the pressed key do not match), the key press coincidence signal K is generated.
EQ can be output and automatic performance can proceed.

Next, the tempo pulse generation circuit U will be explained.

The tempo pulse generation circuit n generates a tempo clock TC of an appropriate frequency based on the suppression interval set by the tempo setting switch 32.
It generates L. First, when setting the tempo, the tempo setting switch 32 is pressed at desired intervals, for example, every beat, which is a unit of time signature. Note that this tempo setting switch 32 is composed of a self-recovery type switch. When the tempo setting switch 32 is pressed, a signal "1" is applied to the differentiating circuit every time the tempo setting switch 32 is depressed. The differentiating circuit takes the differential of the rising edge of the manually input signal @1'' and applies it to the tempo pulse generating circuit 27 as the signal TSW.

The second factor is block (2) showing one embodiment of the tempo pulse generation circuit 27, in which the signal TSW is applied to delay flip-flops DF4 and DF8.

When the first signal TSW is input, all the bits of the counter 34 are 1.l'', and the NAND circuit NA which takes the NAND condition of each bit output of the counter 34 outputs the signal 1.
01 is output. As a result, AND circuit A 11
- A14 is inactive.

Delay flip-flops DF4 and DF8 each delay the input signal TW8 by the time interval of the high-speed stomach pulse φ and output it to the next stage delay flip-flops DF5 and DF9. Pu DF6j? x HiD F 10, delay flip-flops DF6 and DFIO each have a delay of 7
The signal TOW is delayed by the time interval of the high speed clock pulse φ and outputted to the flip-flop DF7 and the reset terminal R of the counter.

The counter A is set by the signal TSW applied from the delay flip 70-tube DFIO, and the counter A is reset by the signal TSW which is further delayed by a time interval of one clock pulse from the delay flip-flop DF7. When the counter is reset, the NAND circuit NA, which takes the NAND condition of each bit output of the counter, outputs a signal @1'' to enable the AND circuits A11-A14.

Here, based on the suppression by the tempo setting switch 32, 2
When the th signal TOW is applied, this signal TOW is applied to the delay flip-flops DF4 and D fi''8, and is also applied to the lead terminal LD of the latch circuit L5 via the AND circuit A12. The information latched in the circuit L6 is latched and this information is output to the average value calculation circuit.Similarly, the latch circuit L6 is delayed by a time interval of one clock pulse by a delay 7 lip-flop DF8, and the above-mentioned signal TSW is delayed by a time interval of one clock pulse. is inputted to the load terminal LD via the AND1 path A13, the information latched in the latch circuit L7 is latched, and this information is output to the average value calculation circuit 46, and the latch circuit L7 is connected to the delay flip-flop The signal TSW, which has been delayed by a time interval of two clock pulses by the switches DF8 and DF9, is inputted to the U-domain terminal LD via the AND circuit Aln, and the count value of the counter 35 (
The information indicating the time interval between the first signal 'rSW and the second signal TSW) is latched and this information is output to the average value calculation circuit A.

Note that the counters 35 and 35 are reset in the same manner as described above. In addition, the time interval of the counter aha signal T8W is a predetermined time (the longest beat interval that can be considered)
When the interval is longer than that, the information corresponding to that time interval is not captured. That is, as described above, in the above case, all bit outputs of the counter become "11", and the AND circuits A11-A14 are rendered inoperable.

Average value calculation circuit Aha latch circuit L5. L6. The average value of the numerical information added from L7 is calculated, and this average value is output to the variable branching unit 37. The variable divider 37 divides the high speed clock pulse φ using the input average value as dividing ratio data to generate a tempo clock TCL.

Therefore, as the suppression interval at the tempo setting switch 32 becomes longer, the frequency of the generated tempo clock TCL becomes lower, and as the suppression interval becomes shorter, the generated tempo clock TCL becomes lower.
The frequency of CL can be high.

In other words, it is possible to generate a tempo clock TCL of an appropriate frequency based on the suppression interval set by the tempo setting switch 32, thereby controlling the tempo of the eye movement performance.

In addition, in this embodiment, the average value of three pieces of numerical information is calculated, and the frequency of the tempo clock TCL is determined based on this average value. Therefore, when setting the tempo before playing, the tempo setting switch 32 is pressed. It is preferable to press at least four times or more. Also, you can change the tempo at any point during the performance.
The tempo can be changed by pressing the tempo setting switch 32 two or more times.

FIG. 3 is a block diagram showing another embodiment of the tempo pulse generation circuit n, in which the pulse generation circuit 27 determines the tempo based on the operation of the tempo setting device before the performance, and during the performance. When the pitch of the melody changes (when the note length matches (+! sign LEQ is output)), the tempo setting switch 32 (Fig. 1) is suppressed from the timing when the note length match signal LEQ and the tempo setting switch 32 are suppressed. The deviation from the base signal TOW is measured, and the tempo is corrected based on this measured value.

As shown in Figure @1, when the code length data TL2 and the counted value of the note length counter 12 match in the comparator section (A=B), the code length match signal LEQ is output from the differentiating circuit 31 to a line t4 shown by a broken line. When the tempo setting switch 32 is depressed, the signal gTSW is applied from the differentiating circuit 33 to the tempo pulse generating circuit n.

In Figure 3, note length -! @No. LEQ is input with the pulse train shown in Fig. 4 (&), (F! No. 'I' SW is 1g
The operation when the pulse train shown in Fig. 4 (d) is input will be explained. The one-key mark circuit 39 receives the note length match signal LE.
By inputting Q, a pulse signal of pulse width T is sent to line t6.
The inverter lN11 outputs the inverted output of the output of line t6 to line t5 (@4 (C)).
Figure (b)). Similarly, the one-shot circuit sum is the signal TSW
With the input of , a pulse signal with a pulse width T is output to the line t8 (WJ4 figure (f)), and the inverter lNl2 outputs the inverted output of the output of the line t8 to the line t7 (
Figure 4(C)).

The AND circuit A15 takes an AND condition between the code length match signal LEQ and the signal generated on the line t7, and in this W combination, the pulse 4g'''1'' is output at the output of the code length match signal LEQ1.
is output (Fig. 4(g)). AND circuit AlbFi,
This occurs on the signal 'rsw and the line t5 (this takes an AND condition with the signal 'g', and in this case, the pulse [4"1" is output at the time the signal TSW2 is output (as shown in Figure 4)).

Further, the AND circuit A17 takes an AND condition between the code length match signal LEQ and the signal generated on the line t8. In this case, when the code length match signal LEQ2 is output, the pulse signal @1
” (4th (b) (i)).

AND circuit A18 generates 4 on signal TOW and line t6.
It takes an AND condition with No. 1, and in this case, fg-S
=j A pulse signal ``1'' is output at the time of output of TSW1 (Fig. 4 (j)).

The outputs of AND circuits A15 and A16 are OR circuit 0R
It is applied to the set terminal R of the counter 41 via II to reset the papermaking counter 40. The outputs of AND circuits A17 and A18 are connected to latch circuit L8 and delay flip-flop D F'1 via OR circuit 0'R12.
1, and the output of the AND circuit A18 is also applied to the delay flip-flip DFL3.

The latch circuit L8 has an OR circuit 0R1 on its p-de terminal LD.
When a pulse signal is applied via latch circuit L9
The information latched in is latched, and this information is added to the A input of the average value calculation circuit 42.

The latch circuit 9 inputs the pulse signal delayed by the time interval of l clock pulses to the load terminal Lo of the delay flip-flop DF11, and the latch circuit LI
Latch the information that has been latched for the OK length and add this information to the B input of the average value calculation circuit 42. The latch circuit LIO consists of delay flip-flops DF14 and DF12.
The pulse signal delayed by a time interval of two clock pulses is inputted to the load terminal LD, and the count value of the counter 41 (the counter 41 is input to the AND circuit A15 or A16) is input to the load terminal LD.
After being reset by the output of AND circuit A 17
t or information indicating the time interval until the latch circuit is activated by the output of A18), and is delayed by a time interval of two clock pulses by delay flip-flops DF13 and DF14, and the inverter IN13
The inverted output of the AND circuit A18 is latched as sign information, and this information is added to the C input of the average value calculation circuit 42. Note that when the code information is "O#" (when the output of the AND circuit A18 is @1#), the code match signal LE
The deviation of the signal TSW with respect to Q is "negative", which means that the output timing of the signal TSW is delayed compared to the output timing of the mark length minus signal LEQ, and when the code information is "1", it is a sign High signal TS for long match signal LEQ
This indicates that the deviation of W is "positive".

Therefore, when the note length-sparse signals I, EQ and signal TSW are input at the timings shown in FIG. Then, the information corresponding to the positive deviation t is latched.

The average value calculation circuit 42 includes a latch circuit L8. L9. Calculate the average value of the numerical information added from L10 and use this average value as correction data for the frequency of the tempo clock TCL to oscillate the tempo! 42. The tempo oscillator 43 has a variable division divider, and before performance, divide ratio data corresponding to the tempo set by the tempo setter A is inputted from the tempo setter A, and the high-speed clock pulse is divided based on this division ratio data. By doing so, a tempo clock TCL is generated, and when the correction data is added from the average value calculation circuit 42 during the performance based on the suppression timing with the tempo setting switch 32, the correction data is subtracted from the division ratio data, A tempo clock TCL is generated by dividing the high speed clock pulse using this as new frequency division ratio data.

Therefore, when the correction data is positive (when the average value of the deviation is positive), the frequency of the tempo clock TCL becomes higher, and the tempo of automatic performance becomes faster.

Also, if the correction data is negative, the tempo clock TTCL
The frequency of υ is low, and the tempo of automatic performance is slow.

As described above, according to the present invention, when the operation timing is delayed with respect to the timing at which the key should be operated, automatic performance is temporarily stopped, thereby making it possible to match the progress of key a performance and automatic performance.

Additionally, automatic performance can be temporarily stopped when a - key is pressed, which can be expected to be very effective for practicing keystrokes on the keyboard. i9. Tempo setting, f' history can be set and changed by the suppression timing of the tempo setting switch, and the tempo of automatic performance can be easily set to a desired tempo.

[Brief explanation of drawings]

Figure wJ1 is a block diagram showing one embodiment of this invention.
The figure is a block diagram showing one embodiment of the tempo pulse generating circuit according to the present invention, FIG. 3 is a block diagram showing another embodiment of the tempo pulse generating circuit according to the present invention, and FIG. There are nine timing charts used to explain the operation. data memory, 7, 8... data write/read control circuit, 11, 12... note length counter, 13... address counter, 14... key display device, 15, 24
, 26... comparator, 17. δ... Melody sound formation circuit, Edict... Oprigade sound formation circuit, 27... Tempo pulse generation circuit, ah...
・Pattern memory, 4...Accompaniment sound formation circuit, 30...
・Rhythm sound source circuit, 32...tempo setting switch;
<4.35 e 41...Counter, ah, 42...
Average value calculation circuit, 37... variable divider, ah... tempo setter, 43... tempo oscillator.

Claims (8)

[Claims] (1) A keyboard, a storage means for storing at least note length data, a tempo clock generation means for generating a tempo clock that advances automatic performance in relation to the suppression timing in the tempo setting switch, and note length data sequentially from the specified storage means. A reading means for reading out the note length data read by the reading means compares the operation timing indicated by the note length data with the operation timing on the specified keyboard, and determines the operation timing when the operation timing is later than the operation timing. An automatic performance device comprising a stop means for temporarily stopping the progress of an automatic performance from to an operation timing. (2) The tempo clock generating means considers the interval between press timings on the tempo setting switch as a reference interval, and generates a tempo clock of a wave number corresponding to the reference interval. Automatic performance device. (3) The tempo clock generating means includes a tempo setting means and a tempo oscillator, and the tempo excavator determines the oscillation frequency of the initial tempo clock based on the output of the tempo setting means, and determines the timing to be operated and the tempo setting. ＞
The automatic performance device according to claim 1, wherein the oscillation frequency of the tempo clock is corrected based on the deviation from the suppression timing of one switch to generate the tempo clock. (4) The reading means detects the time point at which the timing at which the operation should be performed has elapsed by counting the tempo clock, and when the operation timing is earlier than the timing at which the operation should be performed, the time point at which the timing at which the operation should be performed has elapsed. According to claim (1), the note length data is read out from the storage means at the time of operation, and when the operation timing is later than the timing at which the operation should be performed, the note length data is read out from the storage means in synchronization with the operation timing. automatic performance device. (5) The storage means stores note length data as well as pitch data, and the pitch data is read out by the readout means and added to a pressed key display device to display the key to be pressed. The automatic performance device described in scope (1). (6) The automatic performance device according to claim (1), wherein the manual operation means is a key. (7) According to claim (1), the stopping means is characterized in that the tempo clock is prohibited from being generated between the timing at which the operation is to be performed and the timing at which the tempo clock is to be operated, thereby causing the automatic performance to proceed. automatic performance device. (8) The automatic performance device according to claim (1), wherein the automatic performance includes automatic rhythm performance, automatic chord performance, automatic bass performance, automatic melody performance, and automatic oprigade performance.