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JPH04298049A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04298049A
JPH04298049A JP10632491A JP10632491A JPH04298049A JP H04298049 A JPH04298049 A JP H04298049A JP 10632491 A JP10632491 A JP 10632491A JP 10632491 A JP10632491 A JP 10632491A JP H04298049 A JPH04298049 A JP H04298049A
Authority
JP
Japan
Prior art keywords
resist
pattern
photoresist
substrate
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10632491A
Other languages
Japanese (ja)
Inventor
Kazuo Hayashi
一夫 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10632491A priority Critical patent/JPH04298049A/en
Publication of JPH04298049A publication Critical patent/JPH04298049A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To provide a metalized fine electrode pattern, having low wiring resistance, on a substrate using resist. CONSTITUTION:A T-groove is formed in a photoresist 2 with a masking film 3 deposited over it. After the masking film 3 is removed, a metal film is deposited, and then an electrode pattern 4' having a T-shaped cross section by a lift-off technique.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は半導体装置の製造方法
に関し、特にレジストを用いて配線パターンを形成する
方法の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improvement in a method of forming a wiring pattern using a resist.

【0002】0002

【従来の技術】図2は従来の半導体装置の製造方法によ
る製造フローを示す断面図であり、図に示すように、ま
ず半導体基板1上にフォトレジスト2を塗布し、任意の
方法でフォトレジストをパターニング(図2(a))し
た後、そのフォトレジスト2をマスクとし基板1をエッ
チング(図2(b))し、次いで基板全面に配線金属を
蒸着(図2(c))し、その後リフトオフ(図2(d)
)して任意の金属3を基板上にパターニングする。なお
上記工程において、基板に溝を設けない場合にはエッチ
ング工程(図2(b))は必要ないものである。
2. Description of the Related Art FIG. 2 is a cross-sectional view showing the manufacturing flow of a conventional semiconductor device manufacturing method. After patterning (FIG. 2(a)), the substrate 1 is etched using the photoresist 2 as a mask (FIG. 2(b)), then wiring metal is deposited on the entire surface of the substrate (FIG. 2(c)), and then Lift-off (Figure 2(d)
) to pattern an arbitrary metal 3 on the substrate. Note that in the above process, if no groove is provided in the substrate, the etching process (FIG. 2(b)) is not necessary.

【0003】以上のような方法でパターニングされた金
属パターン4は図2(d) に示すように、その線幅は
レジストパターン2の開口幅で決まり、また断面形状は
レジストパターンの形状のために台形のものとなる。
As shown in FIG. 2(d), the metal pattern 4 patterned by the above method has a line width determined by the opening width of the resist pattern 2, and a cross-sectional shape determined by the shape of the resist pattern. It becomes trapezoidal.

【0004】0004

【発明が解決しようとする課題】従来の半導体装置の製
造方法は以上のように構成されているので、得られる配
線パターンの断面形状が台形となるため、パターン線幅
が小さくなったとき、その断面積が小さくなり、配線抵
抗が大きくなるという問題点があった。
[Problems to be Solved by the Invention] Since the conventional semiconductor device manufacturing method is configured as described above, the cross-sectional shape of the resulting wiring pattern is trapezoidal, so when the pattern line width becomes small, There were problems in that the cross-sectional area became smaller and the wiring resistance increased.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、微細パターン化されても配線の
断面積が小さくならない半導体装置の製造方法を提供す
ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the cross-sectional area of wiring does not become small even when finely patterned.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体装
置の製造方法は、基板上に形成したフォトレジストパタ
ーンにレジストよりも薄い膜厚の蒸着膜を設け、レジス
トパターン側壁部をエッチングしてレジストにT型の溝
を形成した後、蒸着,リフトオフによりT型形状金属パ
ターンを形成するようにしたものである。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention provides a photoresist pattern formed on a substrate with a deposited film having a thickness thinner than that of the resist, and etches the sidewalls of the resist pattern to form a photoresist pattern. After forming a T-shaped groove, a T-shaped metal pattern is formed by vapor deposition and lift-off.

【0007】[0007]

【作用】この発明においては、従来の写真製版でフォト
レジストを加工後、そのフォトレジストより薄い膜厚の
蒸着膜を一旦形成し、それをマスクとしてフォトレジス
トのパターン側壁部を除去し、フォトレジストを加工し
T型の溝を設けるようにしたから、そのフォトレジスト
パターンをマスクに蒸着,リフトオフした金属パターン
の断面はT型となる。
[Operation] In this invention, after processing a photoresist using conventional photolithography, a vapor deposited film thinner than the photoresist is formed, and the pattern sidewalls of the photoresist are removed using this as a mask. Since the photoresist pattern is processed to provide a T-shaped groove, the cross section of the metal pattern obtained by vapor depositing and lifting off the photoresist pattern as a mask becomes T-shaped.

【0008】[0008]

【実施例】以下、この発明の一実施例を図について説明
する。図は本発明の一実施例による半導体装置の製造方
法を示すフロー断面図であり、図2と同一符号は同一ま
たは相当部分を示し、3はフォトレジスト2よりも薄い
膜厚の金属または誘電体である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The figure is a flow cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. The same reference numerals as in FIG. It is.

【0009】次に製造方法について説明する。図1(a
) に示すように従来例と同様にして、半導体基板1上
にフォトレジスト2を塗布し、任意の方法でフォトレジ
ストをパターニングする。そして図1(b) に示すよ
うにフォトレジスト2より薄い金属又はSiOx等誘電
体3を基板全面に蒸着して、フォトレジスト2の上面及
び開口側面の基板側の一部を金属または誘電体3により
マスキングする。
Next, the manufacturing method will be explained. Figure 1 (a
) As shown in the conventional example, a photoresist 2 is applied onto a semiconductor substrate 1, and the photoresist is patterned by an arbitrary method. Then, as shown in FIG. 1(b), a metal or dielectric material 3 such as SiOx, which is thinner than the photoresist 2, is deposited on the entire surface of the substrate, and the upper surface of the photoresist 2 and a part of the side surface of the opening on the substrate side are covered with the metal or dielectric material 3. Masking is performed.

【0010】次いでこの金属または誘電体3をマスクと
してプラズマアッシングのような等方的エッチングでレ
ジスト2の側壁部(図1(c) に示す領域A)を除去
し、その後、金属又は誘電体3を除去するとフォトレジ
スト2にT型の溝が形成され、この状態で基板1をエッ
チング(図1(d) 参照)して溝を設け、図1(e)
 に示すように基板全面に電極用金属4を蒸着,リフト
オフすることによりパターニングして図1(f) に示
されるようなT字断面形状の電極4′を得る。
Next, using this metal or dielectric material 3 as a mask, the side wall portion of the resist 2 (area A shown in FIG. 1(c)) is removed by isotropic etching such as plasma ashing, and then the metal or dielectric material 3 is removed. When removed, a T-shaped groove is formed in the photoresist 2. In this state, the substrate 1 is etched (see FIG. 1(d)) to form the groove, and as shown in FIG. 1(e).
As shown in FIG. 1, an electrode metal 4 is deposited on the entire surface of the substrate and patterned by lift-off to obtain an electrode 4' having a T-shaped cross section as shown in FIG. 1(f).

【0011】このように本実施例によれば、基板1上の
フォトレジスト2をパターニングした後、全面にフォト
レジスト2より薄い金属又は誘電体3を蒸着し、これを
マスクとしてレジスト2をエッチングしてレジスト2の
パターン側壁部を除去し、レジスト2断面をT字型の溝
を有するように加工するようにしたから、このレジスト
を用いて電極用金属4を蒸着,リフトオフするとT字断
面形状の電極4′が得られ、従来の方法に比べ電極の断
面積が増大し、微細化されても配線抵抗の小さな配線パ
ターンを得ることができる。
According to this embodiment, after patterning the photoresist 2 on the substrate 1, a metal or dielectric material 3 thinner than the photoresist 2 is deposited on the entire surface, and the resist 2 is etched using this as a mask. The sidewalls of the pattern of the resist 2 are removed and the cross section of the resist 2 is processed to have a T-shaped groove. When the electrode metal 4 is evaporated using this resist and lifted off, a T-shaped cross section is formed. The electrode 4' is obtained, the cross-sectional area of the electrode is increased compared to the conventional method, and a wiring pattern with low wiring resistance can be obtained even when miniaturized.

【0012】なお、図1(c) でのレジスト2のA領
域の除去方法として、誘電体3をマスクとして基板1上
を露光し、光の回折現象によりA領域を感光して、その
後現像してA領域を除去する方法もある。
[0012] As a method for removing the A area of the resist 2 in Fig. 1(c), the substrate 1 is exposed to light using the dielectric 3 as a mask, the A area is exposed to light due to the diffraction phenomenon of light, and then developed. There is also a method of removing the A area.

【0013】また基板1に溝を設けない場合は、図1(
d) におけるエッチング工程を省略することができる
In addition, when no groove is provided in the substrate 1, as shown in FIG.
The etching step in step d) can be omitted.

【0014】[0014]

【発明の効果】以上のように、この発明に係る半導体装
置の製造方法によれば、基板上のフォトレジストパター
ンの一部を蒸着膜でマスキングした後、フォトレジスト
の一部を除去し、フォトレジストをT型に加工したので
、このフォトレジストをマスクに金属パターンを蒸着,
リフトオフで形成すると、微細パターンでも断面積の大
きなT型パターンが形成され、配線抵抗の小さい金属パ
ターンを得ることができるという効果がある。
As described above, according to the method of manufacturing a semiconductor device according to the present invention, after masking a part of the photoresist pattern on the substrate with a vapor-deposited film, part of the photoresist is removed and the photoresist pattern is removed. Since the resist was processed into a T-shape, a metal pattern was vapor-deposited using this photoresist as a mask.
When formed by lift-off, a T-shaped pattern with a large cross-sectional area is formed even in a fine pattern, and there is an effect that a metal pattern with low wiring resistance can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この発明の一実施例による半導体装置の製造方
法を示す工程断面図である。
FIG. 1 is a process cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を示す工程断面図
である。
FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1    半導体基板 2    フォトレジスト 3    金属又は誘電体膜(蒸着膜)4    電極
パターン用金属膜 4′  電極パターン用金属膜
1 Semiconductor substrate 2 Photoresist 3 Metal or dielectric film (deposited film) 4 Metal film for electrode pattern 4' Metal film for electrode pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  基板上にレジストを塗布してパターニ
ングした後、全面に金属を蒸着,リフトオフして金属電
極パターンを形成する工程を有する半導体装置の製造方
法において、基板上のレジストをパターニングした後、
該レジストよりも薄い蒸着膜を全面に設ける工程と、該
蒸着膜をマスクとしてレジストの一部をエッチング除去
し、レジストに断面T型の溝を形成する工程と、上記蒸
着膜を除去した後、全面に金属パターンを蒸着,リフト
オフして金属電極パターンを形成する工程とを含むこと
を特徴とする半導体装置の製造方法。
Claim 1: A method for manufacturing a semiconductor device comprising a step of coating a resist on a substrate and patterning it, then vapor depositing metal on the entire surface and lift-off to form a metal electrode pattern, after patterning the resist on the substrate. ,
a step of providing a vapor deposited film thinner than the resist over the entire surface; a step of etching away a part of the resist using the vapor deposited film as a mask to form a groove with a T-shaped cross section in the resist; and after removing the vapor deposited film, 1. A method for manufacturing a semiconductor device, comprising the steps of depositing a metal pattern on the entire surface and performing lift-off to form a metal electrode pattern.
JP10632491A 1991-03-26 1991-03-26 Manufacture of semiconductor device Pending JPH04298049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10632491A JPH04298049A (en) 1991-03-26 1991-03-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10632491A JPH04298049A (en) 1991-03-26 1991-03-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04298049A true JPH04298049A (en) 1992-10-21

Family

ID=14430741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10632491A Pending JPH04298049A (en) 1991-03-26 1991-03-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04298049A (en)

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