JPH0425893A - Image memory access control device - Google Patents

Abstract

PURPOSE:To enable fast plotting by providing a display controller, which is equipped with an image memory composed of a DRAM and a plotting coordinate generating circuit, with a page mode and a normal access mode for access to the image memory. CONSTITUTION:When a Y address does not vary at the time of next access in the normal access mode, an RAS.CAS generating circuit 7a enters page mode and a CAS signal 9 is varied from 'H' to 'L' while an address switching signal 8 and an RAS signal 10 are held at 'L'. When the Y address varies in next access in the page mode (when a Y address counter 12 is in an increment, decrement, or load state), the RAS signal 10 is also held at 'H' and the normal access mode is entered. Thus, when the plotting coordinate generating circuit 1A does not vary the Y address 3, the image memory 11 is accessed in page mode, so fast linear plotting is realized.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a display control device equipped with a DRAM memory and a drawing coordinate generation circuit, and particularly to a device that controls access to an image memory so as to enable high-speed drawing of straight lines. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional display control device for the image memory 11 consisting of DRAM, and FIG.
3 is a time chart showing changes in the access signal to the image memory 11 in the figure. In FIG. 4, the drawing coordinate generation circuit 1 outputs the X address 2°Y address 3 and the access signal 6 of the drawing coordinate every time it generates the drawing coordinate. The address control circuit 4 sets the Y address 3 to low (Ro w,
Column) address, X address 2 to column (Co 1
umn (meaning row) address, and when the address switching signal 8 is “H”, the row address (Y address) 3 is assigned,
Similarly, when the address switching signal 8 is +1, column address (X address) 2 is selected and output as image memory address 5. When the RAS-CAS generating circuit 7 receives the access signal 6, At the timing shown in the time chart in Figure 5, an active low RAS signal 10° CAS signal 9 and an address switching signal 8 of "H" and "L" are output, and the D
Controls access to the image memo January 1 composed of RAM (that is, gives a row address (Y address) and a column address (X address) to the image memory 11).

[Problem to be solved by the invention]

However, in the above conventional device, (
X address 2. Even if the Y address 3) is generated at high speed, there is a problem that drawing cannot be performed faster than the normal write cycle time of the image memory. Therefore, it is an object of the present invention to provide an image memory access control device that can solve this problem.

[Means to solve the problem]

In order to solve the above problems, the device of the present invention has a D
In a display control device equipped with an image memory (such as 11) constituted by RAM and a drawing coordinate generation circuit (such as 18), the X coordinate of the coordinates generated by the drawing coordinate generation circuit does not change, but only the X coordinate. means (address control circuit 4.RAS-C
AS generating circuit 7A, etc.).

[For use]

The DRAM row address that constitutes the image memory is assigned to the X coordinate address, and the column address is assigned to the Page mode (that is, CAS while keeping RAS signal 10 “L”)
By repeating the change of signal 9 from "'H" to "L", use a mode in which only the column address (X address) changes without changing the row address (Y address) to the image memory. Add a means to access image memory. That is, when drawing a straight line, if this straight line has an ungrooved inclination of 45 degrees with respect to the X axis, the X coordinate remains unchanged and the X coordinate changes a predetermined number of times by incrementing the address. The drawing is performed. When drawing continues in which only the X coordinate changes in this way, the image memory made up of DRAM can be accessed in page mode, making it possible to speed up the drawing.

【Example】

Next, the present invention will be explained in detail using FIGS. 1 to 3. FIG. 1 is a block circuit diagram showing a configuration as an embodiment of the present invention, and corresponds to FIG. 4, and FIG. 2 is a time chart of access signals to the image memory 11 in FIG. 1, and FIG. handle. In FIG. 1, compared to FIG. 4, the drawing coordinate starting path and the RAS-CAS generation circuit are new circuits IA and 4, respectively.
It has been replaced by 7A. The new drawing coordinate generation circuit IA is a straight line generator 16. X address counter 12. Consisting of Y address counter 13, and a new RAS-C
The AS generating circuit 7A inputs the Y address control signal 15 in addition to the access signal 6 from the drawing coordinate generating circuit IA.
RAS signal 10° CAS signal 9. Outputs address switching signal 8. A straight line generator 16 calculates the coordinates of the straight line and inputs each X address counter 12 . X address 2. via Y address counter 13. X address control signal 14 for changing Y address 3. A Y address control signal 15 is output. X address control signal 14. The Y address control signal 15 is connected to the X address counter 12 as shown in Tables 1 and 2 below.
．． Y address counter 13 However, in Table 1, unchanging the X address counter 12 means keeping its output X address 2 unchanged, and incrementing and decrementing means synchronizing the X address 2 with a clock signal not shown. Loading an initial value means loading an initial value given from a means not shown in the linear generator 16 and outputting it as an X address. The above operation is the same for the X address counter 13 in Table 2, except that the X address 2 is replaced by the Y address 3. RAS-CAS generation circuit 7A receives Y address control signal 1
5, the access mode to the image memory 11 is switched as shown in Table 3 below. Next, FIG. 2 will be explained with reference to FIG. 1. In the time chart for image memory address 5 in FIG. 2 (and FIG. 3, which will be described later), R means a row address (Y address), and C means a column address (X address). Now, in the next access in normal access mode, Y
If the address does not change, the RAS/CAS generation circuit 7A goes into page mode, and the address switching signal 8 and RAS signal 10 are set to "L" as shown in the time chart of FIG.
”, change the CAS signal 9 from °゛H to “L”. Also, in the next access in page mode, Y
When the address changes (when the X address counter 12 is incremented, decremented, or loaded), the RAS signal 10 is also set to "H" to perform the normal access mode. FIG. 3 is a diagram comparing the access time to the image memory when drawing a specific straight line between the conventional method and the method of the present invention. That is, FIG. 3(A) shows a part (line segment) of a straight line to be drawn, and it is assumed that ■ to ■ are coordinate points arranged in order on this straight line. Next, FIG. 3(B) shows the RAS signal 10. when the coordinate points ■ to ■ are accessed sequentially using the conventional method. CAS signal 1
11 is a time chart showing changes in image memory address 5, and FIG. 3(C) is a time chart corresponding to FIG. 3(B) when coordinate points ■ to ■ are sequentially accessed by the method of the present invention. be. That is, since the page mode is used for three out of five accesses as shown in FIG. 3(C), drawing is completed in a shorter time than in FIG. 3(B).

【Effect of the invention】

According to the present invention, when the drawing coordinate generation circuit 1 does not change the Y address 3, the screen memory is accessed in page mode, so that high-speed straight line drawing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a configuration as an embodiment of the present invention, FIG. 2 is a time chart of image memory access in FIG. 1, and FIG. 3 is an image of the present invention when drawing a specific straight line. FIG. 4 is a conventional block circuit diagram corresponding to FIG. 1, and FIG. 5 is a time chart of image memory access in FIG. 4. IA: Drawing coordinate generation circuit, 2: X address, 3: Y address, 4 Near address control circuit, 5: Image memory address, 6: Access signal, 7A: RAS/CAS generation circuit, 8 Near address switching signal, 9: CAS signal, 10:RA
S signal, Step 1: Image memory, 12: X address counter, 13: Y address counter, 14: X address control signal, 15: Y address control signal, 16: Linear generator. Diagram

Claims (1)

[Scope of Claims] 1) In a display control device equipped with an image memory constituted by a DRAM in which the X coordinate is assigned to a column address and the Y coordinate is assigned to a row address, and a drawing coordinate generation circuit, the drawing coordinate generation circuit generates If only the X coordinate changes without changing the Y coordinate, the image memory is accessed in page mode, and if the Y coordinate also changes, the image memory is accessed in normal access mode. 1. An access control device for an image memory, comprising means for controlling access to an image memory.