JPH08241418A - Image storage device and image data storing method - Google Patents

Abstract

PURPOSE: To increase the working speed of an entire system by preventing the skews produced between signals and also reading easily and simultaneously the lines. CONSTITUTION: A memory control part includes an X counter 27 which generates 8 row address (X address), 8 Y counter 28 which generates a column address (Y address), a latch 29 which delays the Y address, a 1st multiplexer 30 which performs the switching between the Y address that is directly inputted from the counter 28 and the Y address that is inputted via the latch 29, a 2nd mulitplexer 31 which performs the switching between the Y address inputted from the multiplexer 30 and the X address inputted from the counter 27, an address selection control part 32 which controls both multiplexers 30 and 31, and a RAS/CAS signal generation part 33 which produces the 1st and 2nd RAS signals 22 and 23 and a CAS signal 24 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage device, and more particularly to an image storage device for storing image signals for raster scanning.

[0002]

2. Description of the Related Art Conventionally, this type of image storage device processes image data by dividing it into a plurality of memory blocks.

That is, like the first conventional example shown in FIG. 6, from the first memory block 52 for storing the first data sent from the first data signal 51 and the second data signal 53. A second that stores the second data that is sent
The memory block 54 is controlled by the memory controller 55. Specifically, the first and second memory blocks 5
An address signal 56 in which a row address and a column address are multiplexed for each memory block in units of 2 and 54, and a row address strobe (RA) that takes an input timing for specifying a column address.
S) A row address strobe (colummn address strobe) that takes input timing for signal 57 and row addressing.
be: CAS) signal 58 is commonly input.

Alternatively, as in the second conventional example shown in FIG. 7, the address signals 60 and 61 and the RAS signal 62 are supplied from the memory control unit 59 to the respective blocks composed of the first and second memory blocks 52 and 54. , 63 and the CAS signal 6
Input 4 and 65 independently.

[0005]

However, in the first conventional example described above, the address signal 56, the RAS signal 57, and the C signal common to the memory blocks 52 and 54 are common.
Since the AS signal 58 is input, it is convenient when all the memory blocks always access the same address, but it differs for each block in every read (read) and write (write) or every read cycle. There is a problem that an address (for example, an address shifted by one line) cannot be accessed. Further, in the case where the addresses shifted by one line are simultaneously accessed and the image data for the two lines is used for the calculation by the calculation unit 66, one memory, that is, the first memory block 52
Alternatively, the output signal of either one of the second memory blocks 54 must be connected to the line memory 67, which causes a problem that the processing system is complicated.

Further, in the second conventional example, since each signal is independently input to the first and second memory blocks 52 and 54, the memory controller 55 generates each of these signals. It is necessary to provide two circuits similar to the above, and there is a problem that skew may occur between a plurality of RAS signals and CAS signals when accessing at high speed.

The present invention has been made in view of the above problems, and aims at speeding up of the entire system by preventing the occurrence of skew between signals and easily reading each line simultaneously. It is an object of the present invention to provide an image storage device and an image data storage method capable of storing the image data.

[0008]

In order to achieve the above object, the present invention controls a plurality of memory blocks in which image data is independently input / output via a plurality of data signal lines, and the plurality of memory blocks. In the image storage device including a memory control unit, the memory control unit supplies address signals to the plurality of memory blocks through a single address signal line, and a plurality of RAs.
RAS signal supply means for sequentially supplying independent RAS signals to each of the memory blocks via the S signal line, and CAS for supplying a common CAS signal to each of the plurality of memory blocks via a single CAS signal line. It is characterized in that it is provided with a signal supply means, and further that the memory control section has a delay means for delaying the output timing of the column address.

Further, according to the present invention, in a method of storing image data for processing image data by inputting / outputting a plurality of data signal lines to / from each of a plurality of memory blocks, a column address is sequentially assigned to each of the plurality of memory blocks. A plurality of RAS signals are sequentially supplied to a plurality of memory blocks, a row address is supplied to the plurality of memory blocks, and a CAS signal is commonly supplied to a plurality of memory blocks.

[0010]

According to the above image storage device and image data storage method, an address signal in which a row address and a column address are multiplexed is supplied to a plurality of memory blocks via a single address signal line, and a plurality of RAS signals are supplied. The RAS signal is sequentially supplied to each of the plurality of memory blocks via the line, and the CAS signal is commonly supplied to the plurality of memory blocks via the single CAS signal line.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image storage device according to the present invention.

In the figure, first and second input signals (analog signals) 1 and 2 as image data are input to the first and second A / D converters 3 and 4. Next, the image data is converted into digital signals by the A / D converters 3 and 4 based on the A / D conversion clock 6 from the memory control unit 5, and then the first and second tri-state gates 7, 8
And is stored in the first and second memory blocks 11 and 12, respectively, under the control of the memory control unit 5 described later via the first and second data signals 9 and 10. And
The image data stored in the first and second memory blocks 11 and 12 is read from the first and second memory blocks 11 and 12 under the control of the memory control unit 5 described later, and the memory control unit The first and second D / A converters 1 based on the D / A conversion clock 13 output from
The signals are converted into analog signals at 4 and 15 and output as first and second output signals 16 and 17. Further, the image data read from the first and second memory blocks 11 and 12 is input to the arithmetic unit 18 and arithmetically operated to generate the third D
The A / A converter 19 converts the analog signal by the D / A conversion clock 13 and outputs the analog signal as the third output signal 20.

Thus, the memory control unit 5 controls the input / output of image data and the refresh of the first and second memory blocks 11 and 12. For this reason, the memory control unit 5 uses the first and second memory blocks 11 and 12
Address signal, first and second RAS signals 22, 2
3, a CAS signal 24, a write control signal 25 and an output control signal 26 are generated.

FIG. 2 is a time chart showing the generation timings of the first and second RAS signals 22 and 23 and the CAS signal 24 when performing a normal access.

That is, the first column address (row 1) which is the Y address for accessing the first memory block 11 is output to the address signal 21 and the first RAS signal (RAS (1)) 22 is output. Set to low level. Then, the second column address (row 2) which is the Y address for accessing the second memory block 12 is set to the address signal 21.
To the low level of the second RAS signal (RAS (2)) 23. Next, the row address (co
(1.0) is output to the address signal 21, and the CAS signal 24 is set to low level. Further, the CAS signal 24 repeats the low level and the high level while sequentially updating the X address to access the first and second memory blocks 11 and 12.

FIG. 3 is a time chart showing the timing of the refresh cycle. As can be seen from this FIG. 3, one CAS signal 24 corresponds to the first RAS signal 2
By sequentially inputting 2 and the second RAS signal 23, the first memory block 11 and the second memory block 12 can be sequentially refreshed.

FIG. 4 is a block diagram showing the details of the main part of the memory control unit 5. The memory control unit 5 has an X counter 27 for generating a row address (X address) and a column address (Y address). Y counter 28 to generate and Y
A latch 29 for delaying the output of the address for a predetermined time, and Y
Y address and latch 2 directly input from the counter 28
A first multiplexer 30 for switching the Y address input via 9 and a second multiplexer 31 for switching the Y address input from the first multiplexer 30 and the X address input from the X counter 27.
An address selection control section 32 for controlling the first and second multiplexers 30 and 31, and a first and second R
R for generating AS signals 22 and 23 and CAS signal 24
The AS / CAS generation unit 33 is provided.

In the memory controller 5 thus constructed, the X counter 27 counts the clock signal from the clock signal line 34 and generates the X address. Also,
The Y counter 28 counts the horizontal sync signal from the horizontal sync signal line 35 and generates a Y address.

When writing image data, however, the first multiplexer 30 selects the output of the Y counter 28 as the Y address by the address selection control section 32 based on the horizontal synchronizing signal, the vertical synchronizing signal and the clock signal. Then, the Y address is input to the second multiplexer 31. Then, the second multiplexer 31 outputs the Y address as a column address and the input from the X counter 27 as a row address. In this case, RAS
The CAS generating unit 33 generates the first RAS signal 22 and the second RAS signal 23 when outputting the column address, and the CAS signal 24 when outputting the row address.
Generate. In this case, the first memory block 11 and the second memory block 12 access the same Y address and write in the respective memories, so that the first RAS
The first column address (ro when the signal 22 is set to low level)
w 1) and the second column address (row 2) when making the second RAS signal 23 low are the same address signal.

When the image data is read, the same line data in the first and second memory blocks 11 and 12 is read out and the calculation is performed by the calculation unit 18. The first memory block 11 and the second memory block. There is a case in which the read operation is performed by shifting, for example, by one line.

In the above, similar to the case of writing the above-mentioned image data, the first column address (row 1) output from the first memory block 11 and the second column address output from the second memory block 12 are output. The column address (row 2) is output as the same address signal.

On the other hand, in the above, the first column address (row 1) for the first memory block 11 is the first
The Y address from the Y counter 28 is output by the multiplexer 30 of the first multiplexer 3 and the second column address (row 2) for the second memory block 12 is the first multiplexer 3
When 0, the Y address from the latch 29 that stores the address value of the Y counter 28 one line before is stored as the first and second column addresses by the second multiplexer 31.
And to the second memory blocks 11 and 12.
Since the X address is common even when the lines shifted by one line are read, the same CAS signal 24 and the same row address are output by the second multiplexer 31 and the RAS / CA.
It is output from the S generation unit 33.

In the above embodiment, the selection of the first and second column addresses is changed by the first multiplexer 30, and the output of the latch 29 one line before is selected as the second column address, and the second multiplexer is selected. It goes without saying that the image data read out from the memory block 12 may be used as a reference to read the image data of one line before from the first memory block 11 and the arithmetic unit 18 may perform the arithmetic operation.

FIG. 5 is a block diagram showing the details of the essential parts of another embodiment of the memory controller 5, in which a second Y counter 36 is provided in place of the latch 29 of FIG.

That is, in the other embodiments, the first
Of the Y-counter 2 for generating the first column address (row 1) supplied to the second memory block 11 and the second column address (row 2) supplied to the second memory block 12.
By providing 8 and 36 respectively and setting the initial values separately, it is possible to simultaneously read two lines separated by an arbitrary number of lines.

The present invention is not limited to the above embodiment, and various modifications can be considered without departing from the scope of the invention. That is, the input signal and the output signal may be one, and the internal signal may be two independent signals. Further, it is needless to say that the number of memory blocks is not limited to two and can be applied to two or more memory blocks.

[0028]

As described in detail above, according to the image storage device and the image data storage method of the present invention, it is possible to select any line and read each line simultaneously, and read different lines. It becomes easy to calculate.

Further, the maximum power consumption of the memory block can be suppressed by inputting the RAS signal of each memory block independently and sequentially inputting the RAS signal.

Further, since the CAS signals are made common, skew between a plurality of CAS signals does not occur, and the speedup of the entire system is facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image storage device according to the present invention.

FIG. 2 is a RAS signal and C for normal access
7 is a time chart showing the generation timing of an AS signal.

FIG. 3 is a time chart showing the timing of a refresh cycle.

FIG. 4 is a block diagram showing details of a main part of a memory control unit.

FIG. 5 is a block diagram of details of a main part of another embodiment of the memory control unit.

FIG. 6 is a block diagram showing a first conventional example.

FIG. 7 is a block diagram showing a second conventional example.

[Explanation of symbols]

 5 memory control section 9 first data signal 10 second data signal 11 first memory block 12 second memory block 21 address signal 22 first RAS signal 23 second RAS signal 24 CAS signal

Claims (3)

[Claims] 1. An image storage device, comprising: a plurality of memory blocks into which image data is independently input / output via a plurality of data signal lines; and a memory control unit for controlling the plurality of memory blocks. The control section supplies address signal supply means for supplying an address to each of the plurality of memory blocks through a single address signal line, and sequentially separate columns for each memory block through a plurality of column address strobe signal lines. A column address strobe signal supplying means for supplying an address strobe signal and a row address strobe signal supplying means for supplying a common row address strobe signal to each of the plurality of memory blocks via a single row address strobe signal line are provided. An image storage device characterized in that. 2. The image storage device according to claim 1, wherein the memory control unit has a delay unit that delays the output timing of the column address. 3. A method of storing image data, wherein a plurality of data signal lines are input to and output from each of a plurality of memory blocks to process image data, wherein a column address is sequentially supplied to each of the plurality of memory blocks and a plurality of column addresses are supplied. The column address strobe signal of is sequentially supplied to a plurality of memory blocks, the row address is supplied to the plurality of memory blocks, and the row address strobe signal is commonly supplied to the plurality of memory blocks. Method.