JPH02130792A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To make plural memory areas randomly accessible at high speeds by independently arranging a code section memory and data section memory and discriminating access whether or not it is made to the same page to each memory. CONSTITUTION:In case of outside-page access to a code section memory 2, the page address A of the preceding code section access is stored in a register 3. When a CPU 1 makes access to the code memory of a row address B, a comparator 4 compares the addresses A and B with each other and detects discordance. The output 15 of the comparator 4 is inputted to a timing control circuit 6 and signals, the inverse of RAS 18, the inverse of CAS 19, and a code memory row/column (L/C) switching signal 16 are sent so as to execute a row and column addressing cycles. In case of outside-code access to a data section memory 7, a comparator 9 detects discordance by comparing the output of a register 8 with the current row address. The output 22 of the comparator 9 is inputted to a control circuit 11 which outputs signals, the inverse of CAS and RAS, and an L/C switching signal 23.

Description

[Detailed description of the invention] 1. Upright! The present invention relates to a memory access control circuit, and particularly to a DRA
M (Dynamic RandolAccess
The present invention relates to a memory access control circuit in page mode operation (Memory).

Generally speaking, there is a method that utilizes the page mode operation of DRAM as a method for the CPU to access DRAM at high speed. This DRAM page mode operation is an operation in which if the DRAM addresses to be accessed are within the same page (that is, the page addresses are the same), only the addressing cycle of the address within the page is performed and access is performed at high speed.

In that case, if the row address is the page address, the column address is the in-page address, and only the addressing cycle for the column address needs to be performed.

In this case, when the CPU accesses the memory, only the address is monitored to determine whether the access is within the same page. If the access is within the same page, the access is performed using only the addressing cycle of the column address.

On the other hand, if the address determines that the access is outside the page, the row address is given to the DRAM again (
(row addressing cycle) and a column address (column addressing cycle).

However, in the access method described above, it is determined whether the access is within the same page or not based only on the address, so if the code and data are located in different memory areas (generally, they are ), when code and data were accessed randomly, a row addressing cycle and a column addressing cycle were always performed when changing from accessing code to accessing data (or vice versa).

Therefore, the incidence of accesses within the same page decreases,
This has the disadvantage that the frequency of execution of row addressing cycles increases and overall memory access performance deteriorates.

1. Summary of the present invention An object of the present invention is to provide a memory access control circuit that can perform high-speed access without reducing overall memory access performance even when multiple memory areas are randomly accessed. It is to provide.

The memory access control circuit of the present invention is a memory access control circuit that accesses a plurality of memories by sending a page address and an intra-page address in response to an address from a CPU, and the memory access control circuit accesses a plurality of memories. Correspondingly provided,
holding means for holding the last page address accessed by each memory, and a holding means provided corresponding to each of the memories, the page address currently being accessed when accessing the memory and the holding output of the holding means; The present invention is characterized in that it has a comparison means for comparing the page addresses, and a prohibition means for prohibiting sending of the page address when the comparison result of the comparison means shows a match.

Shake Week Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of a memory access control circuit according to the present invention.

In the figure, the memory access control circuit according to an embodiment of the present invention includes cput, a code section memory 2, and a register 3 that stores the page address (row address) of the previous (that is, last) access to the code section memory 2. and,
A comparator 4 compares the output 14 of the register 3 with the current page address 12, and a
It is configured to include a column address switching circuit 5 and a timing control circuit 6 for the code section memory 2.

The memory access control circuit according to the present embodiment also includes a data section memory 7, a register 8 that stores the page address of the previous (that is, last) access to the data section memory 7, and an output 21 of the register 8 and the current page address. , a row/column address switching circuit 10 for the data section memory 7 , and a timing control circuit 11 for the data section memory 7 .

The column address 27 output from the CPUI is input to the row/column address switching circuit 5 of the code section memory 2 and the row/column address switching port ito of the data section memory 7. Row address 12 output from CPU1
is the row/column address switching circuit 5 of the code section memory 2
, row/column address switching circuit 1 of data section memory 7
0, register 3. It is input to the register 8, one of the inputs of the comparator 4, and one of the inputs of the comparator 9.

The other input of comparator 4 is the output 14 of register 3.
is input, and the output 21 of the register 8 is input to the other input of the comparator 9.

The output 15 of the comparator 4 and the code memory access strobe 13 which is the output of the CPUI are input to the timing control circuit 6. Code memory RASI8 and code memory CAS19 which are the output of the timing control circuit 6
are rτ1 . of the code section memory 2, respectively. The row/column address switching timing signal 16 input to the ζ terminal) IA
has been entered.

The output 22 of the comparator 9 and the data memory access strobe 20 which is the output of CPtJl are input to the timing control circuit 10. Data memory RA325 and data memory CA which are the output of the timing control circuit 10
S26 are RAS and CAS of data section memory 7, respectively.
The row/column address switching timing signal 23 is input to the input terminal and is input to the row/column address switching circuit 10. The memory address 24 which is the output of the row/column address switching circuit 10 is input to the input terminal HA of the data section memory 7.

Next, the operation of the memory access control circuit of this embodiment having such a configuration will be explained with reference to FIGS. 1 and 2. FIG. 2 shows a CP using the memory access control circuit of this embodiment.
5 is a timing chart illustrating an example of an operation when the UI accesses a memory.

The memory access according to this embodiment includes the following 6
There are several types of cases, and FIG. 2 illustrates these cases (1) to (2).

Case ■→Out-of-page access to code section memory 2 Case ■→In-page access to code section memory 2 (1
Case ■→Out-of-page access to data section memory 7 Case ■→In-page access to data section memory 7 (when the previous access was to code section memory 2)
(If the previous access was to data section memory 7) Case ■→Intra-page access to code section memory 2 (1
Case ■ → In-page access to data section memory 7 (in the case of previous access or to data section memory 7)
(When the previous access was to the code section memory 2) Case (2): First, it is assumed that the page address "A" at the time of the previous access to the code section is stored in the register 3. In this state, if the CPU 1 accesses the code memory at row address r13J, the comparator 4 causes the output 14 of the register 3, that is, rA
J and the current row address 12 from the CPUI, i.e.
B'' is compared, and as a result, a mismatch is detected. When the output 15, which is the detection result, is given to the timing control circuit 6, the timing control circuit 6 executes a code to execute two addressing cycles, a row addressing cycle and a column addressing cycle, as shown in FIG. Memory RAS18, code memory Cτ119
and a code memory row/column switching signal 16.

In the case of case ■: This case ■ continues to be CP as case ■
This is a case where the UI accesses the code memory at row address "B". At this time, the comparator 4 compares the output 14 of the register 3, ie, "B" (rB4 is stored in the access in case 2) and the current row address 12, ie, rB from the CPUI, and as a result - will be examined. Output 15 which is this detection result
is given to the timing control circuit 6, the timing control port l! 86 is the second row address because there is no change in row address 12.
As shown in the figure, the code memory RAS18, the code memory CAS19, and the code memory row/column switching signal 16 are sent out so that the row addressing cycle is omitted and only the column addressing cycle is executed.

Case (2): First, it is assumed that the register 8 has recorded and incremented the veggie address r W at the time of the previous data access. In this state, if the CPU 1 accesses the data memory at row address "X", the comparator 9 will output the output r of the register 8 as in case ①.
WJ and the current row address "x" are compared, and a mismatch is detected as a result. When the output 22 resulting from this is given to the timing control circuit 11, the timing control circuit 11 executes the data so as to execute two addressing cycles, a row addressing cycle and a column addressing cycle, as shown in FIG. memory RA
S25, data memory CAS26 and data memory row/column address switching signal 23 are sent out.

In the case of case ■: This case ■ continues to be CP as case ■.
This is a case where ut accesses the data memory at row address rXu. At this time, as in case (2), the comparator 9 compares the output rXu of the register 8 with the current row address "x", and as a result, the timing control circuit 11 starts the row addressing cycle as shown in FIG. Data memory RAS25 and data memory C are omitted so that only the column addressing cycle is executed.
AS26 and data memory row/column address switching signal 23 are sent out.

Case (2): In this case, cput accesses the code memory at a row address r13J that is different from the row address "X" accessed in case (2). This row address rBJ is the same as the row address in case (2) when the code memory was last accessed.In this case, the output 14 of register 3 is
In other words, "B"("B" when there is no access in case ■)
is stored) and the current row address "B" from the CPUI, and as a result, as in case (2), there is no change in the row address, so the timing control circuit 6 is changed as shown in FIG. The code memory R shoulder 18, code memory CAS 19, and code memory row/column address switching signal 16 are sent out so that the row addressing cycle is omitted and only the column addressing cycle is executed. This means that even if data memory accesses with different row addresses (cases ■ and cases ■) are executed between two accesses to the same code memory in case ■ and case ■, the access to code section memory 2 in case ■ is This means that operation access can be performed in the page mode without being affected by access to the internal memory 7.

Case ■: In this case ■, as in case ■, the comparator 9 outputs the output 21 of the register 8, that is, “X
” (“X” is stored when accessed in case ■) and the current row address “X” from the CPU, and as a result, the timing control circuit 11 performs the row address “X” as shown in FIG. The data memory RAS25. Data memory CAS 26 and data memory row/column address switching signal 23 are sent out.

This means that even if a code memory access (case ■) with a different row address is executed between two accesses to the same data memory in case ■ and case ■, the access to data part memory 7 in case ■ is This means that it can be accessed in page mode operation without being affected by access to .

5) As explained above, the present invention arranges the code section memory and the data section memory independently, and determines whether or not the access is within the same page for each memory. Even if data and data are accessed randomly, the issue rate of accesses within the same page does not decrease, and there is an effect that deterioration in overall memory access performance can be suppressed and access can be made at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory access control circuit according to an actual example of the present invention, and FIG. 2 is a timing chart 1 to 1 showing the operation example of FIG. 1. Explanation of symbols of main parts 1...CPU 2...Code section memory 3...Data section memory 3.8...Register 4.9... ···comparator

Claims (1)

[Claims] (1) A memory access control circuit that sends page addresses and intra-page addresses in response to addresses from the CPU and accesses multiple memories, and is provided corresponding to each of the memories, and each memory is holding means for holding an accessed page address; and comparison means provided corresponding to each of the memories, for comparing the currently accessed page address and the holding output of the holding means when accessing the memory. and prohibition means for prohibiting transmission of a page address when the comparison result of the comparison means indicates a match.