JPH01227299A - Memory refresh control method - Google Patents

Abstract

PURPOSE:To prevent the occurrence of access waiting to the memory of a CPU due to the refresh of the memory by banking the structure of the memory, dividing it into plural pieces and refreshing the memory of a bank which is not accessed. CONSTITUTION:A DRAM is divided into (n) units of bank structures by addresses. When an access is made by the CPU through an address bus 4, one of banks 0-n to which the address to be accessed belongs is selected by a RAM selecting circuit 3. A CAS signal and a CAS signal are supplied from a RAS/CAS generating circuit 4 to the DRAM of the selected bank and a nor mal memory access can be attained. Only RAS signal is supplied from the generating circuit 4 to the banks which are not selected. In this case, DRAMs of these banks are refreshed in the access timing of the selected bank accessed by the CPU.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory refresh control method in a device equipped with a CPU and a dynamic RAM as its memory, it is possible to prevent the CPU from waiting for access to the memory due to memory refresh, and improve the processing performance of the CPU. In a memory refresh control method for a device equipped with a CPU and a dynamic RAM as memory, the memory configuration is divided into banks and divided into a plurality of parts, and the CPU accesses the memory almost periodically. The CPU is configured to refresh memory in a bank that is not accessed by the CPU at the access timing.

[Industrial application field]

The present invention relates to a memory refresh control method for refreshing (activating) memory in an apparatus equipped with a central processing unit (CPU) and a dynamic RAM (random access memory) as its storage device (memory).

[Conventional technology]

The main memory of an information processing device using a microcomputer as a CPU needs to be small. Generally Dynaminoku R
Consists of AM. Dynamic RAM needs to be periodically refreshed to retain its stored contents. For example, a refresh time of several hundred nanoseconds is required once every 15 microseconds. For this reason, as the performance of CPUs improves, bus occupancy due to refresh has become impossible to ignore. In other words, the refresh period and CPU access overlap, increasing the frequency at which CPU access must be delayed.

[Problem to be solved by the invention]

As mentioned above, when the CPU performance improves, the processing performance of the device increases by 10% due to bus occupancy caused by refresh.
The issue arose of not being able to perform at 0%.

An object of the present invention is to prevent the CPU from waiting for access to memory due to memory refresh, and
The objective is to improve the processing performance of the PU.

[Means to solve the problem]

In the present invention, in a memory refresh control method for a device equipped with a central processing unit and a dynamic RAM as memory, the memory configuration is divided into banks and divided into a plurality of pieces, and the central processing unit accesses the memory almost periodically. The memory of the bank that is not accessed by the central processing unit at the access timing is refreshed.

[For production]

If the above-mentioned method is used, even in a CPU that performs high-speed processing, when the CPU accesses memory, it is configured to refresh and nosh memory other than that memory, thereby eliminating the CPU wait time due to memory refresh. be able to.

〔Example〕

The configuration of an apparatus for carrying out the method of the present invention is shown in FIG. In the figure, the CPU to be connected to the address bus 1 and the data bus is omitted.

In addition to the CPU, address bus 11 and data bus 2, this device also has a dynamic RAM (D-RA) as memory.
M) 50 to 5n, RAM selection circuit 3 and RAS・C
An AS generating circuit 4 is provided. The D-RAM is divided into n bank configurations based on addresses. When accessing D-RAM from the CPU via address bus 1,
The RAM selection circuit 3 selects one of banks 0 to n to which the address to be accessed belongs. For the D-RAM of this selected bank, RAS-C
The RAS signal and the CAS signal are supplied from the AS generating circuit 4, allowing normal memory access. For unselected banks, RAS-CAS generation circuit 4
Only the RAS signal is supplied from. In this case, the D-RAMs of these banks are refreshed at the access timing of the selected bank accessed by the CPU.

A block circuit diagram of an apparatus for performing a memory refresh control method as an embodiment of the present invention is shown in FIG.
A control signal generating circuit used in the circuit shown in the figure is shown in FIG. FIG. 4 is a diagram showing a timing chart of the control signals.

This device has a 32-bit data bus configuration, with cp
u <not shown), D-RA) 1 divided into four banks from bank 0 to bank 3, and D-RAM address control I11 circuit 0 (
21) to D-RAM address control circuit 3 (24)
and an address bus 1, a data bus 2, and other buses that connect these.

Address signals for accessing the memory from the CPU are supplied to D-RAM address control circuits 21, 22, 23, and 24 via the address bus 1. Since D-RAM address control circuits 21 to 24 surrounded by chain lines have the same configuration, only the internal configuration of D-RAM address control circuit 0 (21) is shown in FIG. The D-RAM address control circuit uses a multiplexer (MP
X) 61 and 62, refresh address counter (
REF, ADD, C, ) 63, an OR gate 64, and an inverter 65. Address bus is MPX6
Connected to 1. ASELS is used as the selection input for MPX61.
An EL signal is generated, and the signal from the address bus is taken into the MPX 61 by this signal. The output of MPX61 is MP
Supplied to X62. Another input of the MPX 62 is supplied with the output of the refresh address counter 63.

The MPX 62 selects either the output of -PX 61 or the output of the refre/nosure address counter 63 according to the selection signals SEL O to SEL 3. In this example, when the SEL signal is "1", the output of the refresh address counter 63 is selected, and when the SEL signal is "0", the M
The output of PX61 is selected and enters the cpU access state.

Since refresh is performed in memory row units, the refresh address counter specifies the row. When the SEL signal is "1" and the RAS signal is input, the refre/nosure address counter is incremented by 1.

In this device, among the bits AO to AN of the memory address, AO and A1 are not used, and a bank is selected using A2 and A3. This is done by the logic circuit of FIG. 3, and A2. After receiving the input of A3, SEL O to SEL
3 signals are output. In D-RAM, neRAS
When the signal receiver receives this CAS signal (see the first and second stages in FIG. 4), it is read out, and when there is no *CAS signal (high level) with only this RAS signal, it is refreshed. Therefore, in the circuit shown in Figure 3, from this CAS O to *C
The AS 3 signal is the corresponding SEL O to 3 signal.
1", there is no output (high level). In FIG. 4, the symbol H indicates a high level, and the symbol H indicates a low level. The main RAS signal from the CPU is used as the main RAS O to *RAS 3 signals supplied to each bank.

In the time chart in Figure 4, bank 0 is the CPU
FIG. Therefore, this CAS O becomes low level at the timing of the main CAS signal from the CPU, and the other main CAS 1 to this main CAS
The signal at No. 3 remains at a high level. The refresh address counter is *CAS in bank 1 to bank 3.
At the end of the O signal, it is updated by adding 1. The SEL O signal is low, and the SEL 1 to SEL 3 signals are high.

In the present invention, as shown in FIG.
Select one D-RAM bank. CPU D-RAM
Most of the accesses are fetches that take in instructions, and in an as-needed CPU, this bank is accessed cyclically. Therefore, it is considered that there is no practical need to take particular measures to avoid concentration of CPU accesses on only one bank.

[Effects of the Invention] According to the present invention, CPtJ by memory refresh
Waiting for access can be eliminated, and the processing capacity of the CPU can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device that performs the memory refresh control method of the present invention, FIG. 2 is a block circuit diagram of a device that performs the memory refresh control method as an embodiment of the present invention, and FIG. 2
FIG. 4 is a circuit diagram showing a control signal generation circuit of the apparatus shown in FIG. 2, and FIG. 4 is a diagram showing a timing chart of control signals of the apparatus shown in FIG. In the figure, 1... address bus, 2... data bus, 3...
...RAM31 circuit, 4...RAS-CAS generation circuit, 21...D-RAM address control circuit 0.22
...D-RAM address control circuit 1.23...Low RA? I address control circuit 2.24...D-RAM address control circuit 3.25...Bank 0, 26...
・Bank 1.27... Bank 2, 28... Bank 3.31, 32... Inverter, 33, 34, 35, 36... Nantes gate, 3
7, 38, 39, 40... or gate, 50.
...D-RA gate bank 0. 51...D-RAM bank 1. 52...D-RAM bank 2. 5 n-D-RAM bank n1 61, 62... multiplexer, 63... refresh address counter, 64...
OR gate, 65...inverter.

Claims (1)

[Claims] In a memory refresh control method in a device equipped with a central processing unit and a dynamic RAM as memory, the configuration of the memory is divided into a plurality of banks, and the central processing unit refreshes the memory approximately periodically. 1. A memory refresh control method, characterized in that a memory in a bank that is not accessed by the central processing unit is refreshed at the access timing.