JPH04216671A - Photoelectric transducer - Google Patents

Abstract

PURPOSE:To obtain a high quality photoelectric transducer capable of sufficiently exhibiting element isolation function, in a photoelectric transducer having a structure wherein a non-single crystal intrinsic semiconductor layer is laminated on a plurality of pixel electrodes subjected to element isolation. CONSTITUTION:A non-single crystal intrinsic semiconductor layer on pixel electrodes 102 has a structure wherein an intrinsic semiconductor layer 103 containing microcrystal structure and an amorphous intrinsic semiconductor layer 104 are laminated in this order. The above-mentioned non-single crystal intrinsic semiconductor layer on the region except the above-mentioned pixel electrodes 102 is characterized by being the amorphous intrinsic semiconductor layer 104.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention utilizes element separation technology for photoelectric conversion elements to produce one-dimensional line sensors, solid-state imaging devices in which a photoelectric conversion film is laminated on a substrate forming a scanning circuit, a drive circuit, etc. The present invention relates to a photoelectric conversion device.

0002

2. Description of the Related Art As this type of photoelectric conversion device, one using a non-single crystal semiconductor is widely and generally well known. Among these, amorphous semiconductors mainly made of silicon can be produced at low temperatures and can be easily manufactured over large areas.
It is used as one-dimensional line sensors and stacked solid-state image sensors.

One of the structures of these photoelectric conversion elements is a Schottky layer between the pixel electrode and the intrinsic semiconductor layer (I layer).
Some have formed a bond (see Figure 3). Here, a pixel electrode 302 is formed on a base 301, and after forming I-type amorphous silicon 303 and P-type amorphous silicon 304, the electrode 302 is
Form 05. Here, the pixel electrode 302 and the I-type amorphous silicon 304 form a potential barrier against the hole through a Schottky junction. In such a configuration, the element isolation step was conventionally omitted because the I-type amorphous silicon 303 has a high resistance.

0004

[Problems to be Solved by the Invention] However, in the prior art, leakage of signal charges between pixels, that is, cross-stitch.
In particular, when trying to achieve higher resolution and higher density in sensors and stacked solid-state image sensors, the distance between pixels becomes shorter and the above-mentioned crosstalk increases. There is a problem with putting it away.

[0005]

OBJECTS OF THE INVENTION The present invention has been made based on the above-mentioned circumstances, and it is an object of the present invention to provide a high-performance photoelectric conversion device that can sufficiently exhibit an element isolation function.

[0006]

[Means for solving the problem] Therefore, in the present invention,
In a photoelectric conversion device having a structure in which a non-single crystal intrinsic semiconductor layer is stacked on a plurality of element-separated pixel electrodes, the non-single crystal intrinsic semiconductor layer on the pixel electrode is an intrinsic semiconductor layer containing a microcrystalline structure; It has a structure in which amorphous intrinsic semiconductor layers are stacked in this order, and the non-single-crystalline intrinsic semiconductor layer on a region other than the pixel electrode is an amorphous intrinsic semiconductor layer.

[0007]

[Operation] Therefore, in the present invention, the I layer on the pixel electrode has a laminated structure of an amorphous light absorption layer and a microcrystalline carrier transport layer, and the I layer on the area other than the pixel electrode is an amorphous layer. Because of the microcrystalline structure, the amorphous material in the region other than the pixel electrode, that is, the pixel isolation region, forms a potential barrier against carriers traveling in the microcrystalline material, improving device isolation characteristics. Therefore, it is desirable that the thickness of the amorphous I layer on the pixel electrode is sufficient to absorb incident light due to its function.

[0008] Note that the above-mentioned “
"Microcrystalline" is defined as a structure in which microcrystals having a grain size of several tens of angstroms to several hundreds of angstroms are mixed in an amorphous state. Note that the grain size of the crystal grains can be determined by X-ray diffraction, Raman spectroscopy, or the like.

In the present invention, the pixel electrode material, materials other than the pixel electrode, film forming method, and film forming conditions are selected so that only a part of the I layer on the pixel electrode is selectively crystallized. By doing so, a desired structure can be realized. For example, S
Ordinary high frequency plasma C using iH4, H2 gas
When creating type I silicon using the VD method, it is known that, for example, by increasing the flow rate of H2, it is possible to change the structure from amorphous silicon to silicon containing a microcrystalline structure. However, for example, silicon containing a microcrystalline structure grows on metal, polycrystalline silicon, or microcrystalline silicon under conditions similar to those just before a silicon film formed on a glass substrate is crystallized. We have found that fabrication conditions exist such that amorphous silicon can be grown on glass substrates and silicon dioxide. As a result, the present invention can be achieved by appropriately selecting such production conditions. In this case, a gas containing, for example, fluorine or chlorine may be introduced during film formation, and in particular, when a gas containing fluorine is used to form a film, selectivity becomes a sufficient creation condition, expanding the design range, This is convenient for realizing the configuration of the present invention. This includes:
For example, HR-CVD using SiF4, H2 gas
Hydrogen Radical enhance
ed Chemical Vapor Deposit
ion), SiH4, and chemical deposition methods using F2 gas.

Suitable base materials for the non-single crystal semiconductor layer used in the present invention include Si, SiGe, SiC, and Cd.
Examples include S, Se, etc., but in particular, Si, SiGe,
SiC is preferred. In the present invention, a highly doped layer, that is, a doping layer, may be used on the amorphous I layer, and the doping layer in this case may be either N type or P type, for example, P type In case of N type, pixel electrode/I layer/P layer are laminated in this order, and in case of N type, pixel electrode/I layer/N layer
The layers will be deposited in sequence. In such a case, the Schottky junction between the pixel electrode and the I layer should be selected from an electrode material and a semiconductor material that form a potential barrier against the majority carriers in the doped layer. Alternatively, a Schottky junction may be formed using metal without using a toping layer. The present invention includes Al, Cr, Ni, W, and T as pixel electrodes.
Metals such as i, Mo, In, Pt, and Au, and alloys containing them, ITO, ZnOX, IrOX, Sn
Metal oxides such as OX can be used, and materials other than the pixel electrode include glass, SiO2, Si
Inorganic materials such as NX and SiON, and organic materials such as polyimide can be used.

Furthermore, since the present invention is characterized in that only a portion of the pixel electrode is selectively crystallized, the element on the pixel electrode is made of, for example, Pt/I type microcrystalline S.
The structure is i/I type amorphous Si/N type microcrystalline Si,
The structure may be Cr/I-type microcrystalline Si/I-type amorphous Si/ITO.

0012

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the photoelectric conversion device of the present invention. Here, after forming a 1000 Å film of Cr on the glass substrate 101 by sputtering, the pixel electrode 102 is formed using a normal photolithography method. Next, by high-frequency plasma CVD method, I-type microcrystalline silicon 103 and I-type amorphous silicon 103' were selectively crystallized at 3000 Å, and I-type amorphous silicon 104 was grown at 800 Å.
P-type microcrystalline silicon 105 is successively formed to a thickness of 300 Å, and finally, ITO is formed to a thickness of 1000 Å as a transparent electrode 106. Table 1 shows the conditions for creating the I layer and P layer at this time.

[0014]

[Table 1] In the photoelectric conversion device of this embodiment, the amorphous silicon on the pixel isolation region 103' acts as a barrier to carriers traveling through the microcrystalline silicon 103 on the pixel electrode, and the carriers that are adjacent to each other by diffusion as in the conventional method Since leakage of carriers to pixels can be suppressed, element isolation characteristics are improved and characteristics sufficient for practical use can be obtained.

[0015] Next, a mode in which the photoelectric conversion device shown in the above embodiment is laminated on the scanning circuit and readout circuit proposed by the present inventors in Japanese Unexamined Patent Publication No. 63-278269 will be specifically explained. .

In FIG. 2(a), an n- layer 202 which becomes a collector region is formed by epitaxial growth on an n-type silicon substrate 201, and a p-base region 2 is formed in the n- layer 202, which becomes a collector region.
03, and an n+ emitter region 204 is further formed to constitute a bipolar transistor.

The p base region 203 is separated from adjacent pixels, and a gate electrode 206 is formed between the horizontally adjacent p base regions with an oxide film 205 in between. Therefore, a p-channel MOS transistor is configured with adjacent p base regions 203 as source and drain regions, respectively. Gate electrode 206 also functions as a capacitor for controlling the potential of p base region 203.

Furthermore, after forming the insulating layer 207, an emitter electrode 208 and a base electrode 208' are formed.

Thereafter, SiO2 is formed as an insulating layer 209, and then Cr is formed as an electrode 211, and each pixel is separated. Here, the electrode 211 is electrically connected to the electrode 208'.

Next, by high frequency plasma CVD method, I-type microcrystalline silicon 213 and I-type amorphous silicon 213 are
' was selected under crystal conditions of 2000 Å, I-type amorphous silicon 214 at 10000 Å, P-type microcrystalline silicon 215 at 5
A transparent electrode 216 with a thickness of 1000 Å is formed to apply a bias voltage to the sensor.

Further, a collector electrode 217 is ohmically connected to the back surface of the substrate 201.

Therefore, the equivalent circuit of one pixel is shown in FIG.
As shown in b), a p-channel MOS transistor 732, a capacitor 733, and a photoelectric conversion device 734 similar to Embodiment 1 are connected to the base of a bipolar transistor 731 made of crystalline silicon, and a terminal for applying a potential to the base is connected. 735, a terminal 736 for driving the p-channel MOS transistor 732 and the capacitor 733, a sensor electrode 737, and an emitter electrode 738.
, collector electrode 739.

FIG. 2(c) is a circuit configuration diagram in which the pixel cells 740 shown in FIGS. 2(a) and 2(b) are arranged in a 3×3 two-dimensional matrix.

In the figure, a collector electrode 741 of one pixel cell 740 is provided for each pixel, and a sensor electrode 742 is also provided for each pixel. Also, PM
The gate electrodes and capacitor electrodes of the OS transistors are connected to drive wiring lines 743, 743', 743'' for each row, and vertical shift transistors (V.S.R.) 744
is connected to. Further, the emitter electrodes are connected to vertical wirings 746, 746', and 746'' for signal readout for each column. Vertical wiring 746, 746', 746
'' are connected to switches 747, 747', 747'' and read switches 750, 750', 750'' for resetting the charges of the vertical wiring, respectively. The gate electrodes of the reset switches 747, 747', and 747'' are commonly connected to a terminal 748 for applying a vertical line reset pulse, and the source electrodes are commonly connected to a terminal 749 for applying a vertical line reset voltage. ing. Readout switch 750, 750', 75
0'' gate electrodes are wires 751 and 751', respectively.
, 751'' through the horizontal shift register (H.S.R.
) 752, and its drain electrode is connected to an output amplifier 757 via a horizontal readout wiring 753. The horizontal readout line 753 is connected to a switch 754 for resetting the charge of the horizontal readout line.

The reset switch 754 is connected to a terminal 755 for applying a horizontal line reset pulse and a terminal 756 for applying a horizontal line reset voltage.

Finally, the output of amplifier 757 is taken out from terminal 758.

The operation will be briefly explained below using FIGS. 2(a) to 2(c).

The incident light is absorbed by the light absorption layer 214 in FIG. 2(a), and the generated carriers are transported by the transport region 213 and accumulated in the base region 203. Figure 2 (
c) When the drive pulse output from the vertical shift register appears on the drive wiring 743, the base potential rises via the capacitor, and signal charges corresponding to the amount of light are transferred from the pixels in the first row to the vertical wirings 746, 746', 746', 746'' respectively.

Next, when the horizontal shift register 752 outputs the scanning pulse to the switches 751, 751', 751'' in sequence, the switches 750, 750', 750'' are turned ON and OFF in order, and the signal is sent to the amplifier 757. It is taken out to an output terminal 758 through. At this time, the reset switch 754 is turned on while the switches 750, 750', and 750'' are turned on in order, and the horizontal wiring 75
3 residual charges are removed. Next, the vertical line reset switches 747, 747', 747'' are turned on, and the residual charges on the vertical lines 746, 746', 746'' are removed. and vertical shift register 74
When a negative direction pulse is applied from 4 to the drive wiring 743, the PMOS transistor of each pixel in the first row is turned on, the base residual charge of each pixel is removed, and the pixel is initialized.

Next, a drive pulse output from the vertical shift register 744 appears on the drive wiring 743', and the signal charges of the pixels in the second row are similarly taken out.

Next, the signal charges of the pixels in the third row are taken out in the same manner.

The apparatus operates by repeating the above operations.

In the embodiments described above, examples of the circuit according to the invention of the present inventors have been shown, but the present device may be applied to the circuit of a generally known photoelectric conversion device.

[0034]

Effects of the Invention The present invention, as explained above, has an element isolation function based on the potential barrier formed by the difference in band gap between the amorphous I layer and the microcrystalline layer on the pixel electrode, and is therefore superior to the prior art. In comparison, the crosstalk between pixels is reduced,
It becomes possible to manufacture a high-performance photoelectric conversion device with higher resolution and higher density.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional structural diagram showing an embodiment of a photoelectric conversion device of the present invention.

[Fig. 2] (a) is a schematic cross-sectional view of the vicinity of the light receiving part of another embodiment of the photoelectric conversion device of the present invention, (b) is an equivalent circuit of one pixel, and (c) is a diagram of the entire photoelectric conversion device of the present invention. It is an equivalent circuit and a block diagram.

FIG. 3 is a schematic cross-sectional view showing a conventional example.

[Explanation of symbols]

101 Glass substrate 102 Cr electrode 103 I-type microcrystalline silicon layer 103' I-type amorphous silicon 104 I-type amorphous silicon 105 P-type microcrystalline silicon 106 ITO electrode 201 N-type silicon substrate 202 N- layer 203 P base base region 204 n+ emitter region 205 oxide film 206 gate electrode 207 insulating layer 208 emitter electrode 208' base electrode 209 insulating layer 211 pixel electrode 213 I type microcrystalline silicon 213' I type amorphous silicon 214 I type Amorphous silicon 215 P-type microcrystalline silicon 216 Transparent electrode 217 Collector electrode 731 Bipolar transistor 732
P-channel MOS transistor 733 Capacitor 734 Photoelectric conversion device 735, 736 Terminal 737 Sensor electrode 738 Emitter electrode 739 Collector electrode 740 One pixel cell 741 Collector electrode 742 Sensor electrode 743, 743', 743'' Drive wiring 744
Vertical shift register (VSR) 746, 746'
, 746″ Vertical wiring 747, 747′, 747
″ Reset switch 750, 750′, 750
″ Readout switch 751, 751′, 751″
Wiring 752 Horizontal shift register (HS
R) 753 Horizontal readout wiring 754 Reset switch 755 Terminal 756 Terminal 757 Amplifier 758 Terminal 301 Base 302 Pixel electrode 303 I-type amorphous silicon 304 P-type amorphous silicon 305 Transparent electrode

Claims (3)

[Claims] 1. In a photoelectric conversion device having a structure in which a non-single crystal intrinsic semiconductor layer is stacked on a plurality of element-separated pixel electrodes, the non-single crystal intrinsic semiconductor layer on the pixel electrode has a microcrystalline structure. The structure is characterized in that an intrinsic semiconductor layer including an intrinsic semiconductor layer and an amorphous intrinsic semiconductor layer are stacked in this order, and the non-single crystal intrinsic semiconductor layer on a region other than the pixel electrode is an amorphous intrinsic semiconductor layer. Photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein the non-single crystal semiconductor layer contains at least silicon. 3. The non-single crystal semiconductor layer comprises a charge storage portion,
2. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is laminated on a substrate on which at least one of a drive circuit, a scanning circuit, and a readout circuit is formed.