JPH02210877A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPH02210877A JPH02210877A JP1031606A JP3160689A JPH02210877A JP H02210877 A JPH02210877 A JP H02210877A JP 1031606 A JP1031606 A JP 1031606A JP 3160689 A JP3160689 A JP 3160689A JP H02210877 A JPH02210877 A JP H02210877A
- Authority
- JP
- Japan
- Prior art keywords
- phototransistor
- film transistor
- thin film
- solid
- difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000003384 imaging method Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 abstract 1
- 239000007787 solid Substances 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 13
- 238000003199 nucleic acid amplification method Methods 0.000 description 13
- 239000010408 film Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 108091008695 photoreceptors Proteins 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Facsimile Heads (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は光電変換素子に増幅作用を持たせた固体撮像装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device in which a photoelectric conversion element has an amplification effect.
[従来の技術]
従来より光信号を画素ごとに増幅し出力信号を取り出す
形式の固体撮像装置としてアイデアがある。素子デバイ
ス固有の物理特性により感度やSN比の向上は段々望め
なくなってきた今ますますその実用化が望まれ、高画質
、高感度、高SN比で高速読み出しが可能な固体撮像装
置に対する要求が高い、そのため具体的にはテレビジョ
ン学会誌 Vol、41 No、11 (19B?)な
どに示されティる形式が研究されている。[Prior Art] Conventionally, there has been an idea for a solid-state imaging device in which an optical signal is amplified pixel by pixel and an output signal is extracted. Now that improvements in sensitivity and signal-to-noise ratio are becoming increasingly difficult to hope for due to the inherent physical characteristics of element devices, their practical application is increasingly desired, and there is a growing demand for solid-state imaging devices capable of high-speed readout with high image quality, high sensitivity, and high signal-to-noise ratio. Therefore, specifically, the format shown in the Journal of the Television Society Vol. 41 No. 11 (19B?) is being studied.
また大面積高性能デバイス用などにSOI技術の開発が
盛んに行われている。Also, SOI technology is being actively developed for large-area, high-performance devices.
[発明が解決しようとする課題]
しかし従来の増幅作用を持つ固体撮像装置では増幅素子
と光電変換素子の特性の均一性を保つことが難しいため
、増幅素子のゲインのばらつきが大きく、さらにはノイ
ズ量のばらつきも大きいため増幅器を外部に持つものと
同レベルの特性のものしか存在しないという課題があっ
た。これは従来の装置では光電変換素子のばらつきに加
えて、独立に増幅素子のばらつきが加わることによる。[Problems to be solved by the invention] However, in conventional solid-state imaging devices that have an amplification function, it is difficult to maintain uniformity in the characteristics of the amplification element and photoelectric conversion element, resulting in large variations in the gain of the amplification element and further noise. There was a problem that only those with characteristics on the same level as those with an external amplifier existed because the variation in the amount was large. This is because in conventional devices, in addition to variations in photoelectric conversion elements, variations in amplification elements are added independently.
また、一方で装置の小型化に伴い、大面積タイプの受光
索子アレイの必要性も高く、画像デバイスとして透明基
板上に装置を形成できるメリットは光の基板側入射力な
どでそのメリットは計り知れない、したがって−素子チ
ップの大きさをシリコンウェハーの寸法により制限され
た素子アレイでは、密着型固体撮像装置として大面積に
用いるには適していなかった。センサ部と走査回路部を
一体化した大面積センサにおいては、シリコンウェハー
上に素子形成したものを多数(10個など)並べること
も考えられるが、実装効率は非常に悪く、感度などのチ
ップ間ばらつきが大きくなるために一チツプでもばらつ
きが大きいのに、複数チップでは増幅作用を内蔵する意
味がなくなる。しかし、チップを大面積にすると上記の
性能劣化要因の影響はさらに大きくなることが考えられ
る。On the other hand, with the miniaturization of devices, there is a strong need for large-area photoreceptor arrays, and the advantage of being able to form a device on a transparent substrate as an imaging device is that the light is incident on the substrate side. Therefore, an element array in which the size of the element chip is limited by the size of the silicon wafer is not suitable for use in a large area as a contact type solid-state imaging device. In a large-area sensor that integrates the sensor part and the scanning circuit part, it is possible to arrange a large number (such as 10) of elements formed on a silicon wafer, but the mounting efficiency is very poor, and the inter-chip problems such as sensitivity etc. Since the variation becomes large, there is no point in incorporating an amplification function in multiple chips even though the variation is large even in a single chip. However, if the area of the chip is increased, the effects of the above-mentioned performance deterioration factors may become even greater.
そこで本発明では、高増幅ゲインであってゲインのばら
つきが小さく、さらにはノイズ量のばらつきも押さえ込
み、さらには高速読み出しを可能にした大1面積固体撮
像装置を提供することを目的とするものである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a large single-area solid-state imaging device that has a high amplification gain, has small variations in gain, suppresses variations in noise amount, and enables high-speed readout. be.
本発明の固体撮像装置は、少なくとも一部は非単結晶に
より構成されるフォトトランジスターを光電変換素子と
し、その駆動回路に薄膜トランジスターを用いて同一基
板上に設けたことを特徴とする。さらには、光電変換素
子の一部と薄膜トランジスターの一部を同一の非単結晶
材料で形成したことを特徴とする。The solid-state imaging device of the present invention is characterized in that a phototransistor, at least a part of which is made of a non-single crystal, is used as a photoelectric conversion element, and a thin film transistor is used for a drive circuit thereof, and the phototransistor is provided on the same substrate. Furthermore, a part of the photoelectric conversion element and a part of the thin film transistor are formed of the same non-single crystal material.
以下、実施例により本発明の詳細を示す。Hereinafter, the details of the present invention will be shown by examples.
[実施例]
実施例1
第1図は本発明による固体撮像装置の構成の一例であり
、第2図はその固体撮像装置の拡大断面図例である。1
01.206は本例では多結晶シリコンを用いて作成し
たn型薄膜トランジスタで成り立っており、102.2
04の非単結晶フォトトランジスタにつながるスイッチ
として働いている。多結晶シリコンはLPCVDにより
約60O″Cにて堆積させた後、約1100°Cの熱酸
化によりゲート膜を形成、ゲート電極を多結晶シリコン
にて形成後、イオン打ち込みにより自己整合法でソース
とドレイン部を形成した。特性を重視するようであれば
シリコン膜堆積後に、熱や光などにより結晶成長させた
もの(いわゆるSOI構造等)を使うのもよい0本例で
は201の基板に石英板を用いたので、ゲート酸化他で
熱を加える問題は少なく、基板が透明であるので基板側
からの光入射も可能となり、実装構造で高信頼性などが
確保できる。薄膜トランジスタとして動作すればその他
の方法を用いても何ら問題はなく、もちろん基板材料の
選択幅が拡がる(石英より安価な基板が使える)ので低
温(例えば約650℃以下など)ですべてが処理できる
のも好ましい、薄膜トランジスタのソースラインは10
3のバイアス電源につながっており、その配線材料は何
を用いてもよいが本例ではシリコン、銅を微量混入した
アルミニュウムを用いている。薄膜トランジスタ(10
1)のゲートライン(105)は多結晶シリコンを用い
て形成されておりスイッチの制御信号線として入力デー
タに応じてON、OFFする。[Examples] Example 1 FIG. 1 is an example of the configuration of a solid-state imaging device according to the present invention, and FIG. 2 is an example of an enlarged cross-sectional view of the solid-state imaging device. 1
In this example, 01.206 consists of an n-type thin film transistor made using polycrystalline silicon, and 102.2
It works as a switch connected to the non-single crystal phototransistor 04. Polycrystalline silicon is deposited by LPCVD at approximately 60°C, then a gate film is formed by thermal oxidation at approximately 1100°C, a gate electrode is formed of polycrystalline silicon, and a source is formed by ion implantation using a self-alignment method. A drain part is formed.If characteristics are important, it is also a good idea to use a crystal grown by heat or light after depositing a silicon film (so-called SOI structure).In this example, a quartz plate is used for the substrate 201. Since it uses a thin film transistor, there are fewer problems with applying heat during gate oxidation, etc., and since the substrate is transparent, light can enter from the substrate side, and the mounting structure can ensure high reliability.If it operates as a thin film transistor, other There is no problem when using this method, and of course, the range of substrate material selection is expanded (substrates cheaper than quartz can be used), and it is also preferable that everything can be processed at low temperatures (for example, about 650 degrees Celsius or less). Source lines of thin film transistors. is 10
It is connected to the bias power source No. 3, and any wiring material may be used for the wiring, but in this example, aluminum mixed with a small amount of silicon and copper is used. Thin film transistor (10
The gate line (105) of 1) is formed using polycrystalline silicon, and is turned on and off according to input data as a control signal line for a switch.
−次元や二次元などの固体撮像装置として用いる場合、
データの転送や作成機能を有する回路に接続され、第1
.2図には記されていないが101と同様の多結晶シリ
コンで形成されたp、 n型薄膜トランジスタによる
CMO8型O8トレジスタを用いて信号を転送している
。この方法を用いればほぼ同一の工程で光電変換素子の
一部もしくは全部を除くスイッチと走査同局を形成でき
るため、条件さえ許せばコストなどのメリットは非常に
大きい、第4図に本例で用いたスタティック動作マスタ
ースレイブ型シフトレジスタの回路図例を示す、スター
ト部のみを示したが404のセルの繰り返しで読み取り
解像度や読み取り範囲に応じて必要段数のフォトトラン
ジスタ密度や数を得ることができ、401のスタートパ
ルスにより信号が順次送られ薄膜トランジスタのスイッ
チを順番に開いていくことで、フォトトランジスタの選
択回路となる。また絶縁基板上に形成されているために
、素子分離の必要なく、浮遊容量も小さく走査スピード
の点では非常に有利である。- When used as a solid-state imaging device such as dimensional or two-dimensional,
Connected to a circuit that has data transfer and creation functions,
.. Although not shown in Figure 2, signals are transferred using a CMO8-type O8 register made of p- and n-type thin film transistors made of polycrystalline silicon similar to 101. If this method is used, it is possible to form a switch and a scanning station excluding part or all of the photoelectric conversion element in almost the same process, so if the conditions permit, the cost and other advantages are very large. This figure shows an example of a circuit diagram of a static operation master-slave type shift register. Only the starting part is shown, but by repeating 404 cells, it is possible to obtain the required number of stages of phototransistor density and number depending on the reading resolution and reading range. A signal is sequentially sent by the start pulse 401 to sequentially open the switches of the thin film transistors, thereby forming a phototransistor selection circuit. Furthermore, since it is formed on an insulating substrate, there is no need for element isolation, and stray capacitance is small, which is very advantageous in terms of scanning speed.
101の薄膜トランジスタのドレイン線は非単結晶(少
なくとも一部に非単結晶を含むものもこう呼ぶことにす
る)フォトランジスタ(102)のエミッタにつながっ
ており薄膜トランジスタ(101)を通してバイアス電
圧が加わる0本例ではフォトトランジスタはS i H
aやそれにH4やPH3やB2Hgなどを加えたガスの
グロー放電分解非晶質シリコンを用いて作成したn1p
in型トランジスタを用いている0本例では各層厚はコ
レクタ側から500A、8000A、250A。The drain line of the thin film transistor 101 is connected to the emitter of a non-single-crystal (hereinafter referred to as a non-single-crystal) phototransistor (102), and a bias voltage is applied through the thin-film transistor (101). In the example, the phototransistor is S i H
n1p made using amorphous silicon decomposed by glow discharge of a gas containing H4, PH3, B2Hg, etc.
In this example using an in-type transistor, the thickness of each layer is 500A, 8000A, and 250A from the collector side.
1500人、500人とした、ドーピング量など複合的
に考える必要があるが、本例ではコレクタ側は最適値近
辺かと考える。不純物の添加は、PH3やB2 Heな
どによっている。利用光に対する窓効果、ブロッキング
特性、高増幅率特性、高速性能や耐熱性、信頼性向上な
どを目的として各層に炭素などを混入しワイドギャプ化
して炭化シリコンなどとし作るのもよい、このばあいは
SiH4にCHaなどを加え分解して膜形成する6本例
ではn層を炭化シリコンとし、バンドギャブを2eV近
辺とした0作成条件は装置依存性が高いが平行平板型(
30cm丸)の容量結合型プラズマ装置で1.10Wか
ら80Wのパワーを投入し非晶質シリコンや非晶質炭化
シリコンを堆積した。Although it is necessary to consider the doping amount of 1,500 people and 500 people, in this example, the collector side is considered to be close to the optimum value. Impurities are added using PH3, B2 He, or the like. For the purpose of window effect, blocking characteristics, high amplification characteristics, high-speed performance, heat resistance, reliability improvement, etc. on the light used, it is also possible to mix carbon into each layer to create a wide gap and make it as silicon carbide. In this example, the n-layer is made of silicon carbide and the band gap is around 2 eV to form a film. Although it is highly dependent on the device, the parallel plate type (
Amorphous silicon and amorphous silicon carbide were deposited by inputting a power of 1.10 W to 80 W using a capacitively coupled plasma device (30 cm round).
また本例ではn1pinの各層を単に積層し、同一面積
のパターンを形成し両端のコレクタとエミッタから電極
を取り出した構造であるが、垂直方向で各層の面積をこ
とならしたり、水平方向に接合の取り出しや電極の一部
若しくは全部を形成してもよ(pinip% npin
% n1pn、npnS pnip、pinpやpnp
としたり、またはi層の一部若しくは全部に不純物を微
量混入させたり、コンタクト用に高ドープ層を用いたり
、各層で不純物濃度やバンドギャブの傾斜やステップを
付けて接合形成や電極とのコンタクト、バイアスのかか
り方、光の利用効率などを最適化してもよい、エミッタ
にのみ非晶質、微結晶や多結晶をそれぞれ用いる構造で
、幾つかの最適化ができ本発明構成でコレクタやベース
側を初め非単結晶とし、層間絶縁膜上に3.5μm厚に
形成、その後に熱アニールにより結晶性の改善を行う、
これは一般に用いられているSOIO術を用いて、本例
では515℃で形成したCVDシリコンを615℃で2
8時間アニールして、1.2μmから2.3μmの結晶
粒径を得た0本発明の構成では層間絶縁膜下に既に走査
回路部及びスイッチ部が非単結晶シリコンにて形成され
ており、上記アニール時には薄膜トランジスタ部も同時
に結晶性が改善される。従って一回のアニール(−昼夜
以上かかるばあいもある)で受光部と走査回路部及びス
イッチ部の両方の特性が大きく改善されることになる。In addition, in this example, each layer of n1pin is simply stacked to form a pattern with the same area, and the electrodes are taken out from the collector and emitter at both ends. It is also possible to take out the electrode and form part or all of the electrode (pinip% npin
% n1pn, npnS pnip, pinp or pnp
Alternatively, a small amount of impurity may be mixed into part or all of the i-layer, a highly doped layer may be used for contact, and each layer may have a gradient or step of impurity concentration or band gab to form a junction or contact with an electrode. Bias application, light utilization efficiency, etc. can be optimized, and the structure uses amorphous, microcrystalline, or polycrystalline only for the emitter, and several optimizations can be made with the configuration of the present invention. is first made into a non-single crystal, formed to a thickness of 3.5 μm on an interlayer insulating film, and then thermally annealed to improve crystallinity.
In this example, CVD silicon formed at 515°C is heated to 20°C at 615°C using the commonly used SOIO technique.
After annealing for 8 hours, a crystal grain size of 1.2 μm to 2.3 μm was obtained. In the structure of the present invention, a scanning circuit section and a switch section are already formed of non-single crystal silicon under the interlayer insulating film. During the above annealing, the crystallinity of the thin film transistor portion is also improved at the same time. Therefore, the characteristics of both the light receiving section, the scanning circuit section, and the switch section can be greatly improved by one annealing (which may take more than one day and night).
薄膜トランジスタに関しては、チャンネル部の結晶性が
上がり、移動度が5倍位以上となった。受光部のエミッ
タ部で膜厚を厚くしたものの層幅率や速度に及ぼす効果
は絶大であった。全体ばらつきは増えるが、高増幅率な
どよりこのエミッタ部などを用いてシリコンウェハー上
に受光部を形成することによる効果も、走査部の最適化
から考えられる。全体工程中では薄膜トランジスタ作成
後、酸化シリコン膜、ビデオライン(203)を形成、
ビデオラインはフォトトランジスタの電極を兼ねており
、透明電極(例えば’I T O膜など)材料で形成し
た。Regarding thin film transistors, the crystallinity of the channel portion has increased, and the mobility has increased by about 5 times or more. Although the film thickness was increased in the emitter section of the light receiving section, the effect on the layer width ratio and speed was tremendous. Although the overall variation increases, the effect of forming a light receiving section on a silicon wafer using this emitter section due to high amplification factors can also be considered from the optimization of the scanning section. During the entire process, after creating a thin film transistor, a silicon oxide film and a video line (203) are formed.
The video line also serves as the electrode of the phototransistor, and is made of a transparent electrode material (for example, an I TO film).
実施例2
第5図に別の構造を示す、507の非単結晶材料を作製
、その後に熱アニールにより結晶性の改善を行う、これ
は一般に用いられているSO工核技術用いて、本例では
415℃で形成したPECVDシリコンを600 ”C
で28時間アニールして、1.8μmから3.3μmの
結晶粒径を得た。ざらにC,VDや熱酸化などで酸化膜
を形成後、必要箇所にゲート電極を形成する0層間絶縁
膜を形成し、コンタクトホール開け、504のフォトト
ランジスターのエミッタ部を形成、506の薄膜トラン
ジスタのソースやドレイン電極を形成するために505
の裏電極と503のビデオラインを形成する。Example 2 A non-single-crystal material of 507, another structure of which is shown in FIG. Here, PECVD silicon formed at 415°C is heated to 600"C.
After annealing for 28 hours, a grain size of 1.8 μm to 3.3 μm was obtained. After roughly forming an oxide film using C, VD or thermal oxidation, an interlayer insulating film for forming a gate electrode is formed in the necessary locations, a contact hole is opened, the emitter part of the phototransistor 504 is formed, and the emitter part of the phototransistor 506 is formed. 505 to form source and drain electrodes
A back electrode 503 and a video line 503 are formed.
フォトトランジスタの材料は非晶質、微結晶や多結晶、
さらにはそれらを結晶成長させたものを用いたり、前述
のようにバンドギャプを利用するためにそれらを複合さ
せてもよい、シリコンを利用して増幅作用を持つ構造で
、受光部の少なくとも一部が薄膜形成されていればよい
、ここでフォトトランジスタはフローティングベース型
で用いられているがさらにスピードや安定性を求める場
合は増幅率は下がるがフローティングとせず第3図の様
につながれたRの抵抗をベースとエミッタ間に入れて用
いることもできる0本例では一次元の光電変換素子アレ
イを用いたラインセンサを構成したが、水平、垂直の二
系統とし二次元に光電変換素子を配列したエリアセンサ
として用いることも十分可能である。102の非単結晶
フォトトランジスタのコレクタは各光電変換素子に共通
な104のビデオラインにつながれている。Phototransistor materials can be amorphous, microcrystalline, polycrystalline,
Furthermore, it is possible to use a crystal grown version of these, or to combine them to utilize the band gap as mentioned above.It is a structure that uses silicon to have an amplification effect, and at least a part of the light receiving part It is sufficient to form a thin film. Here, the phototransistor is used as a floating base type, but if further speed and stability are required, the amplification factor will be lower, but instead of floating, connect the R resistor as shown in Figure 3. In this example, a line sensor using a one-dimensional photoelectric conversion element array was constructed, but an area where photoelectric conversion elements are arranged two-dimensionally with two systems horizontally and vertically It is also fully possible to use it as a sensor. The collectors of 102 non-single crystal phototransistors are connected to 104 video lines common to each photoelectric conversion element.
実施例1.2とも任意の工程位置で水素などによる終端
工程を付加することで、さらなる高性能化が計れる。In both Examples 1 and 2, further improvement in performance can be achieved by adding a termination process using hydrogen or the like at any process position.
102のフォトトランジスタは101の薄膜トランジス
タと合わせて、−ライン読み取り間に電荷を蓄積するこ
とで取り扱いやすい電荷量とする蓄積モードを用いてい
る。動作は薄膜トランジスタがONするとともに逆バイ
アスされた非単結晶フォトトランジスタのコレクタ、ベ
ース間容tcにバイアス電源Vにより電荷が充電される
。容量Cは本例の第2図のように非単結晶材料による構
造の場合、接合容量とともに薄膜容量で形成される。そ
の後に薄膜トランジスタは次の読みだしまでOFFされ
、光の入射量に比例して光電原核により充電された電荷
は失われていく、シたがって、次に読みだされるタイミ
ングで失った電荷量が再充電され、ベース電流となりト
ランジスタの増刷作用で約電流利得hre>1倍されて
ビデオラインから出力されるので、外部にて積分動作を
行い光の入射量に比例して高い感度で出力が得られる。The phototransistor 102, together with the thin film transistor 101, uses an accumulation mode in which charge is accumulated between -line readings to make the amount of charge easy to handle. In operation, when the thin film transistor is turned on, the collector-base capacitance tc of the reverse biased non-single-crystal phototransistor is charged by the bias power supply V. In the case of a structure made of a non-single crystal material as shown in FIG. 2 of this example, the capacitor C is formed by a thin film capacitor together with a junction capacitor. After that, the thin film transistor is turned off until the next readout, and the charge charged by the photonucleus is lost in proportion to the amount of incident light. Therefore, the amount of charge lost at the timing of the next readout is It is recharged and becomes the base current, which is multiplied by the current gain hre > 1 due to the transistor multiplication effect and output from the video line, so an external integration operation is performed and the output is obtained with high sensitivity in proportion to the amount of incident light. It will be done.
以上実施例を述べたが、本発明は以上の実施例のみなら
ず、撮像装置一般に当てはまり、また広く光を扱う装置
、光を処理する装置に応用が可能である。Although the embodiments have been described above, the present invention is applicable not only to the above embodiments but also to imaging devices in general, and can be applied to a wide range of devices that handle light and devices that process light.
[発明の効果]
以上述べたように本発明によれば、これらの素子では同
一装置を用い、同種材料で受光部と増幅部が形成されて
いるため、大面積に形成しても増幅素子と光電変換素子
の特性の均一性を保つことが容易であり、増幅素子のゲ
インのばらつきが小さい、また、薄膜トランジスタは優
れたスイッチング特性を持ち、結晶化などでバルクシリ
コンより優れ、光電変換素子に非常に近接して走査部を
形成できるためにノイズ量のばらつきも小さい。[Effects of the Invention] As described above, according to the present invention, these elements use the same device and the light receiving part and the amplifying part are formed of the same kind of material, so even if formed over a large area, they can be used as an amplifying element. It is easy to maintain the uniformity of the characteristics of photoelectric conversion elements, and the variation in gain of amplification elements is small.Also, thin film transistors have excellent switching characteristics and are superior to bulk silicon in terms of crystallization, making them extremely suitable for photoelectric conversion elements. Since the scanning section can be formed in close proximity to the scanning section, variations in the amount of noise are also small.
さらには、非単結晶材のSOI技術などを用い、フォト
トランジスターと薄膜トランジスターの性能向上を一度
に行えるなどの利点を持つ、そして、素子特性Φ向上ま
た、本構造ではベースとコレクタでの逆バイアス特性が
優れているためリニアリティなど固体撮像素子としての
性能に優れ、優れたベースとエミッタ接合で高増幅率、
高速である。Furthermore, it has the advantage of improving the performance of phototransistors and thin film transistors at the same time by using SOI technology of non-single-crystal materials, improving device characteristics Φ, and eliminating reverse bias between the base and collector. Due to its excellent characteristics, it has excellent performance as a solid-state image sensor such as linearity, and the excellent base and emitter junction allows for high amplification and
It's fast.
という効果を有する。It has this effect.
第1図は、本発明の基本構成例を表す図。
第2図は、素子断面の一例を表す図。
第3図は、本発明の他の一例を表す図。
第4図は、本発明の全体構成例を表す図。
第5図は、本発明の素子断面図の別個を示す図。
101 ・ ・
102 ・ ・
103 ・ ・
104 ・ ・
105 ・ ・
201 ・ ・
202 ・ ・
203 ・ ・
204 ・ ・
205 ・ ・
206 ・ ・
301 ・ ・
・薄膜トランジスタ(n)
・非単結晶フォトトランジスタ
・バイアス電源
・ビデオライン
・ゲートライン
・基板
・絶縁膜
・ビデオライン
・フォトトランジスタ
・裏電極
・薄膜トランジスタ
・薄膜トランジスタ(p)
302・・・非単結晶フォトトランジスタ504・・・
フォトトランジスタ
506・・・薄膜トランジスタ
以
上
出願人 セイコーエプソン株式会社FIG. 1 is a diagram showing an example of the basic configuration of the present invention. FIG. 2 is a diagram showing an example of an element cross section. FIG. 3 is a diagram showing another example of the present invention. FIG. 4 is a diagram showing an example of the overall configuration of the present invention. FIG. 5 is a diagram showing a separate cross-sectional view of the element of the present invention. 101 ・ ・ 102 ・ ・ 103 ・ ・ 104 ・ ・ 105 ・ ・ 201 ・ ・ 202 ・ ・ 203 ・ ・ 204 ・ ・ 205 ・ 206 ・ ・ 301 ・ ・ ・ Thin film transistor (n) ・ Non-single crystal phototransistor bias power supply・Video line ・Gate line ・Substrate ・Insulating film ・Video line ・Phototransistor ・Back electrode ・Thin film transistor ・Thin film transistor (p) 302...Non-single crystal phototransistor 504...
Phototransistor 506...thin film transistor and above Applicant Seiko Epson Corporation
Claims (2)
より構成されるフォトトランジスターを用い、その駆動
回路に薄膜トランジスターを用いて同一基板上に設けた
ことを特徴とする固体撮像装置。(1) A solid-state imaging device characterized in that a phototransistor, at least a part of which is made of a non-single crystal, is used as a photoelectric conversion element, and a thin film transistor is used as a drive circuit for the phototransistor, and the phototransistor is provided on the same substrate.
を同一の非単結晶材料で形成したことを特徴とする請求
項1記載の固体撮像装置。(2) The solid-state imaging device according to claim 1, wherein a part of the photoelectric conversion element and a part of the thin film transistor are formed of the same non-single crystal material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1031606A JPH02210877A (en) | 1989-02-10 | 1989-02-10 | Solid-state image pickup device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1031606A JPH02210877A (en) | 1989-02-10 | 1989-02-10 | Solid-state image pickup device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02210877A true JPH02210877A (en) | 1990-08-22 |
Family
ID=12335860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1031606A Pending JPH02210877A (en) | 1989-02-10 | 1989-02-10 | Solid-state image pickup device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02210877A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0642179A1 (en) * | 1993-03-23 | 1995-03-08 | TDK Corporation | Solid state imaging device and process for production thereof |
USRE39393E1 (en) | 1990-11-30 | 2006-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Device for reading an image having a common semiconductor layer |
JP2008141198A (en) * | 2001-02-28 | 2008-06-19 | Avago Technologies General Ip (Singapore) Private Ltd | Open base phototransistor array with amorphous semiconductor |
-
1989
- 1989-02-10 JP JP1031606A patent/JPH02210877A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE39393E1 (en) | 1990-11-30 | 2006-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Device for reading an image having a common semiconductor layer |
EP0642179A1 (en) * | 1993-03-23 | 1995-03-08 | TDK Corporation | Solid state imaging device and process for production thereof |
EP0642179A4 (en) * | 1993-03-23 | 1995-08-30 | Tdk Corp | SEMICONDUCTOR IMAGING DEVICE AND CORRESPONDING PRODUCTION METHOD. |
JP2008141198A (en) * | 2001-02-28 | 2008-06-19 | Avago Technologies General Ip (Singapore) Private Ltd | Open base phototransistor array with amorphous semiconductor |
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