JPH04212772A - Active pull-up circuit used for semiconductor memory - Google Patents

Abstract

PURPOSE: To provide a method and device for reducing noise interference in a memory of a model particularly using complementary bit lines related to a semiconductor memory. CONSTITUTION: The intersected complementary bit lines and an intersected connection pull-up means are shown. One bit line 26 is intersected with the other bit line 28 of a complementary bit line pair, and thus, a noise impediment is eliminated. A P channel intersected connection pull-up transistor is connected between the bit lines 26, 28 in an intersected point 46, and then, when one bit line is pulled low for reading out a memory cell 30, the matter that the other bit line is pulled by a supply voltage is warranted.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor memory.
More particularly, it relates to methods and apparatus for reducing noise interference in types of memories that use complementary bit lines.

0002

BACKGROUND OF THE INVENTION Efforts continue to develop semiconductor memories that are less sensitive to internally and externally generated noise signals. As the cell size of each generation of memory decreases, the number of digital 1s or 0s stored
The voltage representing this also becomes smaller. Therefore, if a noise signal enters the low-level signal line of the memory, it will adversely affect the reliability of the memory.

In well-known core memories that use toroidal magnetic cores as memory elements, bit line wire pairs carrying input current and output power to the magnetic core assembly are twisted together, while the wires carry small data signals. This reduced electromagnetic interference. In this way, undesired signals are induced in both wires of the bit line with the same strength. If the amplitudes of the signals induced in both wires are the same, then when the state of the magnetic core changes, even with common mode noise, the differential sense amplifier
ier) can easily detect the small analog signals generated.

[0004] For semiconductor memories, which are currently used almost exclusively, problems caused by induced noise signals cannot be easily solved. The problem in semiconductor memories is even more severe when metal or polysilicon conductive lines are separated by only a few microns. If such close signal lines are connected, e.g.
When carrying a volt logic signal, that signal may be capacitively coupled to other signal lines, such as memory bit lines. Semiconductor memory sense amplifiers have become extremely complex in order to be extremely sensitive to memory read signals while being highly rejective to noise signals on the bit lines.

In microprocessor chips that have bidirectional data and address buses connected to other circuits on the chip,
The possibility of noise interference with memory increases. In modern microprocessor designs, it is advantageous to create memory at a subsurface level and data or address lines above the memory. This is advantageous both from the point of view of connecting the data bit lines to the memory inputs and from the point of view of connecting the outputs of the memory to the data lines. Space is also saved. This type of configuration typically has the potential to induce unwanted electrical signals from the data or address lines to the bit lines of the memory.

[0006] This noise interference problem is caused by
This is complicated in memory design using line configurations. This type of memory requires two low level signal bit lines per cell, both for writing data to the cell and for reading data from the cell. High level logic signal transitions on the upper conductor, or on the conductor adjacent to the complementary bit line, are capacitively coupled to the bit line by a disproportionate amount. In this case, the differential sense amplifier cannot distinguish between the induced noise and the legitimate signal read from the memory cell.

As can be seen from the above, memory bits
There is a need for a semiconductor memory structure that reduces susceptibility to line-induced noise signals. In this regard, there is a need for a complementary bit line structure that reduces the effects of bit line induced noise signals.

[0008]

SUMMARY OF THE INVENTION In accordance with the present invention, a complementary bit line memory structure is disclosed that substantially reduces or eliminates the disadvantages associated with corresponding prior art circuits. According to the memory structure of the present invention, metal or polysilicon conducting complementary bit lines are crossed at points where undesirable signals may be induced. In split or partitioned memory designs, it is preferred to have complementary bit lines intersect at a point between memory cell sections for electrical balancing purposes. When crossed, the complementary bits
Since the lines are each exposed to the same noise potential, the differential level of unwanted noise signals on the bit line pair is reduced.

Crossing of complementary bit lines is accomplished by forming the crossing members as first level polysilicon conductive lines. The elongated bit line is made as a second level, or upper metal conductor, isolated from the polysilicon member by silicon dioxide. Contacts are made through the silicon dioxide to connect the polysilicon member to the appropriate ends of the metal bit lines to form a crossed bit line.

Another technical advantage of the present invention comprises cross-connected bit line pull-up means that operate in conjunction with crossed bit lines. 1 bit line is
Drives a P-channel transistor that can drive the other bit line to a logic high level. Similarly, the other bit line is connected to pull up its one bit line through a P-channel transistor. Therefore, a positive voltage feedback is provided for the memory cell read operation so that when one bit line is made slightly low positive by reading the memory cell, the other bit line is automatically pulled up by the pull-up means. give. This positive feedback enhances the effectiveness of differential cell readout. Unwanted negative voltages induced on both bit lines of the crossed complementary pair are also suppressed by being pulled back to a high voltage by the cross-coupled pull-up transistors.

The noise immunity of the memory cell can be further enhanced by the use of N-channel transistors in line with the bit lines in the memory column or word line select section. By using N-channel transistors as column select devices in the bit lines, noise signals whose amplitude is less than the limiting voltage of the N-channel transistors cannot be interpreted as legitimate signals read from the memory.

Other features and advantages will become apparent from the following detailed description of the preferred embodiments of the invention, which are illustrated in the accompanying drawings. In the drawings, the same reference numbers indicate the same elements throughout the figures.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles and concepts of the invention may best be understood by referring first to FIG. 1 of the drawings.
This figure shows an example of an application in which the invention can be implemented advantageously. Microprocessor circuit 10, integrated on a single piece of silicon, has random access memory 12 connected to a data bus 14 that is shared by many other circuits in microprocessor 10. Memory 12 is shown in dashed lines and is formed in an integrated circuit beneath several conductors forming data bus 14. data bus 14
is shown as a typical 32-bit bus in current microprocessor designs.

For purposes of illustration, an arithmetic logic unit (ALU)
) 16 is connected to the memory 12 and other data passing circuits 18. The memory has an input 20 and an output 22 connected to conductor 24 of data bus 14. Data bus 14 may be a conventional bidirectional bus to which many other circuits of microprocessor 10 are connected.

The conductors of data bus 14 carry high speed logic signals that require only a few nanoseconds for rising and falling transitions. Since the electric signal has such sharp rise and fall times, it easily interferes with adjacent circuits such as the memory 12 on the lower side. a conductor of data bus 14;
The problem is complicated when forming the entire structure into a single integrated circuit because parasitic capacitances may exist between adjacent circuits integrated on chip 10.

FIG. 2 shows conductor 24 (D
0) and the portion of memory 12 connected to conductors 20, 22 of this data bus. Specifically illustrated are bit line 26 (BL) and its complementary line 28 (BL).
). It should be understood that memories typically include a larger number of complementary bit lines than shown. bit line 26
, 28 carry the signals written to the memory cells by a write decode circuit 32, one cell being designated by the reference numeral 30. Memory cell 30 is word line 34
can be written by the clock operation. Other cells connected to the bit line are accessed by other similar word lines. bit lines 26, 28
The data present in is stored in the selected cell 30 of the memory. Memory typically consists of 26 bit line pairs
, 28, a number of word lines 34 are provided for accessing one of a number of cells 30 connected to the cells 30, . Write decode circuit 32 decodes the memory address and conveys the data present on conductor 24 of data bus 14 to the selected complementary bit line 26,28. Word line 34 and bit line pair 26,2
8, data can be written to a particular memory cell 30.

Memory cell 30 is again read by activating word line 34, at which time a differential voltage is output to bit lines 26,28. The voltage difference is on the order of 5 volts and is detected by sense amplifier 36. Sense amplifier transistor 36 connects bit line 2
6 and 28, a logic high level is output on the output conductor 22 when a voltage difference on the order of the critical voltage is sensed. That bit
Sense amplifier 36 begins to detect a one or zero when the line voltage difference is a fraction of the total voltage width. Therefore, electrical noise interference must be kept to a minimum in order to provide a reliable readout of the memory. Depending on the microprocessor's shared bus structure, memory
It is also important to understand that data bus 14 typically actively carries a high level data signal while cell 30 is being read. As a result, the signal on data bus 14 is transferred to memory 12 as noise interference.
is capacitively coupled to the bit line of.

FIG. 2 shows parasitic capacitance 38, 40 between data bus conductor 24 and bit lines 26, 28. Parasitic capacitances 42 and 44 are also shown connecting data bus conductor 24 and bit lines 26 and 28. In accordance with an important feature of the invention, complementary paired bit lines 2
6 and 28 intersect so that one section of bit line 26 is adjacent to data bus conductor 24 and one section of bit line 28 is also adjacent to conductor 24. Bit lines 26, 28 intersect at point 46 without physically touching. Because the bit lines are crossed, an undesired signal that enters the upper bit line section 26 due to parasitic capacitance 38 is generally of the same strength as an undesired signal that enters the upper section of bit line 28 due to parasitic capacitance 40. It is.

Similarly, the parasitic capacitances 42 and 44 are
Connecting voltages of substantially the same strength in the lower sections of each of lines 26, 28. bit line 26
, 28 is caused by the parasitic capacitance 38
~44, but it is not easy to control the value. Crossed bit lines 26, 28 induce undesirable signals on both bit lines 26, 28, reducing their differential effects. crossed bits
The lines increase the noise margin of the type of memory that utilizes complementary bit lines and sense amplifiers 36 of the type shown.

FIGS. 3 and 4 show complementary bits and
Other configurations for crossing lines to reduce the effects of unwanted signals induced therein are shown in a simplified manner. Two adjacent bit lines (BL1, BL
2) is shown in Figure 3. Various adjacent bits
It can be seen that as long as parasitic capacitance exists between lines, undesirable voltages can be induced therebetween. In the embodiment of FIG. 3, capacitors 52-58 represent the parasitic capacitance connected between the bit line pair BL1, BL2.

It can be seen that BL1 contains twice the number of intersections as BL2. As a result, the signal on bit line conductor 50 of BL1 is induced on both crossed bit lines 60, 62 of BL2. Similarly, the signal carried by bit line conductor 48 of BL1 is transferred to the crossed bit lines 60, 62 of BL2.
is also induced. The effect of having twice as many bit line crossings in BL1 as compared to BL2 is that the noise connected between bit line pairs BL1, BL2 is proportionately present in the individual pairs 48, 50, 60, 62. The differential voltage applied is reduced to substantially zero. In other words, if a positive voltage is induced on bit line 60 by bit line 48 and a corresponding positive voltage is induced on bit line 62 by bit line 48, bit lines 60, 62 The differential voltage induced between them is zero. This crossed bit line configuration produces similar results on bit lines 60 and 62 with respect to the voltage induced by bit line 50. Similarly, bit lines 60 and 62 cause bit line 4 to
The voltage induced at 8 and 50 becomes a net zero induced voltage. Therefore, for common mode noise voltages present on both bit lines of a pair, such signals will be transparent to many bit line sensing circuits.

The crossing pattern of bit lines BL1, BL2 is symmetrical, with crossing points or points 64, 66
are adjacent to the sides. This means that the bit line
It may be advantageous in integrated circuit manufacturing where it is desired to connect circuitry such as bias or pull-up circuits to both pairs of bit lines. The bias or pull-up common circuit forms polysilicon or other conductive material overlying the crossing points 64, 66 and connects the circuit to the crossed bit lines 48, 50, 60, 62 that lie directly below it. It can be manufactured by In the embodiment of FIG. 3, the pattern designated BL1 is repeated alternately for odd numbered bit lines. Similarly, the crossing pattern shown as BL2 is repeated for even numbered bit lines.

The crossing pattern shown in FIG. 4 can be utilized in complementary bit line memories that do not require crossing symmetry. For example, bits of complementary pair BL4
The linear section of line 68 is the intersection 70 of BL5
It is designed to be adjacent to. As a result, the signal voltage present on bit line 68 is induced on both bit lines 72, 74 of complementary pair BL5. Similarly, a voltage on the other bit line 76 of complementary pair BL4 can be induced in the section of both bit lines 72, 74 of BL5 that intersect near intersection point 72. As mentioned above, although there is no common or symmetrical crossing point between the bit line pairs in the configuration shown in FIG. 4, the differential voltage induced on each bit line BL4, BL5 will eventually decrease. . The fabrication of such a structure is also simpler since there are fewer intersections than the embodiment shown in FIG. Many other crossover patterns can be devised by those skilled in the art.

FIGS. 4 and 6 illustrate top and cross-sectional views of a portion of an integrated memory circuit and illustrate the method of fabricating complementary bit line intersections. Bit line crossing member 8
0 is formed using polysilicon using traditional methods, and bits and
A conductor may be provided for carrying signals between section 84 and section 82 of line BL. The bit line sections 82, 84 are made of silicon dioxide insulation layer 8.
6 may be constructed of metal insulated from the polysilicon cross member 80. Electrical contacts 88, 90 are formed through silicon dioxide 86 and from metal bit line section 82 to polysilicon cross member 80;
The electrical path from cross member 80 to the other metal bit line section 84 is then completed.

The bit line sections 91, 92 forming the bit line BL are also formed of metal separated from the underlying polysilicon cross member 94 by an oxide insulating layer. When forming bit line crossing member 80, it is important that the bit line BL and its complementary line BL are in electrical contact.

According to another technical feature of the invention, a cross-connected transistor pull-up is provided at the intersection of the crossed bit lines BL, BL. Fabrication of cross-connected transistors at bit line intersections can be conveniently performed. For this purpose, the P-channel
Source region 96 and drain region 98 of transistor 100
are formed on the surface of the N-type substrate 102. Metal bit line section 82 includes an extension 104 with a contact 106 to the underlying transistor source region 96. Metal supply voltage rail or bus 1
08 is also formed with a contact 109 to the underlying transistor drain region 98. source area 96
and drain region 98 are heavily doped with P+ semiconductor impurities. Polysilicon cross member 94 of the other bit line BL forms the gate electrode of transistor 100. Therefore, transistor 100 is a P-channel transistor.
transistor, whose gate is connected to the bit line BL
, the source is connected to the bit line BL,
Its drain is connected to the supply voltage. Therefore, when the power of bit line BL is pulled below that of bit line BL, the latter bit line is pulled up to the supply voltage.

A second P-channel transistor 110 connects substrate 10 in a manner comparable to that of transistor 100.
It is formed in 2. However, the base of transistor 110 is connected to bit line BL through polysilicon cross member 80, and its source 112 is connected to bit line BL.
Connected to line BL. transistor 100,1
The ten drain areas 98 are common and supply rail 108
It is connected to the. Transistor 110 operates in a similar manner to transistor 100, with P-channel transistor 110 conducting when the voltage on bit line BL is lower than that on bit line BL. The bit line BL is thereby pulled up to the supply voltage. Like the bit line structure, fabrication of the transistor structure of FIG. 6 is accomplished using conventional integrated circuit fabrication techniques. However, manufacturing methods can be used to form the intersection and the associated circuitry underneath.

FIG. 7 is a circuit diagram illustrating the cross-connect pullup feature of the present invention, which can be conveniently utilized in conjunction with the crossed bit line feature. In the circuit diagram of FIG. 7, a data input logic signal and its complement are provided to a pair of N-channel transistors 114, 116. Inverter 118 provides the complement of the signal on logic data in to transistor 114. The write signal on input 120 is provided to the gate terminal of each transistor 114,116. A pair of cross-connected pull-up transistors 122, 124, different from those described above, are connected to the bits.
Connected between line segments 126 and 134. As explained in more detail below, transistor 1
22, 124 form part of the sense amplifier 125 used for the complementary bit lines mentioned above. An N-channel transistor 130 is connected in series with bit line segments 126,128. Similarly, an N-channel transistor 132 is connected in series between bit line segments 134 and 136. A column select input 138 is connected to the respective gates of transistors 130 and 132 for selecting a particular column of a typical memory. N-channel transistors 140, 142 connect memory cell 144 to bits.
A connection is made between line segments 128 and 136.

Word line input 146 drives the respective gates of transistors 140 and 142 to retrieve or store data in storage cell 144 during a read or write operation. The bit lines 128, 136 form an intersection 148, with the upper bit line section 128 connected to the lower bit line section 150 and the other lower bit line section 136 connected to the lower bit line section 150.
is connected to the other upper bit line section 152. The crossed complementary bit lines are tangibly formed such that the voltage induced therein has a component common to both bit lines of the pair. Bit line section 12
8 forms part of a complementary bit pair parallel to and adjacent to bit line section 136. Bit line section 128 extends adjacent bit line section 136 a desired distance until the two lines intersect at point 148. Bit line section 128 is on one side of section 136, and upon crossing, these sections are laterally flipped and further extended the desired distance in parallel-adjacent relationship. Although both bit line sections are recursed to form an intersection 148, one bit line of the pair can extend directly into the path, while the other can traverse it back and forth. and form a parallel adjacency relationship.

A pair of cross-connected pull-up P-channel transistors 154, 156 are connected between bit line sections 150, 152, as described above. Bit line sections 150, 152 extend through the other half of the memory section to the right of the figure. Memory storage element 158 is connected to bit lines 152, 15 by respective transistors 160, 162 in the other half of this memory section.
Connected to 0. Word line input 164 is connected to the gates of transistors 160 and 162 to cause the selected memory cell 158 to be written.

As mentioned above, P-channel pull-up transistors 154 and 156 are connected to bit line intersections 14.
8 to increase the noise immunity of the memory during read and write operations. Each transistor 154, 15
6's drain terminals are both connected to the supply voltage VCC, and their respective source terminals are connected to the bit lines 152, 150.
It is connected to the. The gate terminal of transistor 154 coupled to bit line 152 is connected to bit line segment 150. The gate of transistor 156 similarly connects to the other bit line segment 15.
Connected to 2. Transistors 154 and 156 are P
A channel transistor, which renders the transistor conductive when its respective gate is driven to a voltage lower than that present on the bit line connected to its respective source terminal. As a result, when a lower voltage on line 150 appears on bit line segment 152, transistor 156 becomes conductive, connecting supply voltage VCC to bit line segment 150. Similarly, when a lower voltage on line 152 appears on bit line segment 150,
Transistor 154 is conductive to supply voltage VCC.
is connected to bit line segment 152. In this way, pull-up transistors 154, 156
facilitates reliable determination by sense amplifier 125 of the logic state of a memory read by pulling one bit line up to the supply voltage, while the memory cell pulls the other bit line towards a logic zero level. Pull.

Cross-connected pull-up transistor 1
54,156, bit line 150,152
The positive feedback generated during reading and writing increases the noise immunity of the memory. The storage element of memory cell 158 typically includes a pair of cross-connected transistors forming a flip-flop. Before performing a storage operation for a particular memory cell, the associated bit line is precharged by transistors 166 and 168. A signal is applied to the PC line of precharge transistors 166, 168 to momentarily turn them on and transfer the VCC supply voltage to bit lines 150, 1.
Connect to 52. During read operations, word line 1
64 is clocked to cause transistors 160 and 162 to conduct. Whether 1 is stored in memory cell 158 or 0
A voltage somewhat lower than VCC is connected to one of the bit line segments 150 or 152, depending on whether the bit line segment 150 or 152 is stored. For example, in a memory with a supply voltage (VCC) of 5 volts, if the differential sense amplifier 125 initially
．． If 00 volts is detected on bit line segment 152 and a lower voltage is detected on bit line 150, then, for example, a zero is assumed to have been stored in memory cell 158. The voltage would be reversed if a 1 was previously stored in memory cell 158.

In the above example, the differential amplifier begins to provide a reliable output when the voltage difference between bit line segments 150, 152 is on the order of the FET transistor limit voltage. As mentioned above, cross-coupled pull-up transistors 154, 156 are provided to help provide reliable sense amplifier operation for differentiating memory cell read voltages corresponding to 1 or 0 bits. For example, if bit line 152 is
．． A single transistor limit voltage below VCC of 00 volts causes transistor 156 to conduct, ensuring that bit line segment 150 is pulled up to 5 volts. Similarly, if a cell read forces bit line segment 150 to a critical voltage below VCC, transistor 154 conducts and raises the other bit line 152 to VCC. This feature increases the differential read voltage of the memory cell 134 by ensuring that electrical noise appearing on the bit lines that are not brought to a low voltage by reading the cell is erased by the positive pull up to the supply voltage.

A similar cross-connected pull-up configuration consists of P-channel transistors 122, 124 connected across bit line segments 126, 134. Similarly to transistors 154 and 156,
Transistors 122 and 124 are cross-coupled so that when one bit line segment is brought to a lower positive voltage, the other bit line segment is brought to the VCC voltage. This is the situation when one memory cell on a bit line is selected and read. A sense amplifier function is also realized in this way. Other sense amplifiers of the more sensitive or differential type can be used with the present invention.

Bit line section 126, 13
The active pull-up of 4 is important because these sections are isolated from the pull-up of bit line sections 150, 152 when column select transistors 130, 132 are turned off. Therefore, without the pull-up by transistors 122, 124, bit line sections 126, 134, 1
There is some loss of noise immunity between 28 and 136. Cross-coupled pull-ups by P-channel transistors 122 and 124 also provide a full logic low or logic high voltage to the data output through inverter 127. Inverter 127 includes transistors 122, 12
4, provides sense amplifier functionality that can drive other circuits at full logic levels.

According to another feature of the invention, column select transistors 130, 132 are configured as N-channel devices to improve read reliability of signal voltages on bit lines 128, 136. transistor 130
, 132 are formed as N-channel devices and allow small signal voltage changes to occur on column select line 1.
If it is within the transistor limit voltage of the level above 38, it will not pass from bit line segment 128 to 136. For example, if the threshold voltage of transistor 122 is approximately 1 volt and a clock signal of approximately 5 volts is applied to column select line 138, transistor 130
does not conduct until the voltage on bit line 128 reaches approximately 4 volts. Therefore, in this example, there is approximately 1 volt margin for noise to appear on bit line 128 without transistor 130 conducting.

Transistors 114 and 116 are turned off, and word line 146 and column select line 1
38 is clocked, the contents of memory cell 144 are read and output on complementary bit lines 128 and 136. The read voltage on that bit line is applied to the cross-coupled pull-up transistors 122,
124 to the appropriate logic high and low levels. As mentioned above, the transistors 122 and 124 are
It acts as a sense amplifier to generate a complete digital signal from the memory cell read signal. Inverter 12
The output of 7 provides drive capability to the data output to drive the other circuit.

Also, as described above, data bits are written to the desired cells of the complementary bit lines by providing the data bits and their complementary bits to respective N-channel transistors 114, 116. Although N-channel transistors are inherently excellent switching transistors, they are not designed to provide rapid drain recovery at the upper end of the supply voltage. However, P-channel devices provide superior fast recovery to the supply voltage rail, thereby compensating for the shortcomings of N-channel devices. Therefore, P-channel transistor 1
22, 124 are N-channel transistors 114, 11
6 provides a beneficial combination for fast switching and perfect pull-up to the supply voltage. Therefore, bit line 126 or 13 during a write operation.
6 is a P-channel transistor 122 or 124
It is ensured that one of the voltages is quickly brought to the supply voltage VCC. The foregoing also holds true for N-channel transistors 130, 132 operating in conjunction with P-channel pull-up transistors 154, 156.

From the above, a complementary bit line structure is disclosed which has features that provide technical advantages over other memory structures previously known. For example, crossed bit line structures have been disclosed that reduce the susceptibility of memory circuits to interference from unwanted electrical signals. A cross-connected pull-up circuit is also disclosed that operates in conjunction with the crossed bit lines to provide positive feedback so that the differential signals on the bit lines remain clear. This can improve the operation of the sense amplifier. The use of N-channel column select transistors placed in series with each bit line of a complementary pair is also disclosed to improve the noise margin of the memory circuit. A cross-coupled pull-up circuit consisting of P-channel transistors is also employed to provide a complete logic level signal to the memory cell during a write operation or to the data output inverter during a read operation.

Although the invention has been disclosed above in connection with MOS type memories, the principles and concepts of the invention are equally and advantageously applicable to bipolar type complementary bit line memories. For example, the N-channel and P-channel devices described above can be interchanged if the bit line is pulled low instead of first being precharged high. It should be understood that many other changes in detail may be made as engineering choices without departing from the scope of the invention as set forth in the claims.

[0041] In connection with the above description, the following items are disclosed.

(1) The semiconductor memory according to claim 1, wherein the intersection has a horizontal component perpendicular to the bit line.

(2) The semiconductor memory according to item (1) above, wherein the pair of 1-bit lines includes a plurality of the lateral components.

(3) The semiconductor memory according to item (2) above, wherein the other bit line of the pair includes a plurality of lateral components.

(4) The semiconductor memory according to item (3) above, wherein the horizontal component of the other bit line is adjacent to the horizontal side of each horizontal component of the one bit line. .

(5) an output is connected to one bit line of the pair and an input is connected to the other bit line of the pair;
2. A semiconductor memory according to claim 1, further comprising pull-up means for pulling said one bit line to a first voltage when said other bit line is brought to a second voltage.

(6) An input is connected to the one bit line and an output is connected to the other bit line, and when the one bit line is set to a second voltage, the other bit line is connected to the other bit line.
The semiconductor memory according to item (5) above, further comprising cross-connected pull-up means for pulling the line to the first voltage.

(7) The cross-connected pull-up means includes a pair of P pull-up means connected in common to the terminal connected to the first voltage.
The semiconductor memory according to item (6) above, characterized in that it consists of a channel transistor.

(8) A bit line structure for use in semiconductor memory having a plurality of storage cells forming regularly arranged columns, each cell having a first port on a first side thereof. and has a second port on its second side,
the first and second ports are for communicating data signals with respective storage cells;

a first bit line connected to the first port of a portion of the plurality of cells and connected to the second port of the remaining cells of the plurality of cells;

The portion of the plurality of cells is connected to the second port, and the remaining first ports of the plurality of cells are connected, and the first and second bit lines are connected to one point. A bit line structure characterized in that the bit line structure is characterized in that the bit lines intersect at each other to reduce the differential level of undesired noise signals.

(9) The bit line structure of paragraph (8), wherein said portion of memory cells is approximately half of said regular column of memory cells.

(10) The bit line structure according to item (9) above, wherein the cells in the part are adjacent to each other.

(11) The bit line structure as set forth in item (9) above, wherein the portion of cells is every other cell in the regular column.

(12) a first transistor having a conduction channel connected between a voltage source and the first bit line and including an input connected to the second bit line; a second transistor having a conduction channel connected between the second bit line and the second bit line;
10. The bit line structure of claim 9, wherein the second transistor includes an input connected to the first bit line.

(13) The first and second transistors are P-channel transistors.

0
[057] Bit line structure described in section (12).

(14) An apparatus for reducing noise interference in a semiconductor memory, comprising: a first set of regularly arranged storage cells each having first and second input/output ports; a second set of regularly arranged storage cells having a second input/output port;

a first bit line and a second bit line that intersect at an electrically isolated intersection point, the first bit line being connected to a first input of the first set of storage cells; /output port and a second input/output port of the second set of storage cells, the second bit line being connected to a second input/output port of the first set of storage cells. and the first input/output port of the second set of storage cells;

a first P-channel transistor having a conduction channel connected between a voltage source and the first bit line, and an input connected to the second bit line; A second P-channel transistor having a conduction channel connected to a bit line and an input connected to the first bit line.

(15) further comprising first and second N-channel transistors, each of which is connected in series with the first and second bit lines, respectively, the N-channel transistor forming a column select function; The memory device according to item (14) above.

(16) further comprising third and fourth N-channel transistors, each of which is connected to the first and second N-channel transistors, respectively;
said third and fourth N-channel transistors connected in series with a bit line, said third and fourth N-channel transistors connecting data to said first and second sets of storage cells during a write operation of said memory; 15) The memory device described in item 15).

(17) further comprising a pull-up circuit connected between the first and second bit lines and insulated from the first storage cell and from the first and second N-channel transistors; and the pull-up circuit includes a P-channel transistor having a conduction channel connected between a voltage source and the first bit line and an input connected to the second bit line; and a second P-channel transistor having a conduction channel connected between the second bit line and the second bit line, and an input connected to the first bit line. Memory devices listed in section.

(18) further comprising a sense amplifier for sensing a signal read from a selected one of the storage cells, the sense amplifier being configured to detect signals from the third and fourth P-channel transistors and the buffer inverter; The memory device according to item (17) above.

(19) An active pull-up circuit for use in a semiconductor memory having complementary bit lines, the bit line being
a first transistor connected between the bit lines and responsive to a signal on one bit line to connect an opposite polarity signal to the other bit line; 1. A circuit for connecting an opposite polarity signal to said one bit line in response to a signal.

(20) The active device according to item (19) above, wherein the first and second transistors are field effect transistors having conduction channels, and each of the channels is connected to a constant voltage. pull-up circuit.

(21) The active pull-up circuit according to item (20) above, wherein the transistor is a P-channel device.

(22) The first transistor includes an input connected to the output of the second transistor, and the second transistor includes an input connected to the output of the first transistor. The active pull-up circuit according to item (19) above.

(23) Item (19) above, further comprising an N-channel FET transistor in series with each of the bit lines, and wherein the first and second transistors are P-channel FET transistors. Active pull-up circuit as described.

(24) further comprising second and third P-channel transistors connected to a bit line and functioning similarly to the first and second transistors, wherein the first and second transistor pairs are connected to the N-channel transistors; - The active device according to item (23) above, characterized in that one side of the transistor is connected to the bit line, and the third and fourth transistors are connected to the bit line on the opposite side. pull-up circuit.

(25) The N-channel transistor serves to select a column of storage cells of the memory and is further connected in series with each bit line to select a plurality of cells associated with the bit line. N-channel providing write operations
The active pull-up circuit according to item (25) above, which includes a transistor.

(26) The active pull-up circuit according to item (19), wherein the bit line includes a crossing section.

(27) The bit line is formed in an integrated circuit, and the first and second transistors are connected to the bit line.
(26) characterized in that it is formed in a semiconductor material existing below the line and connected perpendicularly thereto;
Active pull-up circuit described in ).

(28) A method of fabricating intersecting bit lines in a semiconductor memory using complementary bit lines, the method comprising: forming a first conductive connection on a semiconductor material; and forming a second conductive connection on the semiconductor material. forming a conductive connection member; forming an insulating layer on the first and second connection members; forming a first elongated conductive bit line of two sections on the insulating layer;

A second elongated conductive bit is formed on the insulating layer.
forming a line, the second bit line comprising two sections, one section of each of the first and second bit lines being adjacent and one section of each of the first and second bit lines of the other of each of the first and second bit lines. Adjacent sections;

00
76. connecting the first section of the first bit line to the first connecting member; and connecting the other section of the second bit line to the first connecting member; A method comprising the steps of: connecting the first section of the first bit line to the second connecting member; and connecting the other section of the first bit line to the second connecting member.

(29) The method of item (28) above, wherein the first and second connecting members are generally parallel to each other.

(30) Item (28) above, further comprising the step of forming a circuit that lies at least partially below the intersection of the bit lines and connecting the rotation to the bit lines. The method described in section.

(31) First region defining the source region of the transistor
forming a semiconductor region under the insulating layer; connecting the source region to the one section of the first bit line through the insulating layer; a second semiconductor region remote from the source region;
a semiconductor region is formed under the insulating layer, the second region defining a drain region to which a voltage source can be supplied; the second region between the source region and the drain region; 31. The method of claim 30, further comprising the step of forming a portion of a connecting member, said portion defining a gate conductor of said transistor.

(32) forming a third semiconductor region remote from the second region under the insulating layer; the third region defining a source region of the second transistor; and connecting to the first section of the second bit line through the insulating layer; further comprising forming a portion of the first connection member between a source region of the second transistor and the drain region; Said first
32. The method of claim 31, wherein the portion of the connecting member defines a gate conductor of the second transistor.

(33) The above-mentioned transistor is characterized in that the transistor is made as a P-channel transistor.

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82] The method described in item (31).

(34) The method according to item (32), characterized in that the second transistor is made as a P-channel transistor.

(35) Said 1 of said first and second bit lines
the same bit between the section and the other section.
The above-mentioned step (1) further comprises the step of forming a conductor on the insulating layer that extends transversely to the line.
31) The method described in section 31).

(36) The method according to item (35), further comprising the step of connecting the conductor to the drain region and supplying voltage to the region.

(37) A method for improving noise insensitivity of a semiconductor memory having complementary bit lines, the method comprising:
A method characterized in that the bit lines are crossed in such a way that the noise induced in the lines is common to both lines of said complementary bit pair.

(38) further arranging the location of the intersection of one bit line pair relative to the intersection of an adjacent bit line pair such that the net effect of voltage induced between the bit line pair is reduced; No. (37) above, characterized in that it includes
The method described in section.

(39) The method of item (37), further comprising the step of forming the crossed bit lines when the bit lines are adjacent to other signal transmission conductors.

(40) The method according to the above item (39), wherein the bit line is formed under the other signal transmission conductor.

[Brief explanation of the drawing]

1 shows a microprocessor in which the invention can be advantageously applied; FIG.

FIG. 2 is a circuit diagram of a representative memory structure showing the crossing of complementary bit line pairs.

FIG. 3 illustrates another technique for intersecting alternating columns of complementary bit lines in different patterns.

FIG. 4 shows yet another pattern of intersecting alternating columns of complementary bit lines.

FIG. 5 shows a semiconductor structure effective for crossing complementary bit lines.

6 is a cross-sectional view of the semiconductor structure of FIG. 5 taken along line 6--6; FIG.

FIG. 7 is a circuit diagram of a crossed bit line incorporating cross-connected pull-up transistors.

[Explanation of symbols]

10 Microprocessor chip 14 Data bus 20, 24 Conductor 26, 28 bit line 30 Memory cell 34 Word line 38, 40, 42, 44 Parasitic capacitance 80 Cross member 96 Source area 98 Drain area 100, 110 transistor

Claims (1)

[Claims] 1. An active pull-up circuit for use in a semiconductor memory having complementary bit lines, the circuit comprising: a first transistor coupled between the bit lines and having a section where the complementary bit lines intersect; a second transistor coupled between the bit lines, the transistor coupling an opposite inverse signal to the other bit line in response to a signal on one bit line; the transistor couples an opposite inverse signal to the one bit line in response to a signal on the other bit line, and the first and second transistors couple an opposite inverse signal to the one bit line in response to a signal on the other bit line; and formed at least partially below a section intersected by the bit lines.