JPS618792A - Precharging circuit - Google Patents

Abstract

PURPOSE:To allow the precharging circuit to serve as part of a sense amplifier circuit, and reduce the chip size of a memory circuit by connecting two among three FETs forming the precharging circuit as specified. CONSTITUTION:Insulating gate type FETs 9-11 constitute the precharging circuit; the gate and drain of the FET10 are connected to bit lines Bj and Bj' and those of the FET11 are connected to Bj' and Bj. The FET10 or 11 connected to the lines Bj or Bj' having a lower potential turns on first and the potential of the higher-potential line becomes further higher in potential. When the FET9 is turned on with a clock while part of this sense amplifier function is carried out, the lines Bj and Bj' to be short-circuited are held at the same potential and precharged by a power source VD in the equal-potential state. Thus, the FETs 10 and 11 serve as part of the sense amplifier circuit, thereby reducing the chip size of the memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to insulated gate field effect transistors (hereinafter referred to as I
The present invention relates to a precharge circuit using a GFET (abbreviated as GFET).

Conventional configuration and its problems In order to write and read data into memory cells faster, a pair of complementary bit lines, that is, a bit line and a bit line, are connected to a voltage source. It has been done to precharge to a potential close to , and at the same time short-circuit to the same potential.

FIG. 1 shows a conventional precharge circuit.

(The part surrounded by a dotted line in the figure is a precharge circuit.) This circuit is composed of a bit line, and an MIS type transistor, which is a typical example of an IGFET, and the bit line Bi and the bit line Bi are , MIS type P-type medium channel transistors 1- are connected to the source and drain, respectively, and MIS type transistors 2 and 3 are connected to each other.
connected to each drain of the The gates of MIS type transistors 1 to 3 are all connected to a signal source a, and the same clock pulse φp1 is applied thereto.

Initially, there is a potential difference between the bit line Bi and the bit line Bi. At this time, the clock pulse φp1 is.

When it becomes "high level", MIS type transistor 1
When in the on state, charge is transferred between the bit line Bi and the bit line Bi through the MISmP channel transistor 1, and the potential becomes equal. At this time, the same clock pulse φp1 turns on MIS type P-channel transistors 2 and 3, respectively, and serves to raise the potential of both bit line Bi and bit line Bi.

In FIG. 1, MIS type P-channel transistor 2 transistor 4,
6 and MIS type N-channel transistors 6 to 8 constitute a sense amplifier.

When the clock pulse φp1 is at "low level", the precharge circuit does not operate.

At this time, the clock pulse φ applied from the signal source
When L1 becomes "high level", this sense amplifier operates and the potentials of bit line Bi and bit line Bi are amplified.

However, since there is one set of precharge circuits for each pair of bit lines, the area occupied by the precharge circuits is quite large, which poses a problem in further reducing the chip size.

OBJECTS OF THE INVENTION The present invention provides a precharge circuit that aims to reduce the chip size to 7J with a simple circuit by having the precharge circuit also serve as a part of the sense amplifier circuit. It is.

Structure of the Invention The present invention provides a voltage source and a first voltage source having a capacitance. a second bit line; a first insulated gate field effect transistor having a gate connected to the first bit line, a drain connected to the second bit line, and a source connected to the voltage source; , a second insulated gate field effect transistor having a gate connected to the second bit line, a drain connected to the first bit line, and a source connected to the voltage source; The precharge circuit is constituted by a third insulated gate field effect transistor whose source and drain are respectively connected to the second bit line and whose gate is connected to an external signal source. It is possible to simplify the process and reduce the chip size.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a unit configuration diagram of a circuit according to an embodiment of the present invention. A first MIS type P-type medium channel having a bit line Bj and a bit line B1 having capacitance, a gate connected to the bit line B1, a drain connected to the bit line B), and a source connected to the voltage source VD. A transistor 10 has a gate connected to the bit line Bj, a drain connected to the bit line Bj, and a source connected to the voltage source VD. A second MIS type P-type medium channel transistor 11 whose source and drain are connected to the bit line Bj, respectively. Bit line B5
A third MIS type P-type medium channel transistor 9 whose gate is connected to a signal source C applying a clock pulse φp2 constitutes a precharge circuit. The part surrounded by the chain line in the figure is the precharge circuit.

Since the first to third MIS type transistors 9 to 11 are of P-channel enhancement type, they are turned on when the gate voltage is at a "low level".

Initially, there is a potential difference between the bit line Bj and the e-) line Bj, and the MIS type P-type medium channel transistor 10 whose gate is connected to the bit line with a lower potential
When the transistor 11 is turned on first, the voltage source vD is supplied with a stain, and the MIS type P-type medium channel transistor 10 in the on state is connected to the bit line on the side connected to the drain of the transistor 11. The potential increases. Due to this operation, the bit line with a higher potential becomes a higher potential.

Here, when the clock signal φp2 becomes low level, the MIS transistor 9 is turned on, and the charge is transferred between the bit line Bj and the 77th line. and have the same potential. At this time, charge is supplied from the voltage source VD, and 2
The potential of the book's bit line increases while it remains short-circuited.

Comparing FIG. 1, which shows a conventional precharge circuit and sense amplifier, with FIG. 2, which shows an embodiment of the present invention, it is found that the MIS type P-type child channel transistor 1 in FIG.
It can be seen that 01 corresponds to MIS type transistors 2 and 3 as a precharge circuit and MIS type transistor 4.5 as a sense amplifier in FIG.

That is, the MIS type P-type child channel transistor 101 of this embodiment has both the function of precharging a pair of bit lines (bit line Bj and bit line B) and the function of a sense amplifier.

As described above, according to this embodiment, the first. Second MIS
By allowing the P-type child channel transistor 101 to perform six functions as both a precharge circuit and a sense amplifier, the overall circuit becomes simpler and the chip size can also be reduced.

Effects of the Invention According to the present invention, in a conventional precharge circuit, a pair of bit lines, 77 underline, are each connected to the drain, the same voltage source is connected to the source, and the gate is connected by the same external signal source. Two MISs that are connected to the
A part of the sense amplifier circuit (MIS type P type medium channel transistor whose source is connected to the same voltage source, whose drain is connected to the bit line, and whose gate is connected to the bit line) MIS type P-type medium channel transistor whose drain is connected to the bit line and gate is connected to the bit line, and also functions as a precharge circuit, simplifying the circuit and reducing chip size. be able to.

Since the precharge circuit is coupled to a pair of bit lines (one bit line and one bit line), it occupies a large proportion of the chip as a whole. Therefore, the effects of circuit simplification and size reduction according to the present invention are very large.

[Brief explanation of the drawing]

FIG. 1 to 5, 9 to 11...MIS type P type medium channel transistor~8.12 to 14...MIS type N
Type channel transistors i, Bi, Bj, Bj...
... Bit line, a - d ... Signal source, φP1
．． φP2+φL1. φL2...Clock pulse, VD...Voltage source. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] first and second bit lines connected to a voltage source, a gate connected to the first bit line, a drain connected to the second bit line, and a source connected to the voltage source. a first insulated gate field effect transistor; a second insulated gate field effect transistor having a gate connected to the second bit line, a drain connected to the first bit line, and a source connected to the voltage source; an effect transistor, and a third insulated gate field effect transistor having a source and a drain connected to the first bit line and the second bit line, respectively, and a gate connected to an external signal source. A precharge circuit characterized by: