JPS6235189B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is a static type transistor composed of MISFET (insulated gate field effect transistor).
Regarding RAM (Random Access Memory).

For example, a circuit as shown in FIG. 1 is used as a static RAM built into a digital control circuit of an electronic desktop calculator or the like. This circuit consists of a p-channel as shown in Figure 2.
Figure 1 shows a memory cell MC constructed by providing an n-channel transmission gate MISFET at the input and output of a static flip-flop circuit in which the input and output of a complementary inverter circuit composed of an MISFET and an n-channel MISFET are common. The gates of the transmission gate MISFETs of the memory cells arranged in the same row are used as a common word line W, and the input through the transmission gate MISFET of the memory cells arranged in the same column is arranged in a matrix. A pair of data lines D are configured with a common output. The above word line is connected to the X address signal x ₁ ~
The selection is made by an X address decoder circuit composed of a dynamic logic circuit that receives _x4 as an input.

Inverter circuits IN ₁ to _{IN 4} are output buffer circuits that form the word line selection signal.

On the other hand, the data lines are connected to Y address signals y ₁ , y ₂
is selected by a Y-address decoder circuit composed of a dynamic logic circuit that receives as input. Inverter circuits IN ₅ and IN ₆ are output buffer circuits that form the data line selection signal. The common data line I/O configures the data line D in each column as common through the transmission gate MISFET controlled by the output of the inverter circuits IN ₅ and IN ₆ , and serves as a read/write input terminal. That is.

In the same figure, the marks marked with ○ are the MISFETs that make up each selection circuit as described above, and the ones marked p are the data lines, common data lines, and p channels that make up the address decoder circuit.
MISFET, and only other ○ marks are n
Channel MISFET. Among the above n-channel MISFETs, the MISFET provided on the power supply terminal -V _DD side of the address decoder circuit
is a discharge MISFET that defines the read timing of the address signal.

In this circuit, the low level of the timing pulse φ, which is the output of the inverter circuit IN ₁₂ , turns on the precharge MISFETs of the address decoder circuit, the data line, and the common data line to perform precharging, and the high level turns off the precharge MISFETs. At the same time, the discharge MISFET of the address decoder circuit is turned on to perform a selection operation. Therefore, the earlier the word line selection timing is than the data line precharge end due to parasitic requirements and resistance of the wiring that supplies the timing pulse φ, the more the circuit itself is logically incomplete, resulting in erroneous writing. The problem was discovered.

This invention was made in order to provide a MIS static type RAM that prevents malfunctions using a simple circuit.

The present invention uses a common timing pulse to logically form a pulse that starts a precharge period of an address decoder circuit for word line selection at an earlier timing and ends at a later timing than a data line precharge period. This is to control the precharge MISFET.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 3 is a circuit diagram showing an embodiment of the present invention.

This circuit consists of memory cells MC arranged in a matrix, forming a word line W that shares the gates of the transmission gates MISFET of the memory cells arranged in the same row, and memory cells arranged in the same column. A pair of data lines D are formed by using a common input/output line via the transmission gate MISFET of the cell.

The word line has inverted signals 1 _{to 1} formed by X address signals x ₁ to x ₄ and inverter circuits IN ₇ to IN ₉ .
The MISFET marked with a ○ mark with ₄ inputs is used as a logic block, and the precharge MISFET installed on the ground potential terminal (OV) side and the power supply terminal (-V _DD )
The output of the X address decoder circuit, which consists of a discharge MISFET installed on the side,
Inverter circuit IN ₁ as output buffer circuit
The selection is via IN ₄ .

On the other hand, the data line is an inverted signal formed by Y address signals y ₁ and y ₂ and inverter circuits IN ₁₀ and IN _11.
An inverter circuit as an output buffer circuit is generated by the output of a Y address decoder circuit configured with a dynamic logic circuit similar to the above with ₁ and ₂ inputs.
It is selected via IN ₅ and IN ₆ .

That is, each data line is provided with a transmission gate MISFET controlled by the output of the inverter circuits IN ₅ and IN ₆ , respectively, and these transmission gates are
Through MISFET, data lines D,
common data line I/
0, and serves as a read/write input/output terminal.

The above data line and common data line are each provided with a precharge MISFET indicated by a circle.

In the same figure, the ones marked with p are p-channel MISFETs, and the others are n-channel MISFETs.
It is MISFET.

In this embodiment, the precharge
The timing pulse φ that controls the MISFET and the discharge MISFET is set to low level (-V _DD ).
The precharge MISFET of the data line and the common data line is activated by the timing pulse _φA formed through the inverter circuit _IN15 set to the logic threshold voltage _VLA shifted to the side and the inverter circuit _IN16 for phase matching. shall be controlled;
The above timing pulse φ is set to high level (OV)
_{The precharge MISFET and} This controls the discharge MISFET.

As a result, as shown in FIG. 4, the timing pulse φ _A can fall later and rise faster than the timing pulse φ _B.

In this example circuit, the p-channel
Since the MISFET constitutes a precharge MISFET, it is assumed that the precharge operation is performed at a low level. Therefore, the precharge operation of the address decoder circuit controlled by the timing pulse φ _B is controlled by the timing pulse φ _A
This starts earlier and ends later than the precharge operation of the data line and common data line controlled by .

As a result, when transitioning to a selection operation, the precharge MISFET of the data line is turned off at an early timing, so that erroneous writing due to the precharge MISFET being on when the data line is selected can be prevented.

Also, when transitioning to pre-charge operation, the MISFET of the address decoder circuit is activated at an early timing.
turns on and starts precharging the data line after all word lines are unselected. Also, erroneous writing (data line (disappearance) is prevented.

The circuit of this embodiment can be realized by a simple circuit by simply adding the inverter circuits _IN18 to _IN16 .

In addition, _the logic threshold voltage of the inverter circuits IN ₁₃ and IN _{15 is}
It can be set as described above by the mutual conductance ratio of the p-channel MISFET and the n-channel MISFET that constitute the.

The present invention is not limited to the above embodiments, and the timing pulses φ _A and φ _B are, for example, inverter circuits IN ₁₈ and φ B as delay circuits, as shown in FIG.
It may be formed by IN ₁₉ , an AND gate circuit G ₁ and an OR gate circuit G ₂ which receive this delayed output and the timing pulse φ as inputs. Note that this circuit is configured with a load logic in which a low level is "1" and a high level is "0".

Further, the memory cells constituting the memory circuit may be any static type memory cells, and the address decoder circuit may be any dynamic logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a memory circuit, FIG. 2 is a circuit diagram showing an example of a memory cell, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of the memory cell. The operating waveform diagram and FIG. 5 are essential circuit diagrams showing another embodiment of the present invention.

Claims (1)

[Claims] 1. A plurality of static memory cells arranged in a matrix, a plurality of word lines to which selection terminals of the static memory cells in each row are connected, and input/output of the static memory cells in each column. a plurality of data lines having terminals coupled to each other, precharging means coupled to each data line, and a dynamically operated first selection circuit for selecting the word line;
a second timing pulse that starts the precharge period of the first selection circuit at an earlier timing and ends it at a later timing than the precharge period of the data line based on the first timing pulse; A third circuit that starts at a later timing and ends at an earlier timing than the precharge period of the first selection circuit.
A MIS static type RAM comprising at least a pulse forming circuit for forming at least a timing pulse. 2. The MIS static RAM according to claim 1, wherein the first selection circuit comprises a dynamically operated address decoder circuit and an output buffer circuit that receives the output thereof. 3. The MIS static type RAM further includes a transmission gate means provided between the data line and the common data line, and a second selection circuit for dynamic operation that controls the transmission gate means in accordance with an address signal. MIS static type RAM according to claim 1 or 2, characterized in that: 4. The MIS static RAM according to claim 1, 2 or 3, wherein the MIS static RAM constitutes a built-in RAM in a digital control circuit.