JPH04186776A - Vertical mos field effect transistor - Google Patents

Abstract

PURPOSE:To eliminate a current concentration part in a drain region and to dispersively supply a current by forming a groove on the surface of a semiconductor substrate between first diffused regions of first and second regions, and forming a gate oxide film and a gate electrode on the surface region in the groove and the surface of the first diffused region to become a channel region. CONSTITUTION:Grooves 11 are formed on the surface of a low concentration drain region 1 between diffused regions 2 of first and second regions 8, 9, and a gate oxide film 14 is formed over the channel forming p-type diffused region 2 and the surface of a low concentration n-type silicon substrate 1 formed with the groove 11, and a gate electrode 15 is formed thereon. When a voltage is applied to the electrode 15, a channel is formed in a boundary between the region 2 and the film 14, a current from the region 3 flows along the boundary between a silicon substrate of the drain region 1 and the film 14 to immediately reach the bottom of the groove 11, and then reach a drain electrode 7 while flowing to extend in the region 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical MO3 field effect transistor.

Conventional technology Vertical MOS field effect transistor (hereinafter referred to as vertical MO5F)
ET) is excellent in terms of high voltage resistance and high speed, and is used as an ideal switching prevention in a wide range of fields such as motor drives and switching power supplies.

FIG. 2 is a structural sectional view of a conventional vertical MO3FET. In FIG. 2, 1 is a drain region, 2 is a diffusion region,
3 is a source region, 4 is a gate oxide film, 5 is a gate electrode,
6 is a source electrode, 7 is a drain electrode, 8 is a first region, and 9 is a second region.

The configuration of the n-channel vertical MOSFET will be described in detail below.

This vertical MOSFET is divided into at least two parts, a first region 8 and a second region 9, on a predetermined surface region of a low concentration n-type silicon semiconductor substrate that forms a drain region 1, and is used for forming a channel region. A p-type diffusion region 2 is formed. A source region 3 consisting of an n-type diffusion region separated from the drain region 1 is formed in a predetermined surface region of the p-type diffusion region 2 . Then, a p-type diffusion region (- region 2, drain region 1, and source region 3 on the surface of the silicon semiconductor substrate on the channel side) is formed across the first, fourth, and second regions 8, 9. A gate oxide film 4 is formed, and a gate electrode 5 is further formed on the gate oxide film 4.
is formed. The source electrode 6 is formed across the surfaces of the source region 3 and the p-type diffusion region 2 in each of the first and second regions 8.9, and the drain electrode 7 is formed on the back surface of the silicon semiconductor substrate. .

In the vertical MOSFET with this structure, when a voltage is applied to the gate electrode 5, a channel is formed at the interface between the p-type diffusion region 2 and the gate oxide film 4, and electrons pass from the source region 3 through this channel to the drain region 5. , and flows from there toward the drain electrode 7 provided on the back side of the semiconductor substrate.

In this structure, electrons flowing through the drain region 1 are concentrated in a portion of the drain region 1 between the p-type diffusion regions 2 of the first and second regions 8.9. There was a problem that the voltage drop in the vertical MOSFET becomes large and the resistance when the vertical MOSFET is turned on (on resistance) becomes extremely large.

In order to eliminate the above-mentioned disadvantages, the vertical MO5FET of the present invention disperses the current in the drain region 1 by preventing it from flowing concentratedly in the drain region 1 portion between the p-type diffusion regions 2, and has an on-resistance of The purpose is to reduce the

Means for Solving the Problems In order to achieve this object, the vertical MOS field effect transistor of the present invention includes a semiconductor substrate of one conductivity type which becomes a drain region, and at least first and second regions on the surface of the semiconductor substrate. a first diffusion region of opposite conductivity type which is divided into two parts, and a second diffusion region of one conductivity type which becomes a source region and which is formed on the surface of the first diffusion region separately from the semiconductor substrate.
a groove formed in the surface of the semiconductor substrate between the first diffusion regions of the first and second regions, and a surface of the first diffusion region that becomes the inner surface region of the groove and a channel region. It consists of a gate oxide film formed above and a gate electrode formed on the gate oxide film.

Effect: According to this structure, when the vertical MOSFET is in a conductive state, electrons that pass through the first diffusion region, which becomes the channel region, eventually reach the bottom of the groove, and then disperse and flow into the semiconductor substrate, which becomes the drain region, thereby establishing conduction. The on-resistance during the state is reduced.

Embodiment FIG. 1 shows a structural sectional view of a vertical MOS field effect transistor (hereinafter referred to as vertical MOSFET) in one embodiment of the present invention. In FIG. 1, 1 is a drain region, 2 is a diffusion region, 3 is /-, 1iJjL, 6 is a source electrode, 7 is a drain electrode, 8 is a first region, 9 is a second region, 11 is a groove, 14 1 is a gate oxide film, and 15 is a gate electrode.

The configuration of the n-channel vertical MOSFET will be described in detail below.゛The vertical MOSFET of the present invention has a p-type layer for forming a channel region in at least two parts, the first region 8 and the second region 9, in the lightly doped n-type silicon semiconductor substrate that forms the drain region 1. A first diffusion region 2 is formed. Further, in a predetermined surface region of the diffusion region 2, a source region 3, which is separated from the drain region 1 and is an n-type second diffusion region, is formed. Then, a groove 11 was formed on the surface of the low concentration drain region 1 between each of the diffusion regions 2 of the first region 8 and the second region 9, and the channel forming p-type diffusion region 2 and the groove 11 were formed. A gate oxide film 14 is formed across the surface of the low concentration n-type silicon substrate 1, and a gate electrode 15 is further formed thereon. Source electrode 6 is formed across the surfaces of diffusion region 2 and source region 3 of first region 8 and second region 9, respectively, and drain electrode 7 is formed on the back surface of the silicon semiconductor substrate.

According to this structure, when a voltage is applied to the gate electrode 15, a channel is formed at the interface between the diffusion region 2 and the gate oxide film 14, and the current from the source region 3 flows between the silicon substrate, which is the drain region 1, and the gate oxide film. After flowing along the interface of the membrane 14 and reaching the bottom of the groove 11, the drain region 1
It flows while spreading and reaches the drain electrode 7. Unlike the conventional structure (Fig. 2), current does not flow concentratedly in the drain lightly doped region between the divided p-type diffusion regions, so in the vertical MOSFET of the present invention, the resistance due to the drain lightly doped region is reduced. Ingredients run out.

Effects of the Invention The present invention has the advantage that in a vertical MOSFET, there is no current concentration part in the drain region, the current flows in a distributed manner, and there is no drain resistance in the part forming the groove.
This has the effect of reducing the on-resistance of SFET by about 30% compared to the conventional one.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view showing a vertical MOSFET according to an embodiment of the present invention, and FIG. 2 is a structural sectional view showing a conventional vertical MOSFET. 1... Drain region, 2... Diffusion region, 3... Source region, 4, 14... Gate oxide film, 5, 15... ...Gate electrode, 6...
...Source electrode, 7...Drain electrode, 8
...First area, 9...Second area,
11...Groove.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type serving as a drain region; a first diffusion region of an opposite conductivity type formed on the surface of the semiconductor substrate divided into at least two regions, a first region and a second region; and the first diffusion region. a second diffusion region of the one conductivity type, which serves as a source region, formed separately from the semiconductor substrate on the surface of the semiconductor substrate;
A groove formed on the surface of the semiconductor substrate between the first diffusion regions of the first and second regions, and a gate formed on the surface of the first diffusion region that becomes the inner surface region of the trench and a channel region. A vertical MOS field effect transistor comprising an oxide film and a gate electrode formed on the gate oxide film.