JPH04107877A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To reduce chip size by providing a second conductivity type extended drain area which contacts with a drain contact area, providing a first conductivity type area which is biased reversely to the extended drain area in the extended drain area and permitting the surface of a semiconductor substrate between the extended drain area and a source area to be a channel area so as to provide a gate electrode on the channel area through a gate oxide film. CONSTITUTION:Boron is ion-implanted in an extended drain area 11, some heat processing is performed, then, the surface of a semiconductor substrate 15 is thermally oxidized. Thus, the segregation coefficients of the boron in a silicon oxide film 8 and the boron in silicon are differentiated. Thus, the boron density at the surface of the substrate 15 is reduced to be N-type and a P-type area is buried in the extended drain area 11. The P-type area 10 is biased reversely to the drain area 11 and depletion layers are spread between the extended drain area 11 and the semiconductor substrate 15 and between the P-type area 10 in the extended drain area 11 and the extended drain area 11. Therefore, the on-resistance between the drain sources becomes smaller than the MOSFET of the conventional structure.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device and its manufacturing method, and particularly to a MOSFET which requires a high breakdown voltage between drain and source.
It can be used as an ET.

Conventional technology FIG. 2 shows a cross section of a conventional high voltage lateral MO3FET.

In order to increase the breakdown voltage between the drain 20 and the source 23, an extended drain region 21 with a low impurity concentration is formed in the semiconductor substrate 25, and when the region between the drain 20 and the source 23 is reverse biased, the extended drain region 21 is depleted. I try to spread out the layers. In addition, in the figure, 16 is a drain electrode,
17 is a source electrode, 18 is a silicon oxide film, 19 is a gate electrode, 22 is an anti-punch-through region, and 24 is a substrate contact region.

Problems to be Solved by the Invention In the conventional structure including the extended drain region as described above, when a reverse voltage is applied, the depletion layer spreads from the junction between the extended drain region 21 and the semiconductor substrate 25;
In order to increase the 0-source 23 breakdown voltage, the concentration of the extended drain region 21 must be made low so that the extended drain region 21 is depleted. Although a high breakdown voltage can be achieved by this, the resistance component in the extended drain region 21 increases, and the drain 20-source 23 of the MOSFET increases.
This has the disadvantage that the on-resistance increases during operation, the loss during operation increases, and the element size must be increased in order to allow a large current to flow.

Means for Solving the Problems In order to solve the above-mentioned problems, in the present invention, between the source region of the second conductivity type provided on the semiconductor substrate of the first conductivity type and the drain contact region, providing an extended drain region of a second conductivity type in contact with the extended drain region, providing a first conductivity type region reversely biased with the extended drain region within the extended drain region, and using a surface of the semiconductor substrate between the extended drain region and the source region as a channel region; A gate electrode is provided on this channel region via a gate oxide film.

Operation By employing the structure of the present invention as described above, it is possible to achieve a high breakdown voltage and to significantly reduce the drain-source on-resistance.

Embodiment FIG. 1 shows a cross section of an N-channel MOSFET in an embodiment of the semiconductor device of the present invention. Extended drain region 11
The surface concentration of is approximately 1×10 cm, and a P-type region 10 is formed in this extended drain region 11.
The concentration of 0 was greater than 5×10 cm. Semiconductor substrate 1
The concentration of 5 was set to 3×10140I11-3, and the thickness of the silicon oxide film 8 on the surface of the semiconductor substrate 15 was set to 2 μm or more. A polycrystalline silicon film was used for the gate electrode 7. The silicon oxide film located below the gate electrode 7 becomes a gate oxide film. To form the P-type region 10, first the extended drain region 11 is formed by ion implantation, impurity doping, and diffusion into the semiconductor substrate 15, and then boron is added to the extended drain region 11 in order to dope the P-type region 10 with impurities. After ion implantation and some heat treatment, the surface of the semiconductor substrate 15 is thermally oxidized. As a result, the segregation coefficient of boron between the silicon oxide film 8 and silicon differs, so the substrate 15
The boron concentration on the surface decreases to become N type, and the P type region becomes a structure embedded in the type extension drain region 11. By applying a reverse bias to this P type region 10 and the drain region 11, a depletion layer is spread between the extended drain region 11 and the semiconductor substrate 15 and between the P type region 10 and the extended drain region 11 in the extended drain region 11. Therefore, unlike the conventional structure, the extended drain region 11 can be depleted even if the i1 degree of the extended drain region 11 is increased. Therefore, the on-resistance between drain and source is
It can be made smaller than T. As a result, the train-to-source on-resistance per unit area can be 1775 to 17'6 compared to a MOSFET of conventional structure.

Effects of the Invention As described above, according to the present invention, a high voltage lateral MOSFET
chip size can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows an N-channel MOSF in one embodiment of the present invention.
A cross-sectional view of ET, Figure 2 is a conventional high-voltage horizontal MO5FET.
FIG. ■...Drain terminal, 2...P-type region electrode terminal in extension train, 3...Gate electron, 4
...... Source terminal, 5... Drain electrode, 6... Source electrode, 7... Gate electrode, 8... Silicon oxide film, 9... Drain contact region, 10... P-type region in extended drain region, 11... Extended drain region,
12... Anti-bunch through area, 13...
. . . Source region, 14 . . . Substrate contact region, 15 . . . Semiconductor substrate.

Claims (2)

[Claims] (1) An extended drain region of a second conductivity type that is in contact with the drain contact region is provided between a source region of a second conductivity type and a drain contact region provided on a semiconductor substrate of a first conductivity type, and an extended drain region of a second conductivity type is provided within the extended drain region. A semiconductor device in which an extended drain region and a reverse biased first conductivity type region are provided, the surface of the semiconductor substrate between the extended drain region and the source region is used as a channel region, and a gate electrode is provided on the channel region via a gate oxide film. Device. (2) The semiconductor device according to claim 1 is an N-channel MOSFET.
ET, and when forming a P-type region as a first conductivity type region reverse biased with this drain region in an N-type extended drain region, after forming the extended drain region,
Boron ion implantation is performed to form a type region, and then a silicon oxide film is formed to cover the surface, and the concentration on the surface of the P-type region is lowered to be lower than that on the surface of the extended drain region. A method of manufacturing a semiconductor device that can be confined within an extended drain region.