JPH0462975A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain hot carriers from being generated and to make a breakdown strength high by forming a high-concentration impurity diffusion layer which is extended up to a drain from one part of a low-concentration impurity diffusion region, of a second conductivity type, on the lower side of an oxide film, for element isolation use, on the side of the drain. CONSTITUTION:An n-type source 7, an n-type drain 8 and a low-concentration impurity diffusion region 5 at the lower side of an oxide film 4, for element isolation use, adjacent to a gate oxide film 2 are formed. After that, a high- concentration impurity diffusion region 6 which is extended up to the n-type drain 8 from one part of the low-concentration impurity diffusion region 5 adjacent to the n-type drain 8 is formed. The diffusion region 6 can be formed by implanting ions of an n-type dopant such as n<+>, As<+>, Pb<+> or the like after formation of the implantation mask 7 before the oxide film 4 is formed. Since the diffusion region 6 is formed, a potential gap by a concentration difference is relaxed, and it is possible to restrain hot carriers from being generated and to restrain the thermal destruction when an electric current is concentrated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an MO3 type semiconductor device.

[Summary of the invention]

The present invention forms a high concentration impurity diffusion region extending from a part of the low concentration impurity diffusion region under the element isolation oxide film adjacent to the drain to the drain, so compared to conventional high breakdown voltage semiconductor devices, This makes it possible to suppress the generation of true carriers.

[Conventional technology]

Conventionally, as shown in FIG. 2, an oxide film 4 for element isolation is provided near the surface of a semiconductor substrate 1, a gate oxide film 2 is provided in a region surrounded by the oxide film 4 for element isolation, and the gate oxide film 2 is A gate electrode 3 extending to a part of the element isolation oxide film 4 is provided through the gate oxide film 2, and a source 7 and a drain 8 adjacent to the outside in the channel direction of the element isolation oxide film 4 adjacent to the gate oxide film 2 are provided. By providing an n-type low concentration impurity diffusion region 5 under the element isolation oxide film adjacent to the gate oxide film 2 and the source 7 and drain 8, a high breakdown voltage semiconductor device was formed.

[Problem to be solved by the invention]

However, the conventional technology has problems such as an increase in substrate current due to the generation of true carriers and difficulty in increasing the withstand voltage.

[Means to solve the problem]

In order to solve the above-mentioned problems, in the present invention, a part of the second conductivity type low concentration impurity diffusion region under the drain side element isolation oxide film extends to the drain. A diffusion area was provided.

[Effect]

In the semiconductor device formed as described above, when carriers flow into the semiconductor substrate under the drain side element isolation oxide film, the potential gap is not concentrated in one place, so the generation of real carriers is suppressed, and the substrate Current can be reduced.

Therefore, it is possible to increase the voltage resistance of a high voltage transistor.

〔Example〕

An embodiment of the present invention will be described in detail based on the drawings. FIG. 1 shows a cross-sectional view in the channel direction of an embodiment of the high breakdown voltage MO3 type semiconductor device of the present invention. For example, P
An element-use oxide film 4 is formed near the surface of the type semiconductor substrate 1, a gate oxide film is formed in a region surrounded by the element isolation oxide film 4, and the element isolation oxide film 4 is formed through the gate oxide film 2.
2, and an n-type source 7 and an n-type drain 8 adjacent to the outside in the channel direction of the element isolation oxide film 4 adjacent to the gate oxide film 2 are formed. do. Here, an n-type source 7, an n-type drain 8
can be formed using the element isolation oxide film 4 as an implant mask, and dopants such as P', As', Pb', etc. are used at a dose of, for example, 5 x 10''/cJ.Next, n
type source 7, n type drain 8 and gate oxide film 2
A low concentration impurity diffusion region 5 is formed under the element isolation oxide film 4 adjacent to the n-type drain 8 , and a high concentration impurity diffusion region 5 extending from a part of the low concentration impurity diffusion region 5 adjacent to the n-type drain 8 to the n-type train 8 is formed. Impurity diffusion region 6 is formed. Here, the low concentration particle diffusion region is oxidized l! for element isolation. 4 can be formed in self-alignment by using the oxide mask used during formation as an ion implantation mask, and the dopants are P+As", Pb"
For example, from 2.0X10"/cJ to 8.0
The dose is approximately
It can be formed by ion implantation of a type dopant, for example 2. A dose of about OXl013/cJ is used.

After this, although not shown, an intermediate layer is formed, contact holes are selectively formed, a wiring layer is formed, and a protective film is formed to complete the process.

〔Effect of the invention〕

In the semiconductor device described in detail above, the high concentration impurity diffusion region is provided between the low concentration impurity diffusion region provided under the element isolation oxide film and the drain, so that the potential gap due to the concentration difference is alleviated. In addition to suppressing the generation of real carriers, it also suppresses thermal damage caused by current concentration.

[Brief explanation of drawings]

FIG. 1 is a sectional view in the channel direction of an MO3 type semiconductor device of the present invention, and FIG. 2 is a sectional view in the channel direction of a conventional MO3 type semiconductor device.・P-type semiconductor substrate ・Gate oxide film ・Oxide film for gate electrode element isolation ・N-type low-concentration impurity diffusion region ・N-type high-concentration impurity diffusion region ・N-type source ・N-type drain and above Applicant: Seiko Electronic Industries, Ltd. Company agent Patent attorney Keinosuke Hayashi

Claims (1)

[Claims] An oxide film for element isolation is provided near the surface of a semiconductor substrate of a first conductivity type, a gate oxide film is provided in a region surrounded by the oxide film for element isolation, and a gate oxide film is provided on the oxide film for element isolation via the gate oxide film. a second conductivity type source and a second conductivity type drain adjacent to the outer side of the element isolation oxide film in the channel direction of the element isolation oxide film adjacent to the gate oxide film; A low concentration impurity diffusion region of a second conductivity type is provided under the element isolation oxide film adjacent to the gate oxide film, the source of the second conductivity type, and the drain of the second conductivity type, and A semiconductor device comprising a second conductivity type high concentration impurity diffusion region extending from a part of the low concentration impurity diffusion region adjacent to the drain of the mold to the drain.