JPH04176165A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [v! A] Related to semiconductor devices, especially SoI (Silicon)
On 1nsulator) Haki'f2's MOS (M
etal Oxide 5eliconductor
) Regarding transistors, sorWi made CMO3)
The purpose of the present invention is to provide a semiconductor device in which different back biases can be applied to a p-channel MOS transistor and an n-channel MOS transistor in a transistor. In a semiconductor device in which a field effect transistor and an 11-channel field effect transistor are formed, the insulating layer of the semiconductor substrate below at least one of the P channel field effect transistor and the n channel field effect transistor is formed. A back bias impurity region is provided at the interface.

[Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
I (Silicon On In5ulator)
Structure of MO3 (Metal Oxide 5enico
)) relates to a transistor and its manufacturing method.

[Prior art] Conventional bulk type CMOS (Compleientar
y MO8) transistor is shown in FIG.

A feed oxide film 32 is formed on a P-type silicon substrate 31'' to separate device regions. Further, an n-type well region 33 is formed in this element region. On the surface of this n-type well region 33, P4 type source and drain regions 34 are formed facing each other, and these P+ type source and drain regions 34 are formed facing each other.
An n-type channel region 35 is formed between drain regions 34 . Further, n+ type source and drain regions 36 are formed facing each other on the surface of the P type silicon substrate 31 in the element region adjacent to the n type well region 33, and these n4
A P-type channel region 37 is formed between the P-type source and drain regions 36 .

Gate electrodes 40 and 41 made of polysilicon are formed on the n-type channel region 35 and the p-type channel region 37 through oxide films 38 and 39 to the gate 1, respectively.
is provided. In this way, P-channel MO3
+- transistor 42 and n-channel MOS transistor 4
3 is formed and CMO3? - It constitutes a run sister.

In such a bulk type CMO3I transistor, a substrate voltage of, for example, ■1l-Q to -3V (pol l-) is normally applied to the p-type silicon substrate 31 as a back bias, and the n-type well region 33 is The same voltage as the power supply voltage, for example, 11-5v is applied.

[Problems to be Solved by the Invention] However, it is difficult to apply such a back bias to a 5OII CMOS transistor.

Conventional SOI'! The fourth CMOS transistor manufactured by fJ
As shown in the figure.

That is, a silicon oxide film 52 is formed on a p-type silicon substrate 51.
Silicon Thin Jl via! 53 is formed. This silicon thin film 53 is separated into device regions by a field oxide film 54. In the silicon thin film 53 in this element region, p4 type source and drain regions 55 and an n type channel region 56 sandwiched between these are formed.

Furthermore, the silicon thin film 53 in the adjacent element region has n+
Source and drain regions 57 and a P type channel region 58 sandwiched between these P+ type source and drain regions 57 are formed.

The n-type channel region 56 and the p-type channel region 58 are connected to gate electrodes made of a polysilicon layer through gate oxide WA59.60, respectively. 61.6
2 is formed. In this way, the P-channel MO
3) Transistor 3 and n-channel MoS transistor 6
4 is formed and constitutes a 0MO3) transistor.

In such a conventional 5OII CMO8I-transistor, when the silicon thin film 53 is made thinner as transistors become more sophisticated and denser, the P+ type source,
Between the drain regions 55 and the n1 type source and drain regions 5
There is a problem in that the breakdown voltage between the terminals 7 and 7 decreases.

To solve this problem, it is necessary to apply a bias from the back side. Then, F) channel MO with P+ type source, drain region 55, n type channel region 56 and P type silicon substrate 51 as gate electrodes is formed.
An S transistor is formed, and conduction is established between the P+ type source and drain regions 55. That is, P channel MO8l
~There is a problem in that the transistor 3 becomes conductive and cannot operate as a transistor.

Therefore, to solve these problems, P-channel MO
3) It is necessary to apply a bias to each of the transistors 3 and n-channel MO8 transistors 4 from the back. However, from the SOJ structure, p/
It is extremely difficult to form n different electrodes on the back substrate.

Therefore, the present invention proposes a P-channel MO8) transistor and an n-channel MMOS transistor in an SOI structure CMOS transistor.
An object of the present invention is to provide a semiconductor device that can apply a different back bias to an OS transistor, and a method for manufacturing the same.

[Means for Solving the Problems] The above object is to form a P-channel field effect transistor and a semiconductor thin film provided on a semiconductor substrate via an insulating layer.
In a semiconductor device in which a channel field effect transistor is formed, a back bias layer is provided at an interface with the insulating layer of the semiconductor substrate below at least one of the P channel field effect transistor and the n channel field effect transistor. This is achieved by a semiconductor device characterized in that an impurity region is provided.

The above object also includes a step of forming a mark at a predetermined position on a first semiconductor substrate as a support substrate, and a step of forming a mark at a predetermined position on the semiconductor substrate determined by using the mark for alignment. forming an impurity region for back bias by adding , bonding a second semiconductor substrate to the surface of the first semiconductor substrate via an insulating layer, and polishing the back surface of the second semiconductor substrate. forming a semiconductor thin film on the first semiconductor substrate via the insulating layer; and using the mark for alignment, applying a P-channel electric field to the semiconductor thin film above the back bias impurity region. A first transistor, either an effect transistor or an n-channel field effect transistor, is formed, and a transistor different from the first transistor is formed in the semiconductor thin film above the first semiconductor substrate in a region other than the back bias impurity region. This is achieved by a method for manufacturing a semiconductor device, which is characterized by comprising a step of forming a channel-type second transistor.

Further, a step of forming a mark at a predetermined position on a first semiconductor substrate serving as a support substrate, and a step of forming a mark at a predetermined position on the semiconductor substrate determined using the mark for alignment,
a step of adding different types of impurities to form first and second back bias impurity regions; and a step of bonding a second semiconductor substrate to the surface of the first semiconductor substrate via an insulating layer. , polishing the back surface of the second semiconductor substrate to form a semiconductor thin film on the first semiconductor substrate via the insulating layer; and polishing the first back surface using the mark for alignment. forming a P-channel field effect transistor in the semiconductor thin film above the bias impurity region, and forming an n-channel field effect transistor in the semiconductor thin film above the second back bias impurity region. This is achieved by a method of manufacturing a semiconductor device.

[Function] The present invention provides a back bias impurity region in the semiconductor substrate below either or both of the P-channel field effect transistor and the n-channel field effect transistor.・
Different back biases can be applied to the transistor and the n-channel field effect transistor.

In addition, by controlling this back bias to prevent a drop in the breakdown voltage between the source and drain, it is possible to further reduce the thickness of the semiconductor thin film and the insulating layer between the semiconductor thin film and the semiconductor substrate. Therefore, it is possible to shorten the channel of the field effect transistor, that is, to realize higher speed and higher density.

In addition, in this method of manufacturing a semiconductor device, marks for alignment are formed on the surface of a silicon semiconductor substrate before bonding together with an impurity region for back bias, and after forming an SOI JM structure by a bonding method, the marks are formed. Utilizing this for alignment, a predetermined MOS transistor can be accurately and easily formed in the semiconductor thin film above the back bias impurity region.

[Example] = 12 - Hereinafter, the present invention will be specifically described based on an example that maintains the present invention.

FIG. 1 shows a 0MO8 made of 5OIi according to an embodiment of the present invention.
) is a sectional view showing a transistor.

An n + -type back bias impurity region 12 is formed at a predetermined position on the surface of a P-type silicon substrate 11 . Then, a silicon thin H
14a is formed. This silicon thin IWA 1.
4a is isolated by a field oxide film 15.

In the element region made of the silicon thin film 1.4a above the n+ type back bias impurity region 12, P4 type source and drain regions 16 are formed facing each other, and are sandwiched between these p+ type source and drain regions 16. An n-type channel region 17 is formed therein.

Further, in the element region adjacent to this element region, an n4 type source and train region 18 and one p type channel region are similarly formed.

= 13 - Gate electrodes 22 and 23 made of a polysilicon layer are formed above the n-type channel region J7 and one p-type channel region, respectively, with gate oxide films 20 and 21 interposed therebetween. In this way, a P channel MO8) transistor 24 and an n channel MOS transistor 25 are formed.

As described above, according to the present embodiment, a p-channel MO3 is formed above the n-type back bias impurity region 12 provided on the surface of the p-type silicon substrate 11 through silicon oxide [1, 3].
) A p-type silicon substrate 11 on which a transistor 24 is formed and in which an n+ type back bias impurity region is not provided.
Above, an n-channel MOS is connected via a silicon oxide film 13.
A transistor 25 is formed and constitutes a CMOS 1-transistor.

Therefore, by applying different voltages to the P-type silicon substrate 11 and the r14-type back bias impurity region 12, 1) different desired back biases are applied to the channel MO3I-transistor 24 and the n-channel MOS transistor 25, respectively. IA-- can be connected to these p-channel MO8I ~ transistor 2
0M consisting of 4 and n-channel MOS transistors 25
O8) The transistor can be operated properly.

In addition, since it is possible to prevent the breakdown voltage between the source and the drain from decreasing by controlling the back bias at this time, it is possible to realize thinning of the silicon thin film 14a and the silicon oxide film 13, which are the element regions. Therefore, it is possible to shorten the channel of the Mo8) transistor, that is, to achieve higher speed and higher density.

In the above embodiment, an n+ type back bias impurity region was formed on the silicon substrate surface below the p channel MOS transistor, but conversely, a p+ type back bias impurity region was formed on the silicon substrate surface below the n channel MOS transistor. may be formed.

Alternatively, n+ type and P4 type back bias impurity regions may be formed on the silicon substrate surface below the P channel MOS transistor and the n channel MOS transistor, respectively.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described using the process diagram in FIG. 2.

Marks 26 as alignment marks are formed at predetermined positions on the surface of the P-type silicon substrate 11 (see FIG. 2(a)). Subsequently, after forming silicon oxide M27 on the entire surface,
A window is selectively opened at the predetermined position aligned using the eraser 26. Then, ions are implanted through the window opened in this silicon oxide film 27, and the P-type silicon substrate 11 is
A 04-type back bias impurity region 12 is formed on the surface (see FIG. 2(b)).

Next, after removing the silicon oxide film 27, a silicon substrate 14 with a silicon oxide film 13 formed on its surface is bonded to the surface of the P-type silicon substrate 11 on which the n1-type back bias impurity region 12 is not formed (FIG. 2). (see (c)). Subsequently, the back surface of the silicon substrate 14 is polished and etched to form a thin film, thereby forming a silicon thin film 14a. In this way, an SOI structure is formed in which the silicon thin film 14a is formed on the P-type silicon substrate 11'' with the silicon oxide film 13 interposed therebetween (see FIG. 2(d)).

Next, the silicon thin film 14a is selectively oxidized using the groove 26 as a positioning mark to form a field oxide film [5].
is formed to separate the element regions.

At this time, a predetermined element region is formed above the n+ type back bias impurity region 12.

Then, in this n4 type back bias impurity region 12'' element region, a P+ type source, a drain region 16, an n type channel region 17, a gate oxide film 20, and a gate electrode 2.
At the same time, a P-channel MOS transistor 24 consisting of an Refer to FIG. 2(e) to form an n-channel Mo transistor 25 consisting of an oxide film 2 and a gate I-electrode 23).

Further, although not shown, an electrode connected to the n1 type back bias impurity region 12 is formed.

As described above, according to the manufacturing method of this embodiment, the 04-type back bias impurity region 12 is formed on the surface of the P-type silicon substrate IJ before bonding, and the eraser 26 is formed as a positioning mark. After that, alignment can be easily performed using the eraser 26, and therefore the desired P-channel MO8+- transistor 2 is placed at an accurate position above the n+ type back bias impurity region 12.
4 can be easily formed.

In the above embodiment, the eraser 26 was used as the alignment mark formed on the P-type silicon substrate 11.
The mark is not limited to this, and may be formed by patterning a high melting point metal such as a chromium-based metal or tungsten, as long as it can be used as an alignment mark via the silicon oxide JIi 13 and the silicon thin film 14a.

In addition, during bonding, after removing the silicon oxide film 27 on the P-type silicon substrate 11, silicon oxide 11!13 was formed on the surface of the silicon substrate 14 and bonding was performed. Bonding may be performed by forming an oxide film.

Furthermore, in the above manufacturing method, as shown in FIG. 2(b), an n+ type back bias impurity region 12 is formed on the surface of the p type silicon substrate 11;
By forming P+ type back bias impurity regions at predetermined positions, n'' type and p44 type back bias impurity regions are formed on the silicon substrate surface below the p channel MO transistor 24 and the n channel transistor 25, respectively. can be formed.

Alternatively, when an n-type silicon substrate is used, contrary to this embodiment, a P+ type back bias impurity region can be formed on the surface of the silicon substrate below the n-channel O3) transistor.

[Effects of the Invention] As described above, the present invention provides a semiconductor device in which a P-channel field effect transistor and an n-channel field effect transistor are formed in a semiconductor thin film provided on a semiconductor substrate with an insulating layer interposed therebetween. , P-channel field effect I
- An n-channel field-effect transistor and an n-channel field-effect transistor are different because a back bias impurity region is provided at the semiconductor substrate interface below at least one of the transistors and the n-channel field-effect transistor. A back bias can be applied.

This makes it possible to prevent a drop in the break-down voltage between the source and the train, thereby realizing further thinning of the semiconductor thin film and further thinning of the insulating layer between the semiconductor thin film and the semiconductor substrate. It is possible to achieve higher speed and higher density.

In addition, in this method of manufacturing a semiconductor device, alignment marks are formed on the surface of the silicon semiconductor substrate before bonding together with a back bias impurity region, so that the marks can be used after forming a 5OIi structure by bonding. A predetermined 1 transistor can be accurately and easily formed in one semiconductor thin film by forming a back bias impurity region.

[Brief explanation of drawings]

FIG. 1 shows SOT'! according to an embodiment of the present invention. M made by fJ
FIG. 2 is a process diagram illustrating a method of manufacturing the MOS transistor shown in FIG. 1. FIGS. 3 and 4 are sectional views showing a conventional MOS transistor. In the figure, 11.31.51... p-type silicon substrate, 12
. . . n4 type back bias impurity region, 13.
52...Silicon oxide film, 14...Silicon substrate, 14a, 53...Silicon thin film, 15.32.
54...Field oxide film, 16.34.55
......p+ type source, drain region, 17, 35, 56......n type channel region, 18
．． 36.57...N+ type source, drain region, 19.38.58...P type channel region, 20
．． 21.38.39.59.60...Gate oxide film, 22.23.40.41.61.62...Gate electrode, 24.52.63... P channel MO3) transistor, 25.53.64...0 channel MO8I~ transistor, 26...groove, 27...silicon oxide film, 33... n-type well region. Applicant Fujitsu Ltd. Company Agent
Patent attorney Yoshi Kitano

Claims (1)

[Claims] 1. A semiconductor device in which a p-channel field effect transistor and an n-channel field effect transistor are formed in a semiconductor thin film provided on a semiconductor substrate with an insulating layer interposed therebetween, wherein the p-channel field effect transistor or A semiconductor device characterized in that a back bias impurity region is provided at an interface with the insulating layer of the semiconductor substrate below at least one of the n-channel field effect transistors. 2. Forming a mark at a predetermined position on a first semiconductor substrate serving as a supporting substrate; and adding an impurity to a predetermined position on the semiconductor substrate determined using the mark for alignment. forming a back bias impurity region; bonding a second semiconductor substrate to the surface of the first semiconductor substrate via an insulating layer; polishing the back surface of the second semiconductor substrate; forming a semiconductor thin film on the semiconductor substrate of No. 1 through the insulating layer; using the mark for alignment, forming a p-channel field effect transistor or an n-channel field effect transistor on the semiconductor thin film above the back bias impurity region; A first transistor of one of the channel field effect transistors is formed, and a first transistor of a channel type different from that of the first transistor is formed in the semiconductor thin film above the first semiconductor substrate in a region other than the back bias impurity region. 2. A method for manufacturing a semiconductor device, comprising: forming a transistor. 3. Forming a mark at a predetermined position on a first semiconductor substrate serving as a supporting substrate; and applying different types of impurities at predetermined positions on the semiconductor substrate determined using the mark for alignment. a step of doping to form first and second back bias impurity regions; a step of laminating a second semiconductor substrate on the surface of the first semiconductor substrate via an insulating layer; polishing the back surface of the substrate to form a semiconductor thin film on the first semiconductor substrate via the insulating layer; Manufacturing a semiconductor device, comprising: forming a p-channel field effect transistor in the semiconductor thin film, and forming an n-channel field effect transistor in the semiconductor thin film above the second back bias impurity region. Method.