JPH01162362A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sped up a CMOS element by a method wherein an n-channel FET with a channel region in a plane (100) is built in p-type silicon and a p-channel FET with a channel region in a plane (100) is formed in n-type silicon. CONSTITUTION:A p-Si substrate 11 of a plane index (100) and an n-Si substrate 12 of a plane index (100), mounted with approximately 3000Angstrom thick SiO2 layers 11A and 12A, are put together on their SiO2 surfaces and placed on a carbon heater 13. The substrates 11 and 12 are heated and then exposed to a pulse voltage for adhesion. The substrate 12 is thinned out by lapping and etching. The substrate 12 is subjected to another etching after which only an island- geometry element-forming n-Si region 12B is retained and the SiO2 layer 12A is exposed. A p-channel FET is built on the n-Si region 12B, the SiO2 layers 12A ad 11A are locally removed for the exposure of the substrate 11 for the construction of an n-channel FET thereon. This design enhances a CMOS element in its operating speed.

Description

[Detailed description of the invention] 〔overview〕 Regarding a method for manufacturing high-speed CMOS devices.

The purpose is to enable faster and smaller CMOS devices, and to prevent failures due to latch-up.

A step of forming an n-type silicon substrate with a planar index (110) on a p-type silicon (Si) substrate with a planar index (100) via an insulating layer, and thinning one of the substrates.

A process of patterning to form an island-shaped silicon layer on the insulating layer, forming an n-channel FET with a channel region in the (100) plane in p-type silicon, and forming a channel region in (100) plane in p-type silicon. 110) A step of forming an in-plane p-channel FET.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, particularly for high-speed CMO.
The present invention relates to a method for manufacturing an S element.

The CMOS element is an n-channel MO3FBT on the same chip.
It is equipped with a p-channel MO5FET to form a complementary circuit, and is widely used as a low-power element in logic and integrated circuits.

[Conventional technology]

In order to operate the device at high speed, it is necessary to increase carrier mobility.

Generally, carrier mobility depends on the plane index of the crystal.

For example, the field effect mobility of carriers in Si (cm2
The surface index dependence of V-'5ec-' is as follows.

Plane index Electron Hole (110) < 400 190- When using a (100) plane Si substrate used for boat fishing, the mobility of holes on this plane is 1/3 that of electrons,
In order to make the current capacity equivalent to that of electrons, it is necessary to triple the channel width of the FET, which impedes miniaturization of the device.

Therefore, n-channel MO5PET using electrons as carriers
p with the channel in the (100) plane and holes as carriers.
A possible method is to fabricate the channel MO3FET channel in the (110) plane.

An example of a CMO5 element in which channels are formed on different surfaces in this way will be described next.

1) 1986 VLSI Seventh Bosium Proceedings p17~
.

Figure 2 shows C with channels formed on different surfaces according to the conventional example.
FIG. 3 is a cross-sectional view of an MO3 element.

In the figure, (100) plane n-type St (n-3i)
A p-type well 2 is formed in the substrate 1, and an n-channel F
Form ET. 3 is an oxide film forming a gate insulating layer and an isolation insulating layer, 4 is a gate electrode, and 5 and 6 are n-type source/drain regions.

On the other hand, a vertical trench is dug in the n-3i substrate 1 so that the (110) plane is exposed on the side surface, and an n-channel FET is formed so that a channel region is formed on this side surface. 3 is an oxide film forming the gate insulating layer and the isolation insulating layer; 7 is the gate electrode; 8
．． 9 is a p-type source/drain region.

[Point i while the invention is trying to solve the problem]

In the conventional CMO3 device in which channels are formed on different surfaces, an n
To form the channel region of the channel FET.

There is a drawback that the source/drain region cannot be formed in self-alignment with the gate electrode.

There is a risk that a failure may occur due to launch-up (a conduction phenomenon between an n-channel FET and a p-channel FBT due to the Sirisk effect) peculiar to a CMO5 element formed in bulk Si.

[Means for solving problems]

The solution to the above problem is to form an n-type silicon substrate with a dihedral index (110) on a p-type silicon substrate with a dihedral index (100) via an insulating layer, and to form one of the substrates with a thin film. forming an n-channel FET with a channel region in the (100) plane in the n-type silicon; This is achieved by a method of manufacturing a semiconductor device characterized by comprising the step of forming an n-channel FET having a (110) plane.

[Effect]

The present invention provides an n-channel FET on the (100) plane, (
We formed an n-channel FET on the 110) plane to increase the carrier mobility and increase the speed of the CMO5 device.
Since both 1fETs can be formed on the same plane by self-alignment, miniaturization is possible.

For this purpose, it is necessary to form a semiconductor layer having an arbitrary surface index different from that of the substrate on the substrate, and a bonding method proposed by the present applicant was used for this purpose.

Also, since the three PUTs are separated via an insulating layer,
Failures caused by launch amplifiers can be prevented.

〔Example〕

Figure 1 (11-(3) indicates an embodiment of the present invention)
It is a sectional view of an MO5 element.

In Figure 1 (1), one surface has a thickness of about 3,000 people 5i
A p-5i substrate 11 with a plane index of (100) on which an O7 layer LIA is formed.

Each Si
Stack the O□ sides together and place on the carbon heater 13.
The substrates are heated to 800 to 900° C. by the power source 14, and a pulse voltage of 30 to 300 V is applied between the two substrates from the pulse power source 15 to bond the two substrates together 2'. This method was proposed by the applicant.

2) Proceedings of the 34th Japan Society of Applied Physics, Spring 1987 p544.30a-8-1 Next, the n-5i substrate 12 was reduced by about 5000 layers by lapping and etching, leaving an island-like element formation area. Remove other areas by etching and remove the underlying 5i
(Exposing the h layer 12A.

In FIG. 1(2), an n-channel F
ET is formed, sio, JW128, and IIA are partially removed to expose the p-St substrate 11, where an n-channel F is formed.
Form ET.

Figure 1 (3) is a cross-sectional view of the completed CMO5 element.
17 is an oxide film constituting a gate insulating layer, etc.; 17 is a gate electrode; and 18 and 19 are n-type source/drain regions, which constitute an n-channel FET.

On the other hand, 20 is an oxide film forming a gate insulating layer and the like.

21 is a gate electrode, 22 and 23 are p-type source and drain regions, which constitute an n-channel FET.

Phosphorsilicate glass (PSG) is used as a cover insulating layer on the entire surface of the substrate.
) layer 24 is grown and contact holes are formed to form each electrode 25.

〔Effect of the invention〕

As explained above, according to the present invention, each of the nine FETs is formed by selecting a planar index with a large carrier mobility, thereby making it possible to increase the speed.

Since both FETs are formed on the same plane, the source and drain regions can be formed in self-alignment with the gate electrode, making it possible to miniaturize the device.

Also, the nine FETs are separated by an insulating layer.

Failures due to lagging can be prevented.

[Brief explanation of the drawing]

FIG. 1 (11 to (3)) is a C diagram explaining one embodiment of the present invention.
A cross-sectional view of an MO5 element. Figure 2 shows C with channels formed on different surfaces according to the conventional example.
It is a sectional view of an MO5 element. In fig. 11 is a p-5i substrate with a surface index (100). 11A has 5402 layers. 12 is an n-5t substrate with a plane index (110). 12A is a SiO□ layer. 12B is an island-shaped n-5i layer. 13 is a carbon heater. 14 is the power supply. 15 is a pulse power supply. 16 is an oxide film forming a gate insulating layer and the like. 17 is a gate electrode. 18 and 19 are n-type source/drain regions. 20 is an oxide film forming a gate insulating layer and the like. 21 is a gate electrode. 22 and 23 are p-type source/drain regions. 24 is the insulating layer of the cover, which is the PSG layer. 25 is an m-plane view of the conventional example with each electrode Z and P-phenol.

Claims (1)

[Claims] A step of forming an n-type silicon substrate with a planar index (110) on a p-type silicon (Si) substrate with a planar index (100) via an insulating layer, and one of the substrates described above. forming an island-shaped silicon layer on the insulating layer by thinning and patterning the insulating layer; forming an n-channel FET with a channel region in the (100) plane in p-type silicon; Channel area (
110) A method for manufacturing a semiconductor device, comprising the step of forming an in-plane p-channel FET.