JPH05145073A - Complementary thin film transistor - Google Patents

Abstract

(57) [Summary] (Modified) [Structure] A first conductive type thin film transistor having a forward stagger structure and a second conductive type thin film transistor having an inverted stagger type, and the source and drain regions 107 of the first conductive type thin film transistor. And the source and drain regions 112 of the second conductive type thin film transistor are formed of different layers. [Effects] With the above structure, miniaturization and high integration can be achieved, the best characteristics of N-type and P-type thin film transistors can be obtained, and a high-performance complementary thin film transistor can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary thin film transistor which is effectively applied to liquid crystal display devices and semiconductor integrated circuits.

[0002]

2. Description of the Related Art FIGS. 6 (a) to 6 (d) are views for explaining an example of a complementary thin film transistor according to the prior art, with reference to sectional views of elements in respective manufacturing steps. First, as shown in FIG. 6A, a semiconductor layer 602 is laminated on an insulating substrate 601,
Insulating thin film layer 6 which becomes the gate insulating film after patterning
03, a semiconductor layer is laminated, and patterned into a desired shape to form a gate electrode 604 of the first conductivity type thin film transistor and a gate electrode 6 of the second conductivity type thin film transistor.
05. After that, as shown in FIG. 6B, a portion to be the second conductivity type thin film transistor is covered with a resist 606 and a first conductivity type impurity 607 is introduced, so that the source and drain regions 608 of the first conductivity type thin film transistor and the active region are activated. Region 609 is formed. Then, the resist 6
When 06 is removed, the portion of the first conductivity type thin film transistor is covered with the resist 610 again, and the second conductivity type impurity 611 is introduced, the source and drain regions 612 of the second conductivity type thin film transistor and the active region 613 are formed. FIG. 6C is obtained. Then, the resist 610 is removed, an interlayer insulating film 614 is laminated, and the contact hole 61 is formed.
After forming holes 5, the source and drain electrode terminals 616 are formed to form a complementary thin film transistor as shown in FIG.

[0003]

In recent years, with the development of semiconductor integrated circuits, the number of layers has further increased.
In the conventional semiconductor memory, N-type and P-type M are formed on the conductor substrate
The OS transistor was formed to form the complementary MOS transistor. However, as the number of layers is increased, a technique for making the transistor multilayer to reduce the area and miniaturize is being studied. Also, with the development of liquid crystal display devices,
There is also a strong demand for miniaturization and high integration of a complementary thin film transistor which is a peripheral driving circuit of a liquid crystal display device. However, in the structure of the complementary thin film transistor described in the above-mentioned conventional technique, a space is required between the source and drain regions of the N-type thin film transistor and the P-type thin film transistor in consideration of the accuracy of mask alignment. However, miniaturization and high integration were difficult. Further, in the above-mentioned conventional complementary thin film transistor, when connecting the N-type thin film transistor and the P-type thin film transistor, it is necessary to connect them by using the wiring layer, and the space of the opening for this is the N-type thin film transistor. It is necessary for both the P-type thin film transistor and the P-type thin film transistor, which is also a problem for miniaturization and high integration. Further, the characteristics of the thin film transistor can be controlled by the film thickness of the active region and the film thickness of the gate insulating film.
Characteristics differ between the p-type thin film transistor and the p-type thin film transistor. However, in the complementary thin film transistor according to the related art, since the active regions and the gate insulating film of the N-type and P-type thin film transistors are simultaneously formed,
It has been difficult to obtain optimum values for both the p-type and p-type thin film transistors to have high characteristics. Therefore, it has been difficult to achieve high speed and high performance in a complementary thin film transistor in which these are combined.

The present invention solves the problem of the complementary type thin film transistor as described above. The purpose of the present invention is to enable miniaturization and high integration, and the N type and P type thin film transistors respectively have high performance. , And to provide a high-performance complementary thin film transistor formed by them.

[0005]

In a complementary thin film transistor including a first conductivity type thin film transistor and a second conductivity type thin film transistor on an insulating substrate or an insulating thin film, a first conductivity type of a forward stagger structure is provided. It is characterized by comprising a thin film transistor and an inverted stagger type second conductivity type thin film transistor.

The source and drain regions of the first conductivity type thin film transistor and the source and drain regions of the second conductivity type thin film transistor are formed of different layers.

The source and drain regions of the first conductivity type thin film transistor and the source and drain regions of the second conductivity type thin film transistor are directly connected.

Alternatively, the source or drain region of the first conductive type thin film transistor constitutes a gate electrode of the second conductive type thin film transistor, and the second conductive type gate electrode of the second conductive type thin film transistor. It is characterized in that it constitutes a source or drain region.

[0009]

According to the complementary thin film transistor of the present invention, the first conductivity type thin film transistor is a forward stagger type,
Since the conductive type thin film transistor is an inverted staggered type, and the source and drain regions of the first conductive type thin film transistor and the source and drain regions of the second conductive type thin film transistor are formed in different layers, miniaturization is possible. It is possible and high integration can be achieved. In addition, since at least one of the film thickness of the active region and the film thickness of the gate insulating film of the first-conductivity-type thin film transistor and the second-conductivity-type thin film transistor is formed of different layers, the optimum conditions for each thin film transistor are Can be used. Thereby, the performance of the complementary thin film transistor using them can be improved. Further, the source and drain regions of the first-conductivity-type thin film transistor and the source and drain regions of the second-conductivity-type thin film transistor can be directly connected to each other, which enables further miniaturization. Alternatively, the first
If the conductive type source or drain region constitutes the second conductive type gate electrode and the first conductive type gate electrode constitutes the second conductive type source or drain region, the process is also simple. The area of the formed complementary thin film transistor can be made very small.

[0010]

(Embodiment 1) One of the embodiments of the present invention will be described in detail with reference to sectional views of elements in each manufacturing process. First, as shown in FIG. 1A, a first semiconductor layer is stacked on an insulating substrate 101, patterned, and then a first semiconductor layer is formed.
An insulating film layer 102 serving as a gate insulating film of a conductive type thin film transistor is stacked, and then a second semiconductor layer is stacked and patterned into a desired shape to form gate electrodes 103 of the first conductive type thin film transistor and the second conductive type thin film transistor. 104 are formed respectively, and impurity ions 105 of the first conductivity type are introduced by an ion implantation method such as an ion ion plantation method or an ion doping method to form the source and drain regions 106 of the first conductivity type thin film transistor.
And an active region 107 is formed. The second semiconductor layer to be the gate electrodes 103 and 104 may be a semiconductor layer doped with a high concentration of impurities or may not contain impurities.
The gate insulating film 102 of the first conductive type thin film transistor is formed on the gate insulating film 102 by a thermal oxidation method, a thermal nitriding method, or an atmospheric pressure CVD method.
Method, low pressure CVD method, plasma CVD method, ECR plasma CVD method, sputtering method, or the like, and an insulating thin film formed by a silicon dioxide film, a silicon nitride film, or a combination thereof is used. Then, an insulating thin film to be the gate insulating film 108 of the second conductivity type thin film transistor is laminated, and the first contact hole 1 is formed on the source or drain region 106 of the first conductivity type thin film transistor.
09 is opened, a semiconductor layer is laminated on the entire surface, and then a resist 110 is applied on the entire surface. Then, unnecessary portions are removed, and the remaining portion of the resist 110 is used as a mask to form a second mask.
The conductive type impurity ions 111 are introduced by the same method as that used to introduce the first conductive type impurity ions, and the source / drain region 112 and the active region 113 of the second conductive type thin film transistor are formed. This state is shown in FIG. Then, after removing the resist 110 and patterning the third semiconductor layer, an interlayer insulating film 114 is laminated, a second contact hole 115 is opened, and source and drain electrode terminals 116 are formed. 2C, the complementary thin film transistor is completed.

FIG. 2A shows a circuit diagram when an inverter circuit is formed by using the complementary thin film transistor formed in the first embodiment of the present invention. Figure 2 (b)
[Fig. 3] is a top view of the elements of the inverter circuit. 201 is P
Type thin film transistor, 202 is an N type thin film transistor,
Reference numeral 203 is an input line, 204 is an output line, 205 is a power supply voltage line, and 206 is a ground line.

(Embodiment 2) Another embodiment of the complementary thin film transistor of the present invention will be described with reference to FIGS.
First, as shown in FIG. 3A, after a semiconductor layer is laminated on an insulating substrate or an insulating thin film 301 and patterned into a desired shape, a resist 302 is applied and exposed, and the remaining resist is used as a mask. A first conductivity type impurity ion 303 is introduced to form a source / drain region 304 and an active region 305 of the first conductivity type thin film transistor.
Then, after removing the resist 302, an insulating thin film 306 to be a gate insulating film of the first conductive type thin film transistor and the second conductive type thin film transistor and a semiconductor layer are sequentially laminated, and a resist 307 is applied again and exposed, and this is masked. As the second conductivity type impurity ions 308, the source and drain regions 309 of the second conductivity type thin film transistor are introduced.
And an active region 310 is formed. This state is shown in FIG. After that, the resist 307 is removed, an interlayer insulating film 311 is laminated, contact holes 312 are opened, and then source and drain electrode terminals 313 are formed.
As (c), a complementary thin film transistor is completed.

In the second embodiment of the present invention, either the source or drain region 309 of the second conductivity type thin film transistor constitutes the gate electrode of the first conductivity type thin film transistor, and the source or drain of the first conductivity type thin film transistor is formed. Either one of the drain regions 304 constitutes the gate electrode of the second conductivity type thin film transistor. Further, in this embodiment, the source / drain region 304 and the active region 305 of the first conductivity type thin film transistor are
Although it was formed before forming the gate insulating film 306, it may be formed using a resist or the like as a mask after forming the gate insulating film.

The complementary thin film transistor formed in the second embodiment of the present invention can be applied to, for example, a complete CMOS type static RAM as shown in FIG. In FIG. 4, reference numerals 401 and 402 denote P-type thin film transistors serving as load elements, and 403 and 40.
Reference numeral 4 represents an N-type thin film transistor that serves as a driver transistor, 405 and 406 represent N-type thin film transistors that serve as transfer transistors, 407 is a word line, 408 is a power supply voltage line, 409 is a ground line, and 410 is a data line. .. The transfer transistors 405 and 406 can also be composed of MOS transistors formed on a conductor substrate. The P-type thin film transistor 401 and the N-type thin film transistor 404, and the P-type thin film transistor 402 and 402 are formed by the complementary thin film transistor described in the second embodiment of the present invention.
03 N-type thin film transistor,
The complete CMOS static RAM shown in FIG. 4 can be constructed.

(Embodiment 3) Another embodiment of the complementary thin film transistor of the present invention will be described with reference to FIGS.
First, as shown in FIG. 5A, a first semiconductor layer added with a high concentration impurity is stacked on an insulating substrate 501 and patterned into a desired shape to form a gate electrode 502 of a first conductivity type thin film transistor. .. In this embodiment, a semiconductor layer doped with a high concentration of impurities is used as the gate electrode of the first conductivity type thin film transistor, but a semiconductor layer containing no impurities is doped with impurities by an ion implantation method. May be. Then, an insulating thin film 503 to be a gate insulating film of the first conductivity type thin film transistor and a second semiconductor layer 504 are sequentially stacked, and after patterning the semiconductor layer 504, an insulating thin film to be a gate insulating film of the second conductivity type thin film transistor. 505, a third semiconductor layer is stacked and patterned to form a gate electrode 506 of the first conductivity type thin film transistor and a mask 507 covering the second conductivity type thin film transistor, and impurity ions of the first conductivity type. 508 is introduced by an ion implantation method such as an ion implantation method or an ion doping method to form a source / drain region 509 and an active region 510 of the first conductivity type thin film transistor. This state is shown in FIG. Then, the semiconductor layer 5 covering the second conductive type thin film transistor
07 is removed, and the first conductive type thin film transistor portion and the active region portion of the second conductive type thin film transistor are covered with a resist 5
11 and introducing impurity ions 512 of the second conductivity type by a method similar to the above method to form source and drain regions 513 and active regions 514 of the second conductivity type thin film transistor. ). afterwards,
The resist 511 is removed, the interlayer insulating film 515 is laminated, the contact hole 516 is opened, and the source and drain electrode terminals 517 are formed. As shown in FIG. 5D, a complementary thin film transistor is completed. ..

In the first to third embodiments of the present invention, the insulating substrate is used as the substrate, but the complementary thin film transistor may be formed on the insulating thin film instead. The complementary thin film transistors formed in the first to third embodiments of the present invention are used as the inverter circuit as shown in the first embodiment, the semiconductor memory circuit shown in the second embodiment, or the drive circuit of the liquid crystal display device. The application of is effective.

[0017]

According to the structure of the complementary thin film transistor of the present invention, which has been briefly described in the above embodiments, the following numerous effects can be obtained.

1) A forward stagger type first conductivity type thin film transistor and an inverse stagger type second conductivity type thin film transistor constitute a complementary type thin film transistor, and a semiconductor layer serving as a source and drain region of each thin film transistor is a different layer. And the direct connection, the area of the complementary thin film transistor can be reduced, and miniaturization and high integration can be achieved.

2) A forward stagger type first conductivity type thin film transistor and an inverted stagger type second conductivity type thin film transistor constitute a complementary type thin film transistor, and the respective gate electrodes are formed in the same layer. Since the thickness of the active region and the thickness of the gate insulating film of the conductive type thin film transistor and the second conductive type thin film transistor can be independently set, both N-type and P-type thin film transistors can obtain high characteristics. The constructed complementary thin film transistor has high characteristics.

3) A forward stagger type first conductivity type thin film transistor and an inverted stagger type second conductivity type thin film transistor constitute a complementary type thin film transistor, and the source and drain regions are formed in the same layer. Since the film thickness of the gate insulating film of the first conductivity type thin film transistor and the second conductivity type thin film transistor can be independently set, and both N-type and P-type thin film transistors can obtain high characteristics, a complementary layer formed by these Type thin film transistor has high characteristics.

4) A forward stagger type first conductivity type thin film transistor and an inverted stagger type second conductivity type thin film transistor constitute a complementary thin film transistor, and either the source or drain region of the first conductivity type thin film transistor is formed. A gate electrode of the second conductivity type, and a first
By forming either the source or drain region of the conductive type thin film transistor as the gate electrode of the second conductive type thin film transistor, the complementary thin film transistor can be formed on a very small area.

[Brief description of drawings]

FIG. 1 is an element cross-sectional view in each manufacturing process of a complementary thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram when an inverter circuit is formed by the complementary thin film transistor according to the first embodiment of the present invention and a top view of the element.

FIG. 3 is an element cross-sectional view of each of the manufacturing steps of the complementary thin film transistor according to the second embodiment of the present invention.

FIG. 4 is a circuit diagram when a complete CMOS static RAM is formed by the complementary thin film transistor according to the second embodiment of the present invention.

FIG. 5 is an element cross-sectional view of each complementary manufacturing process of the complementary thin film transistor according to the third embodiment of the present invention.

FIG. 6 is an element cross-sectional view of a complementary thin film transistor formed by a conventional technique.

[Explanation of symbols]

101, 301, 501, 601 ... Insulating substrate 102, 108, 306, 503, 505, 603 ...
-Gate insulating film 103, 310, 502, 604 ... Gate electrode of first conductivity type thin film transistor 104, 304, 506, 605 ... Gate electrode of second conductivity type thin film transistor 105, 303, 508, 607 ... First conductivity type impurity ions 106, 304, 509, 608 ... Source and drain regions of first conductivity type thin film transistor 107, 305, 510, 609 ... Active regions 109, 115, 312 of first conductivity type thin film transistor Contact holes 110, 302, 307, 510, 606, 610 ...
-Resist 111, 308, 512, 611 ... Second conductivity type impurity ion 112, 309, 513, 612 ... Source and drain region 113, 310, 514, 613 of second conductivity type thin film transistor ... Second Conductive type thin film transistor active regions 114, 311, 515, 614 ... Interlayer insulating films 116, 313, 517, 616 ... Source and drain electrode terminals 201, 401, 402 ... P-type thin film transistors 202, 403, 404 , 405, 406 ... N-type thin film transistor 203 ... Input line 204 ... Output line 205, 408 ... Power supply voltage line 206, 409 ... Ground line 407 ... Word line 410 ... Data Lines 504, 507, 602 ... Semiconductor layer

Claims (7)

[Claims] 1. A first substrate on an insulating substrate or an insulating thin film.
In a complementary thin film transistor including a conductive thin film transistor and a second conductive thin film transistor,
A complementary thin film transistor comprising a first conductive type thin film transistor having a forward stagger structure and an inverted stagger type second conductive type thin film transistor. 2. The complementary thin film transistor according to claim 1, wherein the source and drain regions of the first conductivity type thin film transistor and the source and drain regions of the second conductivity type thin film transistor are formed from different layers. A complementary thin film transistor, comprising: 3. The complementary thin film transistor according to claim 1, wherein the gate electrode of the first conductivity type thin film transistor and the gate electrode of the second conductivity type thin film transistor are formed of the same layer. A complementary thin film transistor. 4. The complementary thin film transistor according to claim 1, 2 or 3, wherein the source or drain region of the first conductivity type thin film transistor and the source or drain region of the second conductivity type thin film transistor, A complementary thin film transistor characterized by being directly connected. 5. The complementary thin film transistor according to claim 1, wherein the source and drain regions of the first conductive type thin film transistor and the gate electrode of the second conductive type thin film transistor are formed of the same layer. A gate electrode of the second conductivity type thin film transistor, and the first electrode
A complementary thin film transistor, wherein the source and drain regions of the conductive thin film transistor are formed of the same layer. 6. The complementary thin film transistor according to claim 1, 2 or 5, wherein the source or drain region of the first conductivity type thin film transistor constitutes a gate electrode of the second conductivity type thin film transistor. A complementary thin film transistor, wherein the second conductive type gate electrode constitutes a source or drain region of the second conductive type thin film transistor. 7. The complementary thin film transistor according to claim 1, wherein the source and drain regions of the first conductivity type thin film transistor and the source and drain regions of the second conductivity type thin film transistor are formed from the same layer. A complementary thin film transistor, comprising: