JPH04167450A - Wiring device for mounting semiconductor chip - Google Patents

Abstract

PURPOSE:To facilitate designing of wiring patterns, by establishing virtual quarter sub-divisions of a wiring board with diagonal lines and forming lands at a position where the number of external terminals contained in one of the quarter sub-divisions is substantially equally divided along a side of the wiring board. CONSTITUTION:Where a wiring board 4 is virtually separated into four sub-divisions with diagonal lines, lands 6 are formed at a position where the number of external terminals 10 contained in one of the quarter divisions is substantially equally divided along a side 4a of the wiring board 4. Within the quarter sub-division of the wiring board 4 are disposed thirty six external terminals 10 including the ones located on the diagonal lines. These thirty six external terminals are substantially divided into two parts between a second and a third column from the outermost column of the external terminals 10. In this case, the number of external terminals is sixteen at the area closer to the center of the wiring board 4, while the number is twenty at the area remote from the center of the wiring board relative to the lands. The number of conductors 8, which connect between the lands 6 and the external terminals 10 arrayed in a matrix, is substantially equal at both areas relative to the lands 6, thereby assuring that the conductors pass through each row of the external terminals 10 with the highest efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a wiring device for mounting a semiconductor element used in a semiconductor element-mounted PGA (pin grid array) or the like.

(Prior Art) A conventional semiconductor element-mounted PGA (bin grid array), as shown in FIGS.
(referred to as FP))■ and wiring device 2 for mounting this QFPI
It consists of This wiring device 2 has a square wiring board 4, and lands 6 are formed linearly along each side of the wiring board 4 on the top, bottom, left and right sides of one surface of the wiring board 4. Lead terminals 8 of the QFP 1 are individually connected to each land 6 by soldering or the like.

Further, on the other side of the wiring board 4 opposite to the side on which the QFP 1 is mounted, external terminals 10 of the same number as the lands 6 are arranged in a grid pattern and protruded. It penetrates the substrate 4 and is exposed on the mounting side of the QFP 1. Each external terminal IO is individually connected to each land 6 via a conductor (not shown) such as a copper foil formed on the wiring board 4 in advance. Thereby, each external terminal IO is electrically connected to each lead terminal 8 of QFP I via each conductor and land 6.

(Problem to be Solved by the Invention) By the way, in the wiring device 2 used for the semiconductor element-mounted PGA etc. as described above, it has conventionally been difficult to determine where on the wiring board 4 the land 6 is provided. There were no clear guidelines as to which is the most appropriate. Therefore, depending on the formation position of the land 6, the conductor 1 located between each row of external terminals
2 had a large number of wires.

That is, as shown in FIG. 5, the vertical side 4a of the wiring board 4
When lands 6 are provided between the first and second rows from the outside of external terminals 10 along
There are a maximum of three lines between each row. As described above, when the number of conductor wires to be passed between external terminals increases depending on the formation position of the land, high precision is required in the conductor formation technique correspondingly, and wiring pattern design becomes that much more difficult. In particular, the lead terminal 8 of the semiconductor element l
In a case where the number of external terminals 10 is large, if the formation position of the lands 6 is inappropriate, the number of conductors to be wired between each row of external terminals 10 increases accordingly.

The present invention has been made in order to solve such problems, and is designed to form lands at the most appropriate positions for routing conductors in wiring devices for mounting semiconductor elements used in semiconductor element-mounted PGAs, etc. In this way, the conductors are wired in the most uniform manner between each row of external terminals, thereby facilitating the wiring pattern design.

(Means for Solving the Problems) In order to solve these problems, the present invention has a wiring board having a rectangular plane, and one side of the wiring board has semiconductor elements mounted on the wiring board. Lands individually connected to lead terminals are provided along each side of the wiring board,
On the other side of the wiring board, a number of external terminals corresponding to the lands individually are arranged in a grid and protrude, and each of the lands and the external terminals are formed on the wiring board. In a wiring device for mounting semiconductor elements, each of which is connected by a wiring pattern, the wiring board is virtually divided into four parts using diagonal lines, and the number of external terminals included in each quarter is calculated along the sides of the wiring board. It is characterized in that the lands are formed at positions that are almost equally divided.

(Function) According to the above configuration, the number of conductors passing between each row of external terminals is made uniform on the wiring board, so that wiring pattern design becomes easy.

(Example) FIG. 1 is a plan view showing approximately the left half of a wiring device for mounting semiconductor elements constituting a semiconductor element-mounted PGA according to the present invention, and parts corresponding to the conventional example are given the same reference numerals. .

In the figure, 4 is a wiring board, 6 is a land, and ]0 is an external terminal, and these basic structures are the same as in the conventional example. A feature of this embodiment lies in the formation position of the land 6. That is, in this example, when the wiring board 4 is virtually divided into four parts using a diagonal line shown by a dashed-dotted line, the number of external terminals 10 included in one quarter of the part is roughly divided along the side 4a of the wiring board 4. Lands 6 are formed at positions that are equally divided. Specifically, l/ of the wiring board 4
Thirty-six external terminals IO are provided in the fourth part, including those on the diagonal line, and the position where the 36 external terminals are roughly divided into two along the side 4a of the wiring board 4 is outside the vertical row of external terminals 10. It is between the second and third columns. At this time, there are 16 wires on the center side of the wiring board 4 and 20 wires on the opposite side.

If the land 6 is formed at such a position, the number of conductors 8 connecting the land 6 and the external terminals 10 arranged in a lattice pattern can be increased in the left-right direction around the land 6, as shown in FIG. Therefore, the conductor can be passed between each row of external terminals 1o most efficiently.

In this example, the maximum number is two.

Note that the shapes of semiconductor elements mounted on the semiconductor element mounting wiring device vary in size, so if the shape is slightly different, the length of the lead terminal of the semiconductor element may need to be adjusted. This can be dealt with by

(Effects of the Invention) According to the present invention, the lands are formed at the most appropriate positions for routing the conductors, so that the conductors are uniformly routed between each row of external terminals. Therefore, it is possible to easily design a wiring pattern.

[Brief explanation of drawings]

1 and 2 show embodiments of the present invention, and FIG. 1 is a plan view showing approximately the left half of a wiring device for mounting a semiconductor element used to configure a semiconductor element-mounted PGA; FIG. 2 is an explanatory diagram of the wiring situation of conductors connecting lands and external terminals. FIGS. 3 to 5 show conventional examples, and are explanatory diagrams of the wiring state of the conductor connected to the first terminal. 1... Semiconductor element (QFP etc.), 2... Wiring device for mounting semiconductor element, 4... Wiring board, 6... Land, 1°... External terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) It has a wiring board that is rectangular in plan, and on one side of this wiring board, lands that are individually connected to lead terminals of semiconductor elements mounted on this wiring board are arranged along each side of the wiring board. A number of external terminals corresponding to the lands individually are arranged in a grid and protrude on the other side of the wiring board, and each land and the external terminal are connected to each other on the wiring board. In a wiring device for mounting semiconductor elements, each of which is connected by the formed wiring pattern, the wiring board is virtually divided into four parts using diagonal lines, and the number of external terminals included in each quarter is calculated by dividing the wiring board into four parts using diagonal lines. A wiring device for mounting a semiconductor element, characterized in that the lands are formed at positions that are almost equally divided along the sides.