JPH02100353A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a device smaller and light by increasing the ratio accounting for the area of a die pad to the surface of a wiring board with the foregoing area kept constant and then, disposing input/output pads for external connection that are about the same number as those which are obtained before the ratio accounting for the above area to the surface of the wiring board increases in such a way that they are arrayed in a staggered lattice or in a parallel lattice. CONSTITUTION:This device makes the ratio accounting for the area of a die pad to the surface of a wiring board increase with the foregoing area kept constant. Input/output pads for external connection that are around the same number as those which are obtained before the ratio accounting for the above area to the surface of the wiring board increases are disposed in such a way that they are arrayed in a staggered lattice or in a parallel lattice. For example, in addition to forming a wiring circuit on the surface of an insulating substrate 1, in an external connection part, the input/output pads 2 for external connection allow 72 pins to be formed into three columns by a solder DIP system and the like. In other words, in the case where respective pins formed into three columns are put in the same file, each pitch becomes 2.54mm. As an intermediate column is slid at a distance of 1.27mm, pins are formed, on the whole, into a staggered lattice and then its staggered direction is made up so that are 1.27X2mm pitches. A package is thus made smaller and lighter than that having the pitches 2.54mm.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a pin grid array type package.

[Conventional technology]

Conventionally, this type of semiconductor device has an insulating substrate on which a wiring circuit is formed, as shown in FIG. 3, a front view (A) and a bottom view (D) of a conventional semiconductor device. Input/output pins 3 for external connection are arranged and planted in a parallel grid at a pitch of 2.54n+m, and when mounting is performed, the pins are inserted into through holes of the mounting board.
Alternatively, although not shown, as another example, instead of the input/output pin 3 for external connection, metal such as solder may be piled up to form a pad, and when mounting, connect it directly to the wiring pattern 2 of the mounting board. However, in any case, the pitch of the pins or pads was 2.54 mm.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the pitch of the pins or pads of the external connection part is 2.54 mm, so there are 280 bins,
As the number of pins becomes larger, such as 360 pins, the insulating substrate becomes larger, heavier, and extremely expensive. Particularly, in the case where the external connection part has a pad structure, the horizontal precision of the board itself is poor, and the pads rise up from the mounting board during mounting, making mounting difficult.

[Means to solve the problem]

The present invention has a wiring board in which a wiring circuit is formed on the surface of the insulating substrate and a semiconductor chip mounting part is formed in the center, and a plurality of external connection input/output pads electrically connected to the wiring circuit. In a semiconductor device provided on the back surface of a wiring board, the area of the semiconductor chip mounting part is kept constant and the ratio of the area of this mounting part to the surface of the wiring board is increased, and the input/output pads for external connection are connected to the semiconductor chip. Almost the same number of semiconductor devices are arranged in a staggered or parallel lattice pattern as before the increase in the proportion of the mounting area.

(Example〕 Next, the present invention will be explained with reference to the drawings.

FIGS. 1A and 1B show a first embodiment of the present invention,
Figure (A) is a front view, and Figure CB) is a bottom view.

The insulating substrate 1 is made of an insulating material such as glass epoxy, glass polyimide, glass BT, or ceramic. A wiring circuit is formed on the surface of this insulating substrate 1, and a cavity is provided in the center to serve as a semiconductor chip mounting part to form a wiring board, and the back side of this wiring board is provided with a staggered pattern that is electrically connected to the wiring circuit. The diameter arranged in a grid is 0.9+n+a
This external connection section has 72 external connection input/output pads 2 arranged in three rows using solder dips or the like.

That is, the pitch between all three rows is 2.54 mm, but the middle row is shifted by 1.27 mm, creating a houndstooth pattern as a whole. Therefore, the staggered direction is 1.27X (2
It has w and m pitches. The pad height is determined by
Since it is necessary to maintain a certain distance between the mounting board and the wiring board, at least one distance is set in consideration of reliability.

In addition, the size of the semiconductor chip mounted on the wiring board has been increased to 7.
Since it was assumed that the length of the innermost row of pads was approximately 12 m++s due to the size of the cavity, the number of pads in the innermost row was set to 6 pins per side.

Under these dimensional conditions, when comparing a package with around 80 pins, which is the same as the conventional 2.54 mm pitch pin count, the insulating substrate area was reduced by about 30%.

FIGS. 2(^) and (B) show a second embodiment of the present invention,
Figure (A) is a front view, and Figure (B) is a bottom view. Similar to the first embodiment, the insulating substrate 1 is provided with an external connection portion, but in this embodiment, 88 pins are arranged in two parallel grids with a pitch of 1.27++ um. There, an input/output pad 2 for external connection is provided by a solder dip or the like. However, in this case, since the pitch was narrow, the diameter of the external connection portion was set to about 0.5 mm.

In this embodiment, the size of the cavity is the same as in the first embodiment, and the length of one side of the innermost row of pins is 12.7 nus.
And so. Under these dimensional conditions, the area of the insulating substrate was reduced by about 50% when compared with a conventional package with a 2.54 mm pitch and about 80 pins, which is the same number of bins.

〔Effect of the invention〕

As explained above, the package used in the present invention is smaller and lighter than the conventional 2.54 am pitch package, which in turn contributes to the miniaturization and weight reduction of products using this package, that is, semiconductor devices.

Furthermore, since the insulating substrate itself does not become large, warping of the substrate does not occur, and as a result, there are no problems with defects during mounting or assembly, and a highly reliable semiconductor device can be obtained. Furthermore,
The reduction in the area of the insulating substrate reduces material costs, leading to cost reduction.

[Brief explanation of the drawing]

FIGS. 1(A) and (B) are diagrams showing a first embodiment of the present invention, FIGS. 2(A) and (B) are diagrams showing a second embodiment of the present invention, and FIG. A) and (B) are diagrams showing an example of the conventional technology, with Figure (A) being a front view and Figure (It) being a bottom view. 1... Insulating board, 2... Input/output pad for external connection,
・・Input/output pin for external connection.

Claims (1)

[Claims] It has a wiring board with a wiring circuit formed on the surface of the insulating substrate and a semiconductor chip mounting part formed in the center, and a plurality of external connection input/output pads electrically connected to the wiring circuit on the back side of the wiring board. In the semiconductor device provided in the semiconductor device, the area of the semiconductor chip mounting portion is kept constant, and the ratio of the area of the mounting portion to the surface of the wiring board is increased, and the external connection input/output pads are arranged so that the area of the semiconductor chip mounting portion is increased. A semiconductor device characterized in that substantially the same number of semiconductor devices as before the ratio increases are arranged in a staggered or parallel lattice pattern.