JPH03205859A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03205859A JPH03205859A JP32090A JP32090A JPH03205859A JP H03205859 A JPH03205859 A JP H03205859A JP 32090 A JP32090 A JP 32090A JP 32090 A JP32090 A JP 32090A JP H03205859 A JPH03205859 A JP H03205859A
- Authority
- JP
- Japan
- Prior art keywords
- package
- pins
- pin
- semiconductor device
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000011810 insulating material Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 2
- 101100075512 Oryza sativa subsp. japonica LSI2 gene Proteins 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は半導体装置、特にプリント基板の表面に実装
する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device mounted on the surface of a printed circuit board.
[従来の技術]
従来の半導体装置を第3図及び第4図を用いて説明する
。ます、第3図において,1はインサート型パッケージ
としてのピングリッドアレイ(以下、PGAという)タ
イプの半導体装置(以下、LSIという)である。この
PGAタイプのLS■1は、樹脂又はセラミックなどの
絶縁性材料で成形され内部に半導体チップ12が載置さ
れたパッケージ11と、このパッケージ11の下面から
下方に突出する如く設けられた信号及び電源などのピン
13とからなる。[Prior Art] A conventional semiconductor device will be described with reference to FIGS. 3 and 4. In FIG. 3, reference numeral 1 denotes a pin grid array (hereinafter referred to as PGA) type semiconductor device (hereinafter referred to as LSI) as an insert type package. This PGA type LS1 includes a package 11 molded from an insulating material such as resin or ceramic and having a semiconductor chip 12 mounted therein, and a signal and It consists of pins 13 for power supply, etc.
このPGAタイプのLSIIは、プリント基板10上に
載置し、第3図(b)のようにプリント基板10に形或
されたスルーホール10aに上記ピン13を貫通させは
んだ付けして実装する。もしくは、上記ピンエ3の一部
をプリント基板10上に形成した配線パターン10bに
はんだ付けして実装する。This PGA type LSII is mounted on a printed circuit board 10, and the pins 13 are passed through the through holes 10a formed in the printed circuit board 10 and soldered as shown in FIG. 3(b). Alternatively, a part of the pin 3 is soldered and mounted on the wiring pattern 10b formed on the printed circuit board 10.
また、第4図において、2はマウント型パッケージとし
てのクオータフラットパッケージ(以下、QFPという
)タイプのLSIである。このQFPタイプのLSI2
は,絶縁性材料で成形され内部に半導体チップ.12が
載置されたパッケージ21と、このパッケージ21の四
方側面21aに設けられたピン23とからなる。上記ピ
ン23は、パッケージ21の四方側面21aから下方に
屈曲されたのち外方に突出する如く形威されている。Further, in FIG. 4, reference numeral 2 denotes a quarter flat package (hereinafter referred to as QFP) type LSI as a mount type package. This QFP type LSI2
It is molded from an insulating material and has a semiconductor chip inside. It consists of a package 21 on which 12 is placed, and pins 23 provided on four side surfaces 21a of this package 21. The pins 23 are shaped so as to be bent downward from the four side surfaces 21a of the package 21 and then protrude outward.
このQFPタイプのLSI2は、プリント基板10上に
載置し、第4図fblのように当該プリント基板10に
形成された配線パターン10bにピン23をはんだ付け
して実装する。This QFP type LSI 2 is mounted on a printed circuit board 10, and the pins 23 are soldered to the wiring pattern 10b formed on the printed circuit board 10 as shown in FIG. 4 fbl.
[発明が解決しようとする課題]
従来の半導体装置は以上のように構威されているので、
パッケージ11.21のサイズ及び実装可能なピンの間
隔により、設けることができるピン13.23の本数に
制約があり、多くの配線を施すことができず半導体チッ
プの高集積化に対応できない。また、ピンの本数を増や
すためにはパッケージが大きくなるなどの問題点があっ
た。[Problem to be solved by the invention] Since the conventional semiconductor device is structured as described above,
The number of pins 13, 23 that can be provided is limited by the size of the package 11, 21 and the spacing between pins that can be mounted, and it is not possible to provide a large number of wiring lines, making it impossible to respond to high integration of semiconductor chips. Additionally, increasing the number of pins required a larger package.
この発明は上記のような問題点を解消するためになされ
たもので、パッケージの大きさを変えずに多くのピンを
設けることができる半導体装置を得ることを目的とする
。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device in which a large number of pins can be provided without changing the size of the package.
[課題を解決するための手段]
この発明に係る半導体装置は、半導体チップを有するパ
ッケージと、このパッケージの外方に突出する如く設け
られた複数のピンとからなるとともに、上記ピンは、上
記パッケージの下面に設けられた第1ピンと、上記パッ
ケージの側面に設けられるとともに当該側面から下方に
屈曲された第2ピンとからなるものである。[Means for Solving the Problems] A semiconductor device according to the present invention includes a package having a semiconductor chip, and a plurality of pins provided so as to protrude outward from the package, and the pins are connected to the package. It consists of a first pin provided on the bottom surface and a second pin provided on the side surface of the package and bent downward from the side surface.
[作用]
この発明における半導体装置は、パッケージの下面に設
けた第1ピンと、上記パッケージの側面に設けた第2ピ
ンとにより、半導体チップに対して多くの配線を施すこ
とが可能となる。[Function] The semiconductor device according to the present invention allows many wirings to be provided to the semiconductor chip by the first pin provided on the bottom surface of the package and the second pin provided on the side surface of the package.
[実施例]
以下、この発明の一実施例である半導体装置を第1図を
用いて説明する。なお、第3図及び第4図と同じものは
同一の符号を用いて説明を省略する。第1図[al及び
第1図(blは本実施例のLSIの上方及び下方外観斜
視図、第l図telはこのLSIの実装状態を示す側面
図である。[Embodiment] A semiconductor device which is an embodiment of the present invention will be described below with reference to FIG. Components that are the same as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted. FIG. 1 al and FIG. 1 bl are upper and lower external perspective views of the LSI of this embodiment, and FIG. 1 tel is a side view showing the mounting state of this LSI.
図において、3はLSIであり、このLSI3は、絶縁
性材料で成形され半導体チップ12が載置されたパッケ
ージ31と、このパッケージ31の下面31aから下方
に突出する如く設けられた第1ピン33aと、上記パッ
ケージ31の四方側面3lbに設けられた第2ピン33
とからなる。In the figure, 3 is an LSI, and this LSI 3 includes a package 31 molded from an insulating material and on which a semiconductor chip 12 is mounted, and a first pin 33a provided so as to protrude downward from the lower surface 31a of this package 31. and a second pin 33 provided on the four side surfaces 3lb of the package 31.
It consists of.
上記第2ピン33bは、上記パッケージ31の側面3l
bから下方に屈曲されたのち、パッケージ31の下面3
1,aより下方で外方に突出する如く形威されている。The second pin 33b is connected to the side surface 3l of the package 31.
After being bent downward from b, the lower surface 3 of the package 31
It is shaped like it protrudes outward below 1.a.
このLSI3は、第1図(Clのようにプリント基板1
0上に載置され、第lピン33aを第3図に示すPGA
タイプのLSIIのピン13と同様にプリント基板10
のスルーホール10aに貫通させはんだ付けして実装す
る。また、第2ピン33bを第4図に示すQFPタイプ
のLSI2のピン23と同様にプリント基板10の配線
パターン10bにはんだ付けして実装する。This LSI 3 has a printed circuit board 1 as shown in FIG.
0, and the lth pin 33a is shown in FIG.
Printed circuit board 10 similar to pin 13 of type LSII
It is mounted by passing through the through hole 10a and soldering. Further, the second pin 33b is soldered and mounted on the wiring pattern 10b of the printed circuit board 10 in the same manner as the pin 23 of the QFP type LSI 2 shown in FIG.
上記構威により、従来のLSII,2と比べて2倍以上
の本数のピンをパッケージ31に設けることができ、上
記パッケージ31の大きさを従来のパッケージ11.2
1と変えることなく半導体チップ12に対して多くの配
線を施すことができ、半導体チップ12の高集積化に対
応することができる。With the above structure, it is possible to provide the package 31 with more than twice the number of pins compared to the conventional LSII,2, and the size of the package 31 can be reduced to 11.2 times that of the conventional package.
It is possible to provide a large number of wiring lines to the semiconductor chip 12 without changing the structure of the semiconductor chip 12, and it is possible to cope with higher integration of the semiconductor chip 12.
なお、本実施例においては、第1ピン33aをプリント
基板10のスルーホール10aに貫通させるとしたが、
先端をそのまま配線パターン10bに実装してもよく、
この場合、第1ピン33aと第2ピン33bとの先端は
同じ位置となるように形成すればよい。Note that in this embodiment, the first pin 33a is passed through the through hole 10a of the printed circuit board 10, but
The tip may be mounted as is on the wiring pattern 10b,
In this case, the tips of the first pin 33a and the second pin 33b may be formed at the same position.
また、本実施例においては、第2ピン33bをパッケー
ジ33の側面33aから下方に屈曲されたのち外方に突
出する如く形戒するとしたが、第2図に示すように、第
2ピン33cをパッケージ31の側面3lbから下方に
屈曲して、第1ピン33aと同一長さとなるように形成
してもよく、この場合、第1,第2ピン33a,33c
をそれぞれプリント基板10のスルーホール10aに貫
通させはんだ付して実装するようにしてもよい。Furthermore, in this embodiment, the second pin 33b is shaped so as to be bent downward from the side surface 33a of the package 33 and then protrude outward; however, as shown in FIG. It may be bent downward from the side surface 3lb of the package 31 and formed to have the same length as the first pin 33a; in this case, the first and second pins 33a, 33c
They may be mounted by passing through the through holes 10a of the printed circuit board 10 and soldering them respectively.
[発明の効果]
以上のように、この発明によれば半導体装置に、第1ピ
ンをパッケージの下面に、第2ピンを上記パッケージの
側面に設けたことにより、パッケージのサイズを変えず
にピンの本数を増やすことができ、半導体チップの高集
積化に対応することが可能となる。[Effects of the Invention] As described above, according to the present invention, in a semiconductor device, the first pin is provided on the bottom surface of the package, and the second pin is provided on the side surface of the package, so that pins can be formed without changing the size of the package. The number of chips can be increased, making it possible to cope with higher integration of semiconductor chips.
第1図(al, (b)は本発明の一実施例である半導
体装置の上方及び下方外観斜視図、第1図(Clは本実
施例の半導体装置の実装状態を示す側面図、第2図ta
+及び第2図(1))は本発明の他の実施例である半導
体装置の外観斜視図及び実装状態を示す側而図、第3図
fa)及び第4図ialは従来の半導体装置の−E方外
観斜視図、第3図(b)及び第4図tb+は従来の半導
体装置の実装状態を示す側面図である。
1,2.3・・LSI.11,21.31・・・パッケ
ージ、12・・・半導体チップ、33a・・一第lピン
、33b・・・第2ピン。FIGS. 1A and 1B are upper and lower external perspective views of a semiconductor device according to an embodiment of the present invention, FIG. Figure ta
+ and FIG. 2 (1)) are external perspective views and side views showing the mounting state of a semiconductor device according to another embodiment of the present invention, and FIG. 3 fa) and FIG. 4 ial are views of a conventional semiconductor device. -E perspective external view, FIG. 3(b) and FIG. 4 tb+ are side views showing the mounting state of a conventional semiconductor device. 1,2.3...LSI. 11, 21. 31... Package, 12... Semiconductor chip, 33a... First l pin, 33b... Second pin.
Claims (1)
外方に突出する如く設けられた複数のピンとからなる半
導体装置であって、上記ピンは、上記パッケージの下面
に設けられた第1ピンと、上記パッケージの側面に設け
られるとともに当該側面から下方に屈曲された第2ピン
とからなることを特徴とする半導体装置。A semiconductor device comprising a package having a semiconductor chip and a plurality of pins provided so as to protrude outward from the package, the pins including a first pin provided on the bottom surface of the package and a side surface of the package. and a second pin bent downward from the side surface of the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32090A JPH03205859A (en) | 1990-01-05 | 1990-01-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32090A JPH03205859A (en) | 1990-01-05 | 1990-01-05 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03205859A true JPH03205859A (en) | 1991-09-09 |
Family
ID=11470616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32090A Pending JPH03205859A (en) | 1990-01-05 | 1990-01-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03205859A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475261A (en) * | 1990-09-19 | 1995-12-12 | Fujitsu Limited | Semiconductor device having many lead pins |
US5490040A (en) * | 1993-12-22 | 1996-02-06 | International Business Machines Corporation | Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array |
US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
-
1990
- 1990-01-05 JP JP32090A patent/JPH03205859A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475261A (en) * | 1990-09-19 | 1995-12-12 | Fujitsu Limited | Semiconductor device having many lead pins |
US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
US6031280A (en) * | 1992-06-02 | 2000-02-29 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
US6271583B1 (en) | 1992-06-02 | 2001-08-07 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
US5490040A (en) * | 1993-12-22 | 1996-02-06 | International Business Machines Corporation | Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array |
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