JPH04150056A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04150056A JPH04150056A JP2274587A JP27458790A JPH04150056A JP H04150056 A JPH04150056 A JP H04150056A JP 2274587 A JP2274587 A JP 2274587A JP 27458790 A JP27458790 A JP 27458790A JP H04150056 A JPH04150056 A JP H04150056A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- gold
- sealing
- layer
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
従来の半導体装置は、第２図（ａ）〜（Ｃ）に示すよう
に、内側中央部に素子載置部を設けたセラミック容器１
の側壁を貫通してセラミック容器１の底面まで導出した
配線層２と、配線層２にろう材３を介して接合したリー
ド４と、セラミック容器１の上端面に設けたメタライズ
層７及び金めつき層８を有し、素子載置部に半導体チッ
プ５をマウントし、半導体チップ５と配線層２との間を
金属細線６で接続し、金めつき層８の上にシール用ろう
材１２を介してキャップ１１を接合し、気密封止してい
た。As shown in FIGS. 2(a) to 2(C), a conventional semiconductor device includes a ceramic container 1 in which an element mounting portion is provided at the center of the inside.
A wiring layer 2 that penetrates the side wall of the ceramic container 1 and leads to the bottom surface of the ceramic container 1, a lead 4 that is connected to the wiring layer 2 via a brazing material 3, and a metallized layer 7 and gold plating provided on the upper end surface of the ceramic container 1. The semiconductor chip 5 is mounted on the element mounting portion, the semiconductor chip 5 and the wiring layer 2 are connected by a thin metal wire 6, and a sealing brazing material 12 is formed on the gold plating layer 8. The cap 11 was joined via the cap 11, and the cap 11 was hermetically sealed.
上述した従来の半導体装置は半導体パッケージの大きさ
が大型（例えば１０ｍｍＸ１０＋ａｍ以上）になるとセ
ラミックの焼結時の収縮、応力歪等により封止面の平坦
性が悪くなり、封止面のうねりを生じ、金糸共晶合金を
熔融させキャップを接合する際、第２図（ｃ）に示すよ
うに、空隙１３を生じ、十分な気密封止が出来ず、気密
不良を発生するという欠点がある。In the conventional semiconductor device described above, when the size of the semiconductor package becomes large (for example, 10 mm x 10 + am or more), the flatness of the sealing surface deteriorates due to shrinkage and stress distortion during ceramic sintering, causing waviness of the sealing surface. When the gold thread eutectic alloy is melted and the cap is joined, as shown in FIG. 2(c), voids 13 are formed, and a sufficient airtight seal cannot be achieved, resulting in poor airtightness.
本発明の半導体装置は、絶縁性容器を含むパッケージ本
体と、前記パッケージ本体の封止面に設けたシール用ろ
う材を介して接合し気密封止するキャップとを有する半
導体装置において、前記封止面に設けた金属板を有する
。The semiconductor device of the present invention includes a package body including an insulating container, and a cap that is bonded to and hermetically sealed via a sealing brazing material provided on the sealing surface of the package body. It has a metal plate provided on the surface.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
第１図に示すように、アルミナ又はベリリア等のセラミ
ック容器１の内側中央部に素子載置部を設け、素子載置
部の周囲からセラミック容器１の側壁を貫通してセラミ
ック容器１の底面まで配線層２を設け、セラミック容器
１の底面の配線層２に銀−銅等の共晶合金からなるろう
材３でリード４を取付けて構成した半導体パッケージ本
体のセラミック容器１の上端面に厚さ２０〜３０μｍの
モリブデン又はタングステン等のメタライズ層７と、厚
さ５０〜８０μｍの銀−銅共晶合金等のろう材９と、厚
さ１００μｍのコバールあるいは銀ニッケル合金等の金
属板１０を順次積層し、金属板１０の表面に厚さ２μｍ
の金めつき層を形成する。次に、素子載置部に半導体チ
ップ５をマウントし、半導体チップ５の電極と配線層２
の間を金属細線６て接続する。次に、金めつき層８の上
に厚さ８０〜１００μｍのＡｕ−５ｎ合金等の金糸共晶
合金からなるシール用ろう材１２を介してキャップ１１
を接合して半導体パッケージ本体を気密封止する。As shown in FIG. 1, an element mounting part is provided at the center inside of a ceramic container 1 made of alumina or beryllia, and the device is passed from the periphery of the element mounting part through the side wall of the ceramic container 1 to the bottom surface of the ceramic container 1. A wiring layer 2 is provided on the bottom surface of the ceramic container 1, and a lead 4 is attached to the wiring layer 2 on the bottom surface of the ceramic container 1 using a brazing material 3 made of a eutectic alloy such as silver-copper. A metallized layer 7 of molybdenum or tungsten or the like with a thickness of 20 to 30 μm, a brazing material 9 such as a silver-copper eutectic alloy with a thickness of 50 to 80 μm, and a metal plate 10 of Kovar or silver-nickel alloy with a thickness of 100 μm are sequentially laminated. The surface of the metal plate 10 has a thickness of 2 μm.
Forms a gold-plated layer. Next, the semiconductor chip 5 is mounted on the element mounting part, and the electrodes of the semiconductor chip 5 and the wiring layer 2 are
A thin metal wire 6 is used to connect between the two. Next, a cap 11 is placed on the gold plating layer 8 through a sealing brazing material 12 made of a gold thread eutectic alloy such as an Au-5n alloy with a thickness of 80 to 100 μm.
are joined to hermetically seal the semiconductor package body.
以上説明したように本発明は、キャップと対向する絶縁
性容器の封止面に金属板を介在させて接合し、封止面の
平坦性を確保することにより、十分な気密性を有した封
止かできるという効果を有する。As explained above, the present invention provides a seal with sufficient airtightness by interposing and joining a metal plate to the sealing surface of the insulating container facing the cap and ensuring the flatness of the sealing surface. It has the effect of being able to stop.
第１図は本発明の一実施例を示す断面図、第２図（ａ）
〜（ｃ）は従来の半導体装置の一例を示す一部切欠平面
図及びＡ−Ａ’線断面図及びＢ−Ｂ′線断面図である。
１・・・セラミック容器、２・・・配線層、３・・・ろ
う材、４・・・リード、５・・・半導体チップ、６・・
・金属細線、７・・・メタライズ層、８・・・めっき層
、９・・・ろう材、１０・・・金属板、１１・・・キャ
ップ、１２・・・シール用ろう材、１３・・・空隙。Figure 1 is a sectional view showing one embodiment of the present invention, Figure 2 (a)
-(c) are a partially cutaway plan view, a cross-sectional view taken along the line AA', and a cross-sectional view taken along the line B-B', showing an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Ceramic container, 2... Wiring layer, 3... Brazing material, 4... Lead, 5... Semiconductor chip, 6...
- Fine metal wire, 7... Metallized layer, 8... Plating layer, 9... Brazing material, 10... Metal plate, 11... Cap, 12... Brazing material for sealing, 13...・Void.
Claims (1)
本体の封止面に設けたシール用ろう材を介して接合し気
密封止するキャップとを有する半導体装置において、前
記封止面に設けた金属板を有することを特徴とする半導
体装置。In a semiconductor device having a package body including an insulating container, and a cap that is joined via a sealing brazing material provided on the sealing surface of the package body for airtight sealing, a metal plate provided on the sealing surface is provided. A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274587A JPH04150056A (en) | 1990-10-12 | 1990-10-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274587A JPH04150056A (en) | 1990-10-12 | 1990-10-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04150056A true JPH04150056A (en) | 1992-05-22 |
Family
ID=17543822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2274587A Pending JPH04150056A (en) | 1990-10-12 | 1990-10-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04150056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945735A (en) * | 1997-01-31 | 1999-08-31 | International Business Machines Corporation | Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity |
-
1990
- 1990-10-12 JP JP2274587A patent/JPH04150056A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945735A (en) * | 1997-01-31 | 1999-08-31 | International Business Machines Corporation | Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity |
| KR100260686B1 (en) * | 1997-01-31 | 2000-07-01 | 포만 제프리 엘 | Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity |
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