JPH0414166A - Program controller for multi-cpu system - Google Patents

Abstract

PURPOSE:To enable a master CPU to control the operation of each slave CPU by providing a program store RAM, an internal/external bus switching part, an address control part, and a CPU bus separating part. CONSTITUTION:When a program controller is started, a bus switching part 6 is turned toward an external bus 3 and a slave CPU 4 is set in a waiting state by a wait signal 9. Then a program is written into a program store RAM 5 from a substrate containing a master CPU 1. A specific address produced from the substrate is detected by an address control part 8, and the RAM 5 is turned toward an internal bus 10 by the part 6. At the same time, the operation of the CPU 4 is validated by a bus separating part 7 and connected to the bus 10. Thus an optional program necessary for control of a program can be occasionally written into the RAM 5 of the slave CPU side from the CPU 1. As a result, the CPU 1 can perfectly control the operation of the CPU 4 in a direct method.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a board on which a master CPU is mounted and a slave CPU.
The present invention relates to a multi-CPU (central processing unit) program control device that is connected to a board on which a PU is mounted via an external bus.

Conventional technology Conventionally, in this type of multi-CPU system, the mask CPtJ
, data exchange between slave CPUs was carried out using a bus coupling method or a shared memory method, execution control between the CPUs was controlled by the contents of the data exchanged, and a series of operations were realized as a device.

Problems to be Solved by the Invention However, in the conventional program control method described above, the data necessary for program control is extracted from the data exchanged between the mask CPU and the slave CPU, and each CPU executes the program in accordance with the data. Since the control method has to be changed, these procedures are complicated, and the complexity of synchronizing the master CPU and each individual slave CPU is doubled.

The present invention is intended to solve these conventional problems.
The master CPU directly controls the program of the slave CPU, allowing the master CPU to control the operation between each CPU.
The purpose is to provide an excellent program control device that can be easily managed.

Means for Solving the Problems In order to achieve the above object, the present invention provides a program storage RAM, an internal/external bus switching section, an address control section, and a CPU bus separation section in a board on which a slave CPU is mounted, Using software from the board on which the mask CPU is mounted, the slave CPU is arbitrarily placed in a maintenance state, the RAM for program storage is switched to an external bus, and the RAM for program storage is switched to the external bus.
This allows new programs to be written to AM.

Therefore, according to the present invention, any program necessary for program control can be transferred from the master CPU to the slave CPU at any time.
Since it can be written to the program storage RAM on the PU side, the master CPU can completely manage the operations of the slave CPU in a direct manner. In addition, the slave CPU can operate completely independently of the state of the master CPU until the master CPU becomes necessary, thus making it possible to configure a system with a high degree of freedom.

Example The figure shows the configuration of an embodiment of the present invention.

In the figure, 1 is a board (board A) on which a master CPU for managing the entire device is mounted, and 2 is a board (board B) on which a slave CPU is mounted, which is placed under the control of board A.

3 is an external path line that electrically connects board A (1) and board B (2), 4 is a slave CPU, 5 is a RAM for storing programs, and 6 is a connection of RAM 5 for storing programs to the external path line. internal bus or internal/
7 is a bus separation unit that separates the slave CPU from the internal path line; 8 is an address control unit that controls the bus switching unit 6 and the bus separation unit 7 by an address signal from the master CPU; 9 is a slave CPU; A wait signal line for keeping the CPU 4 in a holding state, 10 is an internal pass line, 11
is a power supply section for supplying power to the entire device.

Next, the operation of the above embodiment will be explained. When the device is started up, the bus switching unit 6 is switched to the external bus 3 side, and the wait signal 9 puts the slave CPU 4 into a waiting state. After that, the program is transferred from board A1 to the RAM for program storage.
5 and when a specific address (or specific command) is issued from the board A, the address control unit 8 detects this and causes the bus switching unit 6 to transfer the program storage RAM 5 to the internal bus side. The bus separation unit 7 enables the operation of the slave CPU 4 and connects it to the internal path line 10. As a result, the slave CPU 4 becomes executable and operates according to the program instructed by the master CPU of the board A.

If the master CPU of the board A during execution becomes necessary, it accesses a specific address and the bus separation unit 7 is activated by the address control unit 8.
The slave CPU enters a 4-wait state via the bus switching unit 6, and the program storage RAM 5 is transferred to the external bus by the bus switching unit 6.The master CPU updates part and all of the program of this slave CPU 4, and then restarts the power supply. Slave CPU 4 can be restarted using the same method. Note that if a reset signal is generated from the bus separator 7 to the slave CPU 4 in the same manner as the wait signal, the slave CPU
It is also possible to start U4 from an initial state.

This operation has the advantage that the master CPU can directly control the operation of the slave CPU 4 by modifying the program.

Effects of the Invention As is clear from the above embodiments, the present invention utilizes a slave CPU.
A program storage RAM, a bus switching section, a bus separation section, and an address control section are installed on the board mounted on the board, and the program mounted on one board can be easily changed from the other board at any time. Master CP
This has the effect that the board on which U is mounted can manage all operations of the board on which the slave CPU is mounted by direct control by changing the program.

[Brief explanation of drawings]

The figure is a block diagram of an apparatus that implements a program control method according to an embodiment of the present invention. A board on which a master CPU is mounted, 2...Slave CPU
Board on which U is mounted, 3... External pass line, 4...
Slave CPU, 5, RAM for program storage, 6...
・Bus switching unit, 7...Bus separation unit, 8 Address control unit, 9...Wait signal line, 10...Internal lotus line,
11...Power supply section.

Claims (1)

[Claims] A first board on which a master CPU is mounted, and this master CPU
A second board mounting a slave CPU connected to the U via an external bus, a program storage RAM provided in the second board, and a program storage RAM connected to the external bus or the internal bus. a bus switching section for switching to the internal bus side, a bus separation section for separating the slave CPU from the internal bus, and a control section for controlling the bus switching section and the bus separation section according to commands from the master CPU; When the switching unit is switched to the external bus side, the program is stored in the program storage RAM from the master CPU,
A program control device for a multi-CPU system, characterized in that the bus switching section is switched to an internal bus side, and the bus separation section connects the slave CPU to the internal bus to operate the slave CPU.