JPH01125653A - Information processing system - Google Patents

Abstract

PURPOSE:To give an action instruction to an optional microprocessor in a short time by designating an optional processor and giving an instruction direct ly to this processor in the case of all microprocessors except the working ones are cut off from buses. CONSTITUTION:A processor selecting designation signal line 102 is driven for an optional microprocessor itself so that this microprocessor cut off from a bus except the working microprocessors. Thus an instruction is sent to an address instruction bus 103 together with an instruction parameter sent to a data bus 104 respectively. When a write designation signal line 106 is driven under such conditions, a processor instruction control circuit 4 sets a signal line 112 by an instruction given to the circuit 4 itself and sets an instruction at an instruction register 3. Then the circuit 4 sets the instruction parameter at a data register 2. When an instruction is received by the register 3, the register 3 gives information to a microprogram control circuit 5 via an instruction start designation signal line 101.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a system in which a plurality of microprocessors are connected to one bus, and more particularly to a system for instructing the operation of the microprocessors in such a system.

(Prior Art) Conventionally, in this type of information processing system, it has not been possible to directly instruct the operation of a processor, but instructions have been given via main memory, local memory, or the like.

FIG. 2 is a block diagram showing an example of an information processing system according to the prior art. In Figure 2, 1 is an address register for accessing the input/output device or storage circuit, 2 is a data register for holding data sent from the input/output device or storage circuit, and 5 is for controlling the microprogram. It is a microprogram control circuit for.

6 is a microprocessor circuit, and address register 1
, a data register 2, and a microprogram control circuit S.

Data register 2 is connected to microprogram control circuit 5 by data set signal 99209.

The microprogram control circuit S is connected to the write instruction signal line 20
3. Meeting instruction signal line 204, I10 instruction instruction line 205
, a memory instruction signal line 206, a hold request signal line 20f, and a hold clearance signal line 208.

If the microprocessor is logically disconnected from bus 201 by hold request signal line 20,
It cannot receive signals from bus 201 or output signals to bus 201.

However, it is operable as a microprogram, and is stopped at the time the bus 201 is accessed. Here, when the hold request signal 5207 is released, the microprocessor whose hold is released can use the bus 201. Therefore, by preparing a startup flag and parameters for each microprocessor in the main memory and releasing the hold request signal line 20 after a certain period of time, it becomes possible to start the microprocessor and pass the parameters. Here, if a large number of parameters are passed, it will take a long time to create the parameters themselves and read them from the microprocessor.

(Problems to be Solved by the Invention) The conventional information processing system described above issues instructions to an arbitrary microprocessor via main memory, local memory, etc., and therefore it takes a long time to transfer data associated with instruction operations. It has the disadvantage that it takes a long time.

An object of the present invention is to specify an arbitrary processor and directly instruct the microprocessor, even if other microprocessors other than the currently operating microprocessor are logically separated from each other by bus. It is an object of the present invention to provide an information processing system configured to eliminate the above-mentioned drawbacks and shorten processing time by sending instruction data.

(Means for Solving the Problems) In the information processing system according to the present invention, a plurality of microprocessor circuits and one main memory circuit are connected by an address bus and a data bus, and any microprocessor circuit can operate. The other microprocessor circuits are configured to be disconnected from the bus by a hold instruction when the microprocessor is running, and each of the multiple microprocessors has a command register, a data register, a processor command control circuit, and a microprogram control circuit. It is constructed by comprising the following.

The command register is for receiving instructions from other Frosesakara commands.

The data register is for receiving input data accompanying command instructions or other input data.

The processor command control circuit is for instructing the command register and the data register to write a command through an address bus and data through a data bus, respectively, in accordance with an instruction to select its own processor, a write instruction, and a waiting instruction.

The microprogram control circuit receives a command activation instruction and controls the microprogram.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention. In FIG. 1, 1 is an address register for accessing input/output devices and memory circuits, 2 is a data register for inputting read data and command parameters, 3 is a command register, and 4 is a data register for inputting read data and command parameters.
Is it a processor command control circuit and S is a microprogram? This is a microprogram control circuit for control.

, 7 is a microprocessor circuit, which is constructed to include an address register 1, a data register 2, a command register 3, a processor command control circuit 4, and a microprogram control circuit S.

Command register 3 is connected to command data set signal line 11
2 is connected to the processor command control circuit 4, and connected to the microprogram control circuit 5 by a command activation instruction signal f4101. The processor command control circuit 4 is also connected to the data register 2 by the command data set signal a112, and is further connected to the outside by has been done.

The microprogram control circuit S is connected to the I10 instruction line 10.
8, memory instruction signal line 109, hold request signal line 11
01 and a hold clearance signal line 111.

Now, in an attempt to start up an arbitrary microprocessor, a signal line 1 is sent to the microprocessor that instructs the microprocessor to select its own processor.
02, a command is output on the address command bus 103 and command parameters are output on the data bus 104.

When the write instruction signal @106 is driven, the processor command control circuit 4 recognizes that the command is sent to itself and sends the command data set signal? Set f1112 to set a command in command register 3, and set command parameters in data register 2.

When a command is input to the command register 3, the command register 3 notifies the microprogram control circuit S of the above through the command activation instruction signal line 101.

When inputting a plurality of parameters following a command, it is possible to make the output of the command parameters wait by using the waiting instruction signal line 107 until the microprogram or data is used.

Finally, even if any microprocessor is in the hold state, it is possible to activate the microprocessor. Commands and command parameters can be transferred to any microprocessor in about the same time as other microprocessors store the command and command parameters in a particular location in the memory circuit.

Even in the hold state, the microprogram can operate and can interpret and prepare commands.

If you release the hold request after a certain amount of time, if necessary,
At that time, you can miss using the bus.

(Effects of the Invention) As explained above, the present invention allows any processor to be specified and directly accessed even if other microprocessors other than the currently operating microprocessor are logically disconnected from the bus. By directly sending instructions and instruction data to the microprocessor concerned, there is an effect that operation instructions can be given to any microprocessor in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention. FIG. 2 is a block diagram showing an example of an information processing system according to the prior art. 1...Address register 2...Data register 3...Working command register 4aa/Processor command control circuit 5a/microprogram control circuit 6, F...hiro microprocessor circuit

Claims (1)

[Claims] A plurality of microprocessor circuits and one main memory circuit are connected by an address bus and a data bus, and when any microprocessor circuit is operating, other microprocessor circuits are disconnected from the bus by a hold instruction. The information processing system is configured to be separated, and each of the plurality of microprocessor circuits has a command register for receiving commands from the other processors, and input data accompanying the commands, or A data register for receiving other input data, a command by the address bus, and data by the data bus, respectively, for the command register and the data register according to the own processor selection instruction, write instruction, and waiting instruction. An information processing system comprising: a processor command control circuit for instructing writing; a command control circuit; and a microprogram control circuit for receiving a command activation instruction and controlling a microprogram.