JPH04107925A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] To provide a semiconductor device, particularly regarding the structure of the connecting portion between metal wiring and leads within a chip, which is highly reliable and allows relaxation of control conditions in the manufacturing process. [1] It has a pad made of silicide, a part of the surface of the pad is in contact with an intra-chip wiring, the intra-chip wiring is covered with an insulating film, and the other part of the surface of the pad is in contact with a part of the surface of the pad. A bump is formed on a portion of the metal layer through a multilayer metal film.

[2] The silicide is tungsten silicide, and the multilayer metal film is configured such that the pad side is made of tungsten and the bump side is made of palladium.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a structure of a connecting portion between metal wiring and leads within a chip.

[Conventional technology]

In conventional semiconductor devices, the connection between the chip and the leads is usually
A wire bonding method is used in which the bonding pads provided on the chip and the leads are connected with wires such as gold.The bonding pads are made of the same material as the aluminum or aluminum alloy internal wiring in the chip during the wafer process. formed at the same time. The internal wiring on the chip is then protected by applying a protective insulating film (passivation film), or since it is not possible to apply an insulating film to the bonding pad, the surface of the aluminum or aluminum alloy bonding pad is , as shown in FIG. 2, is exposed until it is sealed in a package.

FIG. 2 is a schematic cross-sectional view showing an example of a chip of a conventional semiconductor device. This is an example of an integrated circuit having a multilayer wiring structure. In the figure, 1 is a silicon substrate, and elements are formed inside it, although not shown.

2 is an oxide film (SiO□), 23 is a polysilicon electrode,
24 is a polysilicon pad, 25 is a barrier metal (T
iW, etc.) 26 is the first internal wiring, 28 is the second internal wiring, both of which are made of aluminum or aluminum alloy (in this example, the former is Al-Cυ and the latter is Al
-3i). A part of the second internal wiring 28 covers the surface of the pad 24, and a part of the second internal wiring 28 covers the surface of the pad 24, and
It becomes. 27 is an interlayer insulating film (PSG, etc.);
29 is a protective insulating film (P S G +S+3N4 etc.). The protective insulating film 29 has an opening above the bonding pad 28A.

In addition to the wire bonding method described above, TAB (tap)
There is a method of connecting with a bump, such as the automated bonding method, but in this case, the bump is formed on the bonding pad 28A via a multilayer metal film.

[Problem to be solved by the invention]

However, during the manufacturing process of these semiconductor devices, when the aluminum or aluminum alloy pads are exposed, they are exposed to the atmosphere or purified water for cleaning, resulting in moisture absorption, which can lead to poor contacts, disconnections, or device failure. There was a problem in that it could cause changes in characteristics.

Moreover, in order to prevent these problems, it is necessary to strictly control manufacturing conditions and storage conditions.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a semiconductor device that is highly reliable and allows for relaxing control conditions in the manufacturing process.

[Means to solve the problem]

This purpose, according to the present invention, [1] has a pad made of silicide, a part of the surface of the pad is in contact with an in-chip wiring, and the in-chip wiring is covered with an insulating film; [2] The above-mentioned silicide is tungsten silicide, and the above-mentioned multilayer metal This is achieved by configuring the film so that the pad side is made of tungsten and the bump side is made of palladium.

[Effect]

Although silicide has a slightly higher specific resistance than aluminum or aluminum alloys, it has much better oxidation resistance, moisture resistance, water resistance, etc. Therefore, if the bonding pad is formed of silicide, almost no problems will occur even if the pad is exposed to the atmosphere or pure water for cleaning during the manufacturing process when its surface is exposed. However, since there is a problem with wire bonding, bonding is performed using bumps. As a silicide, tungsten has good adhesion to 5i02.
Silicide (WSiz) is used, and as a multilayer metal film, the pad side (contact metal) is made of tungsten (W), which has good adhesion with WSir and has low contact resistance, and gold (A
By using palladium (Pd), which has good adhesion to gold, as the bump side (barrier metal) of u), a highly reliable bump can be obtained.

Note that the internal wiring itself on the chip is made of aluminum or aluminum alloy as before, but it is brought into contact with the parts of the silicide pads other than the bump formation areas, and is covered with an interlayer insulation film or protective insulation film, so there are no exposed parts and it is easy to bond. is not directly involved.

〔Example〕

An embodiment of a semiconductor device according to the present invention will be described with reference to FIG.

FIG. 1 is a schematic cross-sectional view showing a chip of a semiconductor device according to an embodiment of the present invention. This is an example applied to an integrated circuit having a multilayer wiring structure. In the figure, ■ is a silicon substrate, and although not shown, elements are formed inside it. 2 is an oxide film (
5 iOz), 3 is a polysilicon electrode (however, the upper surface is silicided (WSL)), 4 is a tungsten silicide (WSiz) pad, and 5 is a barrier metal (TiW).

Reference numeral 6 denotes a first intra-chip wiring, and numeral 8 denotes a second intra-chip wiring, both of which are made of aluminum or aluminum alloy (in this example, the former is Al-Cu and the latter is Al-3i).

7 is an interlayer insulating film (P S G), and 9 is a protective insulating film (P S G + Sis'fh). 10 is a multilayer metal film (Pd+W), and 1] is a bump (Au), and the upper surface of the bump 1] protrudes from the protective insulating film 9.

The second intra-chip wiring 8 is in contact with a part of the surface of the pad 4, but the periphery is covered with the interlayer insulating film 7 and the protective insulating film 9, and there is no exposed part.

On the other hand, the protective insulating film 9 has an opening in a portion of the surface of the pad 4 that does not include the contact portion with the second intra-chip wiring 8, and a bump 1] is formed there through the multilayer metal film IO. ing. Therefore, there is no exposed portion on the surface of the bat 4.

The inventor created a chip having such a structure as follows. First, a contact hole is formed in the oxide film 2 on the surface of a silicon substrate 1 (wafer), and then polysilicon is grown on the oxide film 2 (to a thickness of about 0.1 μm) by CVD and patterned. Next, after depositing tungsten on the entire surface using a sputtering method, when heated, the tungsten on the polysilicon combines with the polysilicon, forming a tungsten layer.
Silicide (WSL). Thereafter, the desired pad 4 is obtained by removing tungsten by wet etching. At this time, the upper part of the electrode 3 is also made into tungsten silicide. Next, TiW was deposited by sputtering method (
After the thickness is about 0.3 .mu.m, A1Cu is further deposited by sputtering (thickness of about 1.0 .mu.I+1) and patterned to form barrier metal 5 and first intra-chip wiring 6. Next, PSG is grown using the CVD method (thickness approximately 1.0
After forming an interlayer insulating film 7 (with a thickness of approximately 1.0 μm) and forming a connection hole in this, a layer of Sho-3i is deposited by sputtering to a thickness of approximately 1.0 μm), and this is patterned to form the second in-chip wiring. form 8. Furthermore, PSG (thickness approximately 1.0μm)
A protective insulating film 9 is formed by growing 5i3N4 (thickness: about 0.3 μm) using the CVD method. After opening a hole in the protective insulating film 9 at the bump formation location, first tungsten is selectively grown on the pad 4 in the opening using the CVD method (to a thickness of about 0%).
．． 1 .mu.m), and then palladium is deposited by sputtering (to a thickness of about 0.3 .mu.m) to form the multilayer metal film 10.

Furthermore, this was used as an electrode and gold was plated on top of it to a height of about 3.
0 μm bump 1] is formed.

In the above manufacturing process, there is no need to strictly limit the storage method or storage time even during the period when the bumps 4 are exposed, and there is no need to narrow the process margin in anticipation of changes in device characteristics.

The present invention is not limited to the above embodiments, but can be implemented with various modifications. For example, the present invention is effective even in the case of contact between the first intra-chip wiring 6 and the pad 4.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor device that is highly reliable and allows for relaxing control conditions in the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view showing a chip of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view showing an example of a chip of a conventional semiconductor device. In the figure, ■ is a silicon substrate, 2 is an oxide film, 4 is a pad, 6 and 26 are wirings in the first chip, 7.27 is an interlayer insulating film, 8.28 is wiring in the second chip, 1] is the wiring in the second chip. Bump 28A is a bonding pad. 1: Silicone sales 2: Densification copy f, fe month/
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Claims (1)

[Claims] [1] It has a pad made of silicide, a part of the surface of the pad is in contact with an intra-chip wiring, the intra-chip wiring is covered with an insulating film, and the pad surface has A semiconductor device characterized in that a bump is formed on the other part with a multilayer metal film interposed therebetween. [2] The semiconductor device according to claim 1, wherein the silicide is tungsten silicide, and the multilayer metal film has tungsten on the pad side and palladium on the bump side.