JPH06196526A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06196526A JPH06196526A JP4346422A JP34642292A JPH06196526A JP H06196526 A JPH06196526 A JP H06196526A JP 4346422 A JP4346422 A JP 4346422A JP 34642292 A JP34642292 A JP 34642292A JP H06196526 A JPH06196526 A JP H06196526A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- aluminum
- semiconductor substrate
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/03—Manufacturing methods
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に同装置のボンディングパッド部の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bonding pad portion of the same device.
【０００２】[0002]
【従来の技術】従来、この種の半導体装置の製造方法
は、例えば特開昭６２−２１６３３９号公報に示されて
いるように（図２参照）、半導体素子を形成した半導体
基板１上に例えばアルミニウムにＳｉ等を含ませた導電
材料によりボンディングパッド部Ｂを含む導電膜２を形
成し、その後この導電膜２を熱処理してシンタリングす
る。さらに、半導体基板１上に絶縁膜３を形成し、この
絶縁膜３のボンディングパッド部Ｂ上の部分を除去して
開口部３ａを設け、露出したボンディングパッド部Ｂ上
に第２の導電材料によるバリア膜４を形成し、このバリ
ア膜４上にワイヤボンディングにより金線５を接続し、
外部電極と接続させるようにしていた。2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device of this type is, for example, as disclosed in Japanese Unexamined Patent Publication No. 62-216339 (see FIG. 2), for example, on a semiconductor substrate 1 on which a semiconductor element is formed. The conductive film 2 including the bonding pad portion B is formed of a conductive material containing Si or the like in aluminum, and then the conductive film 2 is heat-treated and sintered. Further, an insulating film 3 is formed on the semiconductor substrate 1, a portion of the insulating film 3 on the bonding pad portion B is removed to provide an opening 3a, and the exposed bonding pad portion B is covered with the second conductive material. A barrier film 4 is formed, and a gold wire 5 is connected to the barrier film 4 by wire bonding,
It was connected to an external electrode.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記従来の製
造方法によれば、導電膜２の熱処理時に、図２に示すよ
うに、導電膜２に高さ２μｍ程度のアルミニウムのいわ
ゆるヒロックと言われる突起６が生じ、バリア膜４では
この突起６をカバーしきれず、突起６はバリア膜４上に
露出する。そして、突起６の生じたバリア膜４上に金線
によるワイヤボンディングを行うと、金線５と突起６の
アルミニウムとが反応して脆弱な金属間化合物７を生成
する。この金属間化合物７のために金線５のボンディン
グパッド部Ｂへの接着強度が低下して金線のはがれ等の
不良が生じ、ボンディング部分の信頼性を低下させると
いう問題がある。このような突起６の影響を避けるため
にはバリア膜４の厚みを突起の高さ以上にする必要があ
り、このようにすると材料費が高くなると共に製造時間
も長くなる。しかも、この突起６の大きさは一様ではな
くこれに応じてバリア膜４の厚みをコントロールするこ
とは事実上困難である。本発明は上記問題に対処するた
めになされたもので、その目的はボンディングパッド部
においてアルミニウム又はアルミニウム合金からなる導
電膜に突起の生じないようにした半導体装置の製造方法
を提供することを目的とする。However, according to the above-mentioned conventional manufacturing method, when heat treatment of the conductive film 2 is performed, so-called hillock of aluminum having a height of about 2 μm is formed on the conductive film 2 as shown in FIG. Protrusions 6 are formed, and the barrier film 4 cannot completely cover the protrusions 6, and the protrusions 6 are exposed on the barrier film 4. Then, when wire bonding with a gold wire is performed on the barrier film 4 in which the protrusion 6 is formed, the gold wire 5 and the aluminum of the protrusion 6 react with each other to form a brittle intermetallic compound 7. Due to the intermetallic compound 7, there is a problem that the adhesion strength of the gold wire 5 to the bonding pad portion B is reduced and a defect such as peeling of the gold wire occurs and the reliability of the bonding portion is reduced. In order to avoid such an influence of the protrusions 6, it is necessary to make the thickness of the barrier film 4 equal to or more than the height of the protrusions, which increases the material cost and the manufacturing time. Moreover, the size of the protrusions 6 is not uniform, and it is practically difficult to control the thickness of the barrier film 4 accordingly. The present invention has been made to address the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device in which a conductive film made of aluminum or an aluminum alloy does not have protrusions in a bonding pad portion. To do.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
に本発明の構成上の特徴は、半導体基板上にアルミニウ
ム又はアルミニウム合金によるボンディングパッド部を
含む第１導電膜を形成する第１導電膜形成行程と、第１
導電膜上にバリア性の高い導電材料による第２導電膜を
形成する第２導電膜形成行程と、第１導電膜及び第２導
電膜の設けられた半導体基板を熱処理する熱処理行程
と、熱処理された半導体基板の表面に絶縁膜を形成する
絶縁膜形成行程と、ボンディングパッド部上の絶縁膜を
選択的に除去する絶縁膜除去行程と、絶縁膜の除去によ
り露出した第２導電膜上に金との接合性の良い導電材料
からなる第３導電膜を形成する第３導電膜形成行程と、
第３導電膜上に金線を接合する金線接合行程とを設けた
ことにある。To achieve the above object, a structural feature of the present invention is that a first conductive film is formed on a semiconductor substrate, the first conductive film including a bonding pad portion made of aluminum or aluminum alloy. Forming process, first
A second conductive film forming step of forming a second conductive film of a conductive material having a high barrier property on the conductive film; a heat treatment step of heat-treating a semiconductor substrate provided with the first conductive film and the second conductive film; An insulating film forming step of forming an insulating film on the surface of the semiconductor substrate, an insulating film removing step of selectively removing the insulating film on the bonding pad portion, and a gold film on the second conductive film exposed by removing the insulating film. A third conductive film forming step of forming a third conductive film made of a conductive material having good bonding property with
And a gold wire bonding step for bonding the gold wire on the third conductive film.
【０００５】[0005]
【発明の作用・効果】上記のように構成した本発明にお
いては、アルミニウム又はアルミニウム合金による第１
導電膜上にバリア性の高い第２導電膜を形成した後に半
導体基板は熱処理されるので、第２導電膜が第１導電膜
によるヒロックの発生を防止する。また、金線との接合
性の良い第３導電膜を第２導電膜上に形成し、この第３
導電膜上に金線を接着するようにしたので、金線は第３
導電膜に強固に接着されると共に第２導電膜によって第
１導電膜との反応も防止される。これにより、ボンディ
ング部分の信頼性が補償される。特に、ボンディングパ
ッド部が高温になり、金−アルミニウムの金属間化合物
の成長が促進され易い高温用半導体装置に対して本発明
を適用することにより、ボンディング部分の信頼性を高
める効果が一層有効に発揮される。また、第２導電膜の
膜厚は、第１導電膜のアルミニウムの成長を抑制するこ
とができる所定の厚さにすればよく、不必要に厚くする
必要はないので、材料費の削減及び製造時間の短縮化を
図ることができる。According to the present invention having the above-described structure, the first member made of aluminum or aluminum alloy is used.
Since the semiconductor substrate is heat-treated after forming the second conductive film having a high barrier property on the conductive film, the second conductive film prevents the generation of hillocks due to the first conductive film. In addition, a third conductive film having good bondability with the gold wire is formed on the second conductive film, and the third conductive film is formed.
Since the gold wire is adhered on the conductive film, the gold wire is the third
The second conductive film prevents the reaction with the first conductive film while being firmly adhered to the conductive film. Thereby, the reliability of the bonding portion is compensated. In particular, by applying the present invention to a high-temperature semiconductor device in which the temperature of the bonding pad portion becomes high and the growth of the gold-aluminum intermetallic compound is easily promoted, the effect of improving the reliability of the bonding portion becomes more effective. To be demonstrated. Further, the film thickness of the second conductive film may be set to a predetermined thickness that can suppress the growth of aluminum of the first conductive film, and it is not necessary to unnecessarily increase the thickness, so that the material cost can be reduced and the manufacturing can be performed. The time can be shortened.
【０００６】[0006]
【実施例】以下、本発明の一実施例を図面を用いて説明
すると、図１は本発明に係る製造方法を用いて半導体装
置のボンディングパッド部を形成する行程を模式的に示
している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a step of forming a bonding pad portion of a semiconductor device by using the manufacturing method according to the present invention.
【０００７】まず、トランジスタ等の形成されたシリコ
ン半導体基板１０上に、アルミニウムにＳｉを含ませた
導電膜（以下、アルミニウム膜と記す）１１をスパッタ
リング法等を用いて１〜２μｍの厚さに形成する。な
お、アルミニウム膜１１の材料としては、アルミニウム
にＳｉを含ませたものに代えてアルミニウムにＳｉ−Ｃ
ｕ，Ｓｉ−Ｔｉ，Ｃｕ，Ｔｉ等を含ませるようにしても
よく、またアルミニウム単体を用いるようにしてもよ
い。アルミニウム膜１１の設けられたシリコン半導体基
板１０上に、バリア性の高い導電材料例えばＴｉＮ，Ｔ
ｉＷ等による第１バリア膜１２をスパッタリング法等に
より０．２〜０．５μｍの厚さに形成する。これらのア
ルミニウム膜１１及び第１バリア膜１２の形成において
は、両膜１１，１２を同一装置により連続的に形成して
もよいし、別々に行ってもよい。次に、これらのアルミ
ニウム膜１１及び第１バリア膜１２をリソグラフィ技術
及びエッチング技術により導体配線及びボンディングパ
ッド部Ｂからなる所定パターンに形成する（図１(ａ)参
照）。なお、第１バリア膜１２に関してはボンディング
パッド部Ｂ上にのみ設けるようにしてもよい。First, a conductive film (hereinafter referred to as an aluminum film) 11 containing Si in aluminum is formed on a silicon semiconductor substrate 10 on which a transistor or the like is formed to a thickness of 1 to 2 μm by using a sputtering method or the like. Form. As the material of the aluminum film 11, instead of the material containing Si in aluminum, Si-C in aluminum is used.
u, Si-Ti, Cu, Ti, etc. may be included, or a simple substance of aluminum may be used. On the silicon semiconductor substrate 10 provided with the aluminum film 11, a conductive material having a high barrier property such as TiN, T
The first barrier film 12 of iW or the like is formed to a thickness of 0.2 to 0.5 μm by a sputtering method or the like. In forming the aluminum film 11 and the first barrier film 12, both films 11 and 12 may be continuously formed by the same apparatus or may be separately formed. Next, the aluminum film 11 and the first barrier film 12 are formed into a predetermined pattern including the conductor wiring and the bonding pad portion B by the lithography technique and the etching technique (see FIG. 1A). The first barrier film 12 may be provided only on the bonding pad portion B.
【０００８】次に、アルミニウム膜１１及び第１バリア
膜１２が形成されたシリコン半導体基板１０を、４５０
℃にて熱処理して、アルミニウム膜１１をシンタリング
する。このとき、アルミニウム膜１１は第１バリア膜１
２によって表面が被覆されて成長が抑えられているの
で、ヒロック等の突起が形成されることはない。また、
第１バリア膜１２に被覆されることにより、水分等によ
る電気・化学反応であるアルミニウム膜１１におけるエ
レクトロマイグレーションの発生が抑制されるので、ア
ルミニウム膜１１の信頼性が高められる。なお、第１バ
リア膜１１の膜厚はアルミニウム膜の成長を抑制するこ
とができる所定の厚さ（例えば０．２〜０．５μｍ）に
すればよく、不必要に厚くする必要はないので、材料費
の削減及び製造時間の短縮化を図ることができる。Next, the silicon semiconductor substrate 10 having the aluminum film 11 and the first barrier film 12 formed thereon is
The aluminum film 11 is sintered by heat treatment at ℃. At this time, the aluminum film 11 is the first barrier film 1
Since the surface is covered with 2 and growth is suppressed, protrusions such as hillocks are not formed. Also,
By being covered with the first barrier film 12, the occurrence of electromigration in the aluminum film 11, which is an electric / chemical reaction due to moisture or the like, is suppressed, so that the reliability of the aluminum film 11 is improved. The first barrier film 11 may have a predetermined thickness (for example, 0.2 to 0.5 μm) capable of suppressing the growth of the aluminum film, and does not need to be unnecessarily thick. It is possible to reduce the material cost and the manufacturing time.
【０００９】前記熱処理されたシリコン半導体基板１０
の表面に保護膜としてＣＶＤ法により例えばＰＳＧ膜１
３を膜厚約１．０μｍに形成する。このＰＳＧ膜１３の
ボンディングパッド部Ｂ上の部分をリソグラフィ技術及
びエッチング技術により選択的に除去し、開口部１３ａ
を設ける（図１(ｂ)参照）。次に、開口部１３ａの設け
られたＰＳＧ膜１３上に、金線との接合性の良い金属例
えばＴｉ−Ｎｉ−Ａｕの組合せの第２バリア膜１４をス
パッタリング法等により厚さ０．４〜１．０μｍに形成
する（図１(ｃ)参照）。次に、第２バリア膜１４をリソ
グラフィ技術及びエッチング技術によりボンディングパ
ッド部Ｂを除いて選択的に除去する（図１(ｄ)参照）。
このように形成されたボンディングパッド部Ｂに、熱圧
着法等のワイヤボンディング技術を用いて金線１５を接
着させる（図１(ｅ)参照）。The heat-treated silicon semiconductor substrate 10
As a protective film on the surface of, for example, a PSG film 1
3 to a film thickness of about 1.0 μm. A portion of the PSG film 13 on the bonding pad portion B is selectively removed by a lithography technique and an etching technique to form an opening 13a.
Are provided (see FIG. 1B). Next, on the PSG film 13 provided with the opening 13a, a second barrier film 14 made of a metal having a good bondability with a gold wire, for example, a combination of Ti—Ni—Au, is formed to a thickness of 0.4 to 0.4 by a sputtering method or the like. It is formed to 1.0 μm (see FIG. 1C). Next, the second barrier film 14 is selectively removed except the bonding pad portion B by the lithography technique and the etching technique (see FIG. 1D).
The gold wire 15 is bonded to the bonding pad portion B thus formed by using a wire bonding technique such as a thermocompression bonding method (see FIG. 1E).
【００１０】これにより、金線１５は接合性の良い第２
バリア膜１４に強固に接着されるとともに、第１バリア
膜１２によりアルミニウム膜１１と完全に遮断されるの
で、アルミニウム膜１１と反応することはない。したが
って、ボンディング部分に接合の信頼性を低下させる金
−アルミニウムの金属間化合物が生成されることもな
く、ワイヤボンディングの信頼性が補償される。特に、
上記製造方法を、ワイヤボンディング部分が高温にな
り、金−アルミニウムの金属間化合物の成長が促進され
易い高温用半導体装置に適用することにより、ワイヤボ
ンディング部分の信頼性を高める効果が一層有効に発揮
される。As a result, the gold wire 15 has a good second bonding property.
Since it is firmly adhered to the barrier film 14 and is completely shielded from the aluminum film 11 by the first barrier film 12, it does not react with the aluminum film 11. Therefore, the gold-aluminum intermetallic compound that deteriorates the reliability of the bonding is not generated in the bonding portion, and the reliability of the wire bonding is compensated. In particular,
By applying the above-described manufacturing method to a high-temperature semiconductor device in which the temperature of the wire bonding portion becomes high and the growth of the gold-aluminum intermetallic compound is easily promoted, the effect of enhancing the reliability of the wire bonding portion is more effectively exhibited. To be done.
【００１１】なお、上記実施例においては、アルミニウ
ム膜１１及び第１バリア膜１２のパターン形成後にシリ
コン半導体基板１０の熱処理を行っているが、アルミニ
ウム膜１１及び第１バリア膜１２が形成されたシリコン
半導体基板１０を熱処理した後に両膜１１，１２のパタ
ーン形成を行うようにしてもよい。また、上記実施例に
おいては、シリコン半導体基板１０を用いた場合につい
て説明しているが、その他の半導体基板上にアルミニウ
ム又はアルミニウム合金によるボンディングパッド部を
形成する場合に本発明を適用してもよい。In the above embodiment, the heat treatment of the silicon semiconductor substrate 10 is performed after the pattern of the aluminum film 11 and the first barrier film 12 is formed. However, the silicon film having the aluminum film 11 and the first barrier film 12 is formed. The both substrates 11 and 12 may be patterned after the semiconductor substrate 10 is heat-treated. In addition, although the case where the silicon semiconductor substrate 10 is used has been described in the above-described embodiments, the present invention may be applied to the case where a bonding pad portion made of aluminum or an aluminum alloy is formed on another semiconductor substrate. .
【図１】 本発明の一実施例に係る層間絶縁膜を形成す
る製造行程を示す模式図である。FIG. 1 is a schematic view showing a manufacturing process for forming an interlayer insulating film according to an embodiment of the present invention.
【図２】 従来例に係るボンディングパッド部の不良発
生を説明する説明図である。FIG. 2 is an explanatory diagram illustrating occurrence of a defect in a bonding pad portion according to a conventional example.
１０…シリコン半導体基板、１１…アルミニウム膜、１
２…第１バリア膜、１３…ＰＳＧ膜、１４…第２バリア
膜、１５…金線、Ｂ…ボンディングパッド部。10 ... Silicon semiconductor substrate, 11 ... Aluminum film, 1
2 ... 1st barrier film, 13 ... PSG film, 14 ... 2nd barrier film, 15 ... Gold wire, B ... Bonding pad part.
Claims (1)
ニウム合金によるボンディングパッド部を含む第１導電
膜を形成する第１導電膜形成行程と、 前記第１導電膜上にバリア性の高い導電材料による第２
導電膜を形成する第２導電膜形成行程と、 前記第１導電膜及び第２導電膜の設けられた半導体基板
を熱処理する熱処理行程と、 前記熱処理された半導体基板の表面に絶縁膜を形成する
絶縁膜形成行程と、 前記ボンディングパッド部上の前記絶縁膜を選択的に除
去する絶縁膜除去行程と、 前記絶縁膜の除去により露出した第２導電膜上に金との
接合性の良い導電材料からなる第３導電膜を形成する第
３導電膜形成行程と、 前記第３導電膜上に金線を接合する金線接合行程とを設
けたことを特徴とする半導体装置の製造方法。1. A first conductive film forming step of forming a first conductive film including a bonding pad portion made of aluminum or aluminum alloy on a semiconductor substrate, and a second conductive material having a high barrier property on the first conductive film.
A second conductive film forming step of forming a conductive film; a heat treatment step of heat treating the semiconductor substrate provided with the first conductive film and the second conductive film; and an insulating film formed on the surface of the heat treated semiconductor substrate. Insulating film forming step, insulating film removing step of selectively removing the insulating film on the bonding pad portion, and conductive material having good bondability with gold on the second conductive film exposed by removing the insulating film. And a gold wire bonding step of bonding a gold wire on the third conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4346422A JPH06196526A (en) | 1992-12-25 | 1992-12-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4346422A JPH06196526A (en) | 1992-12-25 | 1992-12-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06196526A true JPH06196526A (en) | 1994-07-15 |
Family
ID=18383316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4346422A Pending JPH06196526A (en) | 1992-12-25 | 1992-12-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06196526A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100421043B1 (en) * | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein |
| US6784545B2 (en) | 2002-04-12 | 2004-08-31 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device having pad electrode connected to wire |
| US6794732B2 (en) | 2001-07-25 | 2004-09-21 | Rohn Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2010157683A (en) * | 2008-12-03 | 2010-07-15 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US7759803B2 (en) | 2001-07-25 | 2010-07-20 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2016028410A (en) * | 2014-07-09 | 2016-02-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
-
1992
- 1992-12-25 JP JP4346422A patent/JPH06196526A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100421043B1 (en) * | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein |
| US6794732B2 (en) | 2001-07-25 | 2004-09-21 | Rohn Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7244635B2 (en) | 2001-07-25 | 2007-07-17 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7759803B2 (en) | 2001-07-25 | 2010-07-20 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US8049343B2 (en) | 2001-07-25 | 2011-11-01 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US6784545B2 (en) | 2002-04-12 | 2004-08-31 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device having pad electrode connected to wire |
| JP2010157683A (en) * | 2008-12-03 | 2010-07-15 | Renesas Technology Corp | Semiconductor integrated circuit device |
| JP2016028410A (en) * | 2014-07-09 | 2016-02-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
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