JPH0385730A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain production of dust due to a contact with a carrier, etc., by connecting a ground wiring corresponding to a ground wiring pattern with a wafer electrically and by applying a conductive film to a light screening region on a wafer whereto a pattern is not transcribed. CONSTITUTION:In a semiconductor wafer 12, a region whereto a pattern of a product pattern region 1 of reticle is transcribed becomes a product pellet part 9; a region whereto a pattern of a TEG pattern region 3 is transcribed becomes a TEG pellet part 11; a region whereto a scribe pattern region 2 is transcribed becomes a scribe region 10; and a region whereto a ground wiring pattern 5 is transcribed becomes a ground wiring 8. In a peripheral region of a wafer 12, an Al film 7 is formed. In the outermost pattern of a pattern transcription region, the ground wiring 8 is connected to the Al film 7; thereby, the semiconductor wafer 12 is electrically connected to the Al film 7 through the ground wiring 8. Then, a passivation film is formed all over with a ring for fixing the semiconductor wafer of a plasma CVD device being brought into contact with the Al film 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device in which a plasma CVD film is formed on a wiring layer of a semiconductor wafer using a plasma CVD apparatus.

[Prior art] When forming an insulating film on a semiconductor wafer, plasma C
When the VD method is used, film formation can be performed at a lower temperature than a method that utilizes a thermal reaction such as the normal temperature/low pressure CVD method. For this reason, plasma CVD apparatuses are used for forming passivation films for protecting wiring layers, etc.

By the way, when forming a padded vane film using a plasma CVD apparatus, it is necessary to set the semiconductor wafer at a ground potential to avoid accumulation of electric charges on the semiconductor wafer (hereinafter referred to as charge-up).

Conventionally, in order to prevent this charge-up, a dummy product portion is provided at the peripheral edge of the semiconductor wafer. In this dummy product section, wirings such as A and ff are formed, and these wirings are connected to the semiconductor wafer through contacts. Then, the semiconductor wafer is processed by plasma CVD.
When fixing the dummy product to the device, the wafer fixing ring of the plasma CVD device is brought into contact with this dummy product. Then, since this wafer fixing ring is electrically connected to the ground, the semiconductor wafer is maintained at the ground potential even during the formation of the CVD film. Thereby, charge-up of the semiconductor wafer can be avoided and a CVD film in good condition can be formed.

[Problems to be Solved by the Invention] However, in the conventional method described above, when the dummy product part comes into contact with the carrier when the semiconductor wafer is transported by the wafer carrier, the wiring etc. of the dummy product part peel off and become dust. There is a problem in that this dust adheres to product parts on the wafer, reducing the manufacturing yield of semiconductor devices.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the generation of dust and improve the manufacturing yield of semiconductor devices.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device including a predetermined wiring formation pattern in a predetermined region of an insulating film on a semiconductor wafer, and a light-shielding pattern provided around the wiring formation pattern. a step of transferring the pattern using a reticle having a ground wiring pattern adjacent to the inside of the light-shielding area; and forming predetermined wiring and ground wiring on the insulating film based on the pattern; a step of depositing a conductor on the light-shielding region on the semiconductor wafer to form a conductive film;
forming a plasma CVD film on the semiconductor wafer by supporting the semiconductor wafer with a jig that contacts the conductive film, and forming the ground wiring so as to be electrically connected to the semiconductor wafer. It is characterized by

[Operation] In the present invention, first, a reticle pattern is transferred onto a semiconductor wafer. In this case, the reticle is provided with a ground wiring pattern adjacent to a light shielding area provided around the wiring formation pattern. Therefore, in the outermost pattern of the patterns transferred by this reticle, the pattern area to which the ground wiring pattern is transferred is connected to the peripheral area of the wafer to which no pattern is transferred. Next, conductive wiring and ground wiring are formed based on the transferred wiring pattern and ground wiring pattern, but at this time, the ground wiring is electrically connected to the wafer. To do this, for example, a contact hole is opened in the insulating film in the ground wiring formation area, and a conductor is deposited to fill the contact hole after the pattern for the ground wiring is transferred, thereby forming the ground wiring. do it. Further, a conductor is applied to a light-shielding region at the periphery of the wafer to form a conductive film. Thereby, the conductive film on the peripheral edge of the semiconductor wafer is electrically connected to the semiconductor wafer via the ground wiring.

When forming a plasma CVD film, if a grounded fixing jig of a CVD apparatus is brought into contact with the peripheral conductive film of the semiconductor wafer to support the semiconductor wafer, the wafer is It is held at ground potential and can avoid charge-up of the semiconductor wafer.

In the present invention, since the peripheral edge of the semiconductor wafer is not a thin wiring but a conductive film deposited over a relatively wide area,
Generation of dust is suppressed when the wafer is transported and fixed to the device. This improves the manufacturing yield of semiconductor devices.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing a reticle used in a first embodiment of the present invention. This reticle is provided with a product pattern area 1 in the center in which a predetermined wiring pattern is formed. A scribe pattern area 2 is provided around this product pattern area 1, and above and below the product pattern area 1 with this scribe pattern area 2 in between, patterns used for process improvement, etc. are formed. Test Element
Group) pattern area 3 is provided. The ground wiring pattern 5 is a rectangular pattern provided in a part of this TEG pattern area 3, and is provided at a position adjacent to and connected to the light shielding area 4 provided at the periphery of the reticle. There is.

First, a semiconductor wafer is patterned using this reticle, and a predetermined wiring pattern is formed using a conductive material.

At this time, a predetermined wiring layer and interlayer insulation n! are formed on the semiconductor wafer to be patterned. Contact holes are formed at each position. The reticle pattern is moved in parallel and repeatedly transferred onto this wafer. In this case, the reticle pattern is not transferred to the peripheral region of the wafer.

Next, Af wiring is formed based on this transfer pattern. Furthermore, AI is applied to the peripheral edge of the wafer where the reticle pattern is not transferred.

FIG. 2 is a plan view showing a semiconductor wafer on which each pattern is formed in this way, and FIG. 3 is a partially enlarged view showing the ground wiring pattern portion surrounded by the two-dot chain line ■ in FIG. FIG. 4 is a sectional view taken along the line IV--IV in FIG. 3.

As shown in FIG. 2, on the semiconductor wafer 12, the area to which the pattern of the product pattern area 1 of the reticle is transferred becomes the product pellet part 9, and the area to which the pattern of the TEG pattern area 3 is transferred becomes the TEG pellet part 11. The area to which the scribe pattern area 2 has been transferred becomes the scribe area IO, and the area to which the ground wiring pattern 5 has been transferred becomes the ground wiring 8. Furthermore, an AI film 7 is formed in the peripheral region of the wafer 12.

In this case, as shown in FIG. 4, predetermined elements are formed on the semiconductor wafer 12, and a field oxide film 14, a predetermined wiring layer (not shown), and an interlayer insulating film 15 are formed on the semiconductor wafer 12. etc. are formed. A contact hole 6 that reaches the semiconductor wafer 12 is formed in a predetermined region of the interlayer insulating film 15, and the ground wiring 8 is connected to the semiconductor wafer 12 through this contact hole 6. In addition, in the outermost pattern of the pattern transfer area, the ground wiring 8 is connected to the A1 film 7, so that the semiconductor wafer 12 is connected to the A1 film 7 via the ground wiring 8.
It is electrically connected to the membrane 7.

Next, a passivation film is formed on the entire surface. At this time, a ring for fixing the semiconductor wafer of the plasma CVD apparatus is attached to the AI! on the wafer 12. This is done by bringing it into contact with the membrane 7. This ring is electrically connected to the ground of the CVD apparatus, thereby allowing the wafer 12 to be at ground potential.

In this embodiment, as described above, the semiconductor wafer 12 is connected to the ground of the CVD apparatus to form the CVD film.
Charge-up during formation of the passivation film can be avoided. Further, since no wiring or the like is formed in the portion that contacts the ring, generation of dust can be suppressed.

FIG. 5 is a plan view showing a reticle used in a second embodiment of the invention.

For example, if the manufacturing yield of the product has been sufficiently improved, T
There is no need to manufacture EG pellets. Therefore, the reticle used in this example does not have a TEG pattern area.

In this embodiment, the scribe pattern area 2 provided around the product pattern 9 area 21 of the reticle is
A grounding wiring pattern 25 is provided in a part of 2. In this case as well, the ground wiring pattern 25 is connected to the light-shielding region 24 at the periphery of the reticle, as in the first embodiment.

In this embodiment, a wiring pattern is transferred and formed on a semiconductor wafer using the above-mentioned reticle, but since the following steps are substantially the same as those in the first embodiment, detailed explanation thereof will be omitted.

In this example, since no TEG pattern is formed, areas other than the light-shielding area on the semiconductor wafer can be patterned using only the product pellets. For this reason, the first
In addition to obtaining the same effect as in the embodiment, wafer 1
The number of products per sheet increases.

[Effects of the Invention] As explained above, according to the present invention, a predetermined pattern is transferred onto a semiconductor wafer by a reticle provided with a ground wiring pattern adjacent to a light shielding area, and a pattern corresponding to the ground wiring pattern is transferred onto the semiconductor wafer. Since the grounding wiring 10- is electrically connected to the wafer and a conductive film is applied to a light-shielding region on the wafer where no pattern is transferred, a plasma CVD film can be formed while avoiding charge-up. Further, since the conductive film can be formed over a relatively wide area, generation of dust due to contact with carriers, etc. is suppressed, and the manufacturing yield of semiconductor devices is improved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a reticle used in the first embodiment of the present invention, FIG. 2 is a plan view showing a semiconductor wafer on which a pattern is formed, and FIG. FIG. 4 is a sectional view taken along the line ■-■ in FIG. 3; FIG. 5 is a plan view showing a reticle used in the second embodiment of the present invention. It is. 1.21; Product pattern area, 2, 22; Scribe pattern area, 3; TEG pattern area, 4.24; Light shielding area, 5.25; Ground wiring pattern, 6; Contact hole, 7; Af film, 8: Ground wiring, 9; Product pellet part, 10; Scribe area, 11; TEG pellet part,
12; semiconductor wafer, 14; field oxide film, 15:
interlayer insulation film

Claims (1)

[Claims] (1) A reticle having a predetermined wiring formation pattern in a predetermined region of an insulating film on a semiconductor wafer, a light-shielding area provided around this wiring-forming pattern, and a ground wiring pattern adjacent to the inside of this light-shielding area. forming a predetermined wiring and a ground wiring on the insulating film based on the pattern, and depositing a conductor on the light-shielding region on the semiconductor wafer to form a conductive film. and forming a plasma CVD film on the semiconductor wafer by supporting the semiconductor wafer with a jig in contact with the conductive film, the ground wiring being electrically connected to the semiconductor wafer. A method for manufacturing a semiconductor device, characterized in that it is formed by connecting it.