JPH0469948A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH0469948A JPH0469948A JP18210390A JP18210390A JPH0469948A JP H0469948 A JPH0469948 A JP H0469948A JP 18210390 A JP18210390 A JP 18210390A JP 18210390 A JP18210390 A JP 18210390A JP H0469948 A JPH0469948 A JP H0469948A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- scribe
- semiconductor device
- etching
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特にウェハプロセスで形成され
る集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly an integrated circuit formed by a wafer process.
本発明は、半導体装置の製造方法において、スクライブ
領域に絶縁膜を形成し、シリコン基板が直接露出しない
構造をとる事により、スクライブ領域のレジスト残りに
より生じるA1エツチング〔従来の技術〕
従来、スクライブ領域を形成する方法として、第2図に
あるように、スクライブ領域にはシリコン基板が露出す
るような工程が用いられている。The present invention provides a method for manufacturing a semiconductor device in which an insulating film is formed in the scribe region and a structure is adopted in which the silicon substrate is not directly exposed, thereby eliminating A1 etching caused by resist residue in the scribe region [prior art]. As shown in FIG. 2, a process is used in which the silicon substrate is exposed in the scribe area.
しかし、前述の従来の技術においては、プロセスの各工
程においてシリコン基板が露出するようにエツチング加
工を行なう為、スクライブ領域のシリコン基板が各エツ
チング工程で徐々にエツチングされてい(。特に、スク
ライブ端部においては絶縁膜の端部がせっぴ状になるほ
どシリコン基板がエツチングされてしまう。このような
状況の中で、次工程特にA1配線形成時におけるレジス
ト露光時において、前述のスクライブ端部に塗布された
レジストは、十分に露光されない事がある。その結果と
して、次工程のレジスト剥離工程において、このAlが
離脱して工0チップ表面に付着し、信頼性上の問題を発
生させる事が考えられる。However, in the above-mentioned conventional technology, etching is performed to expose the silicon substrate in each step of the process, so the silicon substrate in the scribe area is gradually etched in each etching step (particularly at the scribe end). In this case, the silicon substrate is etched to such an extent that the edges of the insulating film become sparse.Under these circumstances, during the next process, especially during resist exposure during the formation of the A1 wiring, the silicon substrate is coated on the scribe edges as described above. The exposed resist may not be exposed sufficiently.As a result, in the next resist stripping process, this Al may detach and adhere to the surface of the chip, causing reliability problems. .
本発明は、このような従来の半導体装置の問題点を解決
するもので、その目的とするところは、。The present invention is intended to solve these problems of conventional semiconductor devices, and its objectives are as follows.
より安定した信頼性の高い半導体装置を提供するところ
にある。The goal is to provide more stable and reliable semiconductor devices.
本発明の半導体装置の製造方法は、シリコンウェハのス
クライブ領域において、スクライブ表面にシリコン基板
を露出させない工程から成る事を特徴とする。The method for manufacturing a semiconductor device of the present invention is characterized by comprising a step in which the silicon substrate is not exposed on the scribe surface in the scribe region of the silicon wafer.
第1図は、本発明の実施例における半導体装置の製造工
程に従う断面図である。FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
まず、第1図(α)にあるように、比抵抗10(Ω−m
)のN型シリコン基板100上に、二酸化珪累からなる
絶縁膜1・01を通常の熱酸化法で形成する。First, as shown in Figure 1 (α), the specific resistance is 10 (Ω-m
) An insulating film 1.01 made of silicon dioxide is formed by a normal thermal oxidation method on an N-type silicon substrate 100.
次に、第1図Cb)にあるように、A’1102を通常
の蒸着あるいはスパッタリングにより形成させる。Next, as shown in FIG. 1Cb), A'1102 is formed by conventional vapor deposition or sputtering.
次に、第1図(c)にあるように、スクライブ領域には
前記で形成したA1102は必要ない為エツチングによ
り除去する。Next, as shown in FIG. 1(c), since the A1102 formed above is not needed in the scribe area, it is removed by etching.
次に、第1図(d)にあるように、前記パターン上にパ
ッシベーション膜105を形成する。Next, as shown in FIG. 1(d), a passivation film 105 is formed on the pattern.
以上の工程を経てスクライブ領域が形成される。本実施
例においては、スクライブ領域に絶縁膜が一層残す構造
を採用したが、多層配線構造により層間絶縁膜を有する
場合は、この層間絶縁膜も残す事も有効である。但し、
パッシベーション膜を残す事については、ダイシング時
にパッシベーションのクラックによりIOチップの信頼
性に影響が出る事が考えられる為に避けるべきである。A scribe area is formed through the above steps. In this embodiment, a structure is adopted in which a layer of the insulating film is left in the scribe region, but if a multilayer wiring structure has an interlayer insulating film, it is also effective to leave this interlayer insulating film as well. however,
Leaving a passivation film should be avoided since cracks in the passivation during dicing may affect the reliability of the IO chip.
以上述べたように、本発明によれば、スクライブ領域の
A1残りによる不良を防止する対策として、絶縁膜を形
成しスクライブ表面にシリコン基板が露出しないような
工程を経ることにより、スクライブ領域のシリコン基板
が深くエツチングされるのを防ぐ事ができる。その結果
、A1等のエツチング残りを防・ぎ、次工程でその人1
等が20チツプ上に付着して起こす不良を低減する事が
でき、より信頼性の高い半導体装置を提供する事が出来
る。As described above, according to the present invention, as a measure to prevent defects caused by remaining A1 in the scribe area, silicon in the scribe area is This can prevent the substrate from being deeply etched. As a result, it prevents etching residue such as A1, and the next process
It is possible to reduce defects caused by adhesion of such substances on the 20-chip, and it is possible to provide a more reliable semiconductor device.
第1図(α)〜(d)は、本発明による実施例の半導体
装置の製造工程の断面図である。
第2図は、従来の半導体装置の構造を示す断面図であ、
る。
100・・・・・・・・・N型シリコン基板101・・
・・・・・・・絶縁膜
102 ・・・・・・・・・ A 1
103・・・・・・・・・パッシベーション膜(cl)
第2図FIGS. 1(α) to 1(d) are cross-sectional views of the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device.
Ru. 100...N-type silicon substrate 101...
...... Insulating film 102 ...... A 1 103 ...... Passivation film (cl) Fig. 2
Claims (1)
ブ表面にシリコン基板を露出させない工程から成る事を
特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising a step in which a silicon substrate is not exposed on the scribe surface in a scribe region of a silicon wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18210390A JPH0469948A (en) | 1990-07-10 | 1990-07-10 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18210390A JPH0469948A (en) | 1990-07-10 | 1990-07-10 | Manufacturing method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0469948A true JPH0469948A (en) | 1992-03-05 |
Family
ID=16112393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18210390A Pending JPH0469948A (en) | 1990-07-10 | 1990-07-10 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0469948A (en) |
-
1990
- 1990-07-10 JP JP18210390A patent/JPH0469948A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0469948A (en) | Manufacturing method of semiconductor device | |
JP2991388B2 (en) | Method for manufacturing semiconductor device | |
JPH0442559A (en) | Manufacture of semiconductor device | |
JPH09199588A (en) | Manufacture of semiconductor device | |
JPH09129524A (en) | Method for manufacturing semiconductor device | |
JPH0587973B2 (en) | ||
JPS59115542A (en) | Manufacture of semiconductor device | |
JPH04179124A (en) | Manufacture of semiconductor device | |
JPS60785B2 (en) | Manufacturing method of MOS type semiconductor device | |
JPH0684908A (en) | Semiconductor device and its manufacturing method | |
JPH02151052A (en) | Manufacture of semiconductor device | |
JPS6010753A (en) | Manufacture of semiconductor device | |
JPH01135041A (en) | Manufacture of semiconductor device provided with contact part | |
JPS59211249A (en) | Wirings forming method | |
JPH02194530A (en) | Manufacturing method of semiconductor device | |
JPH05121561A (en) | Manufacture of semiconductor device | |
JPS6054468A (en) | Manufacture of semiconductor integrated circuit device | |
JPH0457342A (en) | Manufacture of semiconductor device | |
JPH05152444A (en) | Manufacture of semiconductor device | |
JPH0414851A (en) | Manufacturing method of semiconductor device | |
JPH01123434A (en) | Semiconductor device with wiring layer | |
JPH05160126A (en) | Formation of multilayer wiring | |
JPS5852828A (en) | Manufacture of semiconductor device | |
JPH03248533A (en) | Semiconductor integrated circuit device | |
JPS61216344A (en) | Manufacture of semiconductor device |