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JPH02194530A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPH02194530A
JPH02194530A JP1014275A JP1427589A JPH02194530A JP H02194530 A JPH02194530 A JP H02194530A JP 1014275 A JP1014275 A JP 1014275A JP 1427589 A JP1427589 A JP 1427589A JP H02194530 A JPH02194530 A JP H02194530A
Authority
JP
Japan
Prior art keywords
film
insulating film
interlayer insulating
polyimide
polyimide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1014275A
Other languages
Japanese (ja)
Inventor
Tatsuya Mise
辰也 三瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1014275A priority Critical patent/JPH02194530A/en
Publication of JPH02194530A publication Critical patent/JPH02194530A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To prevent a bonding pad from being stripped off and to easily measure a film thickness of an interlayer insulating film by a method wherein a lower layer of the bonding pad, a scribe region and an SOG film are isolated by using a polyimide film. CONSTITUTION:A field oxide film 2 is formed on the surface of a semiconductor substrate 1; an alignment pattern 3 is formed in a scribe region in between; an insulating film 4 is formed on the surface of the oxide film 2; a wiring layer 5 is formed on it; an interlayer insulating film 6 and a polyimide film 7 are formed one after another on the whole surface. Then, a resist film is formed on the whole surface of the polyimide film 7; the resist film in a region in which the polyimide film 7 is to be left is patterned; a resist film 8 is formed; the polyimide film 7 is etched and removed by using it as a mask. Then, the resist film 8 is removed; an SOG film 9 is formed on the whole surface; after that, the whole surface is etched; the surface of the interlayer insulating film 6 and the polyimide film 7 is exposed. After that, the polyimide film 7 is removed completely. Lastly, an interlayer insulating film 10 is formed on the whole surface; after that, it is patterned; a wiring layer 11 is formed on the surface of the scribing region and the interlayer insulating film 10.

Description

【発明の詳細な説明】 〔概 要〕 ポンディングパッドの形成方法の改良に関し、ポンディ
ングパッドの下層にSOG膜を形成しないで、ポンディ
ング工程におけるポンディングパッドの剥離を防止し、
スクライブ領域の層間絶縁膜の膜厚測定を容易に行うこ
とが可能となる半導体装置の製造方法の提供を目的とし
、複数層の配線層を備えた半導体装置の最上部の配線層
の形成工程において、その表面にスクライブ領域を画定
するフィールド酸化膜を形成し、該スクライブ領域にア
ライメントパターンを形成し、MiN記フシフイールド
酸化膜面に絶縁膜を形成し、該絶縁膜の表面に配線層を
パターニングして形成し、全面に層間絶縁膜を形成し、
た半導体基板の全表面にポリイミド膜を形成する工程と
、前記ポリ・イミド膜の表面に、最上部の配線層を形成
する領域に相当するレジスト膜をパターニングして形成
し、該レジスト膜をマスクとして前記ポリイミド膜をパ
ターニングする工程と、前記層間絶縁膜及び前記ポリイ
ミド膜の表面にSOG膜を形成し、m記層間絶縁膜及び
前記ポリイミド膜が露出するまで前記SOG膜を全面エ
ンチングする工程と、前記ポリイミド膜を除去し、層間
絶縁膜を全面に形成し、パターニングし、て前記スクラ
イブ領域を画定し、nI記、@量比縁膜の表面に配線層
を形成するよう構成する。
[Detailed Description of the Invention] [Summary] Regarding the improvement of the method for forming a bonding pad, the present invention is to prevent the peeling of the bonding pad during the bonding process by not forming an SOG film under the bonding pad,
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to easily measure the thickness of an interlayer insulating film in a scribe region, and to provide a method for manufacturing a semiconductor device that makes it possible to easily measure the thickness of an interlayer insulating film in a scribe region. , form a field oxide film that defines a scribe region on its surface, form an alignment pattern in the scribe region, form an insulating film on the surface of the MiN field oxide film, and pattern a wiring layer on the surface of the insulating film. an interlayer insulating film is formed on the entire surface,
forming a polyimide film on the entire surface of the semiconductor substrate, patterning and forming a resist film on the surface of the polyimide film corresponding to the area where the uppermost wiring layer will be formed, and masking the resist film. forming an SOG film on the surfaces of the interlayer insulating film and the polyimide film, and etching the entire surface of the SOG film until the mth interlayer insulating film and the polyimide film are exposed; The polyimide film is removed, an interlayer insulating film is formed on the entire surface, and patterned to define the scribe region, and a wiring layer is formed on the surface of the atomic film.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製造方法に係り、特にポンディ
ングパッドの形成方法の改良に関するものである。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a bonding pad.

半導体装置は近年界々集積度が向上し、DRAMにおい
てもアルミニウム(AI)の二層品が出現してきており
、平坦化が益々要求されている。
The degree of integration of semiconductor devices has been increasing rapidly in recent years, and two-layer products made of aluminum (AI) have appeared in DRAMs as well, and flattening is increasingly required.

平坦化の手段の一つとしてスピン・オン・グラス膜(以
下、SOG膜と略称する)が用いられているが、S O
G IJ!がボンディングバンドの下層に形成されてい
ると、半導体装置を組み立てるワイヤボンディング工程
においてボンディングキャピラリによってボンディング
バンドに加えられる加圧力により、SOG膜が剥離し、
そのためボンディングバンドが剥離する障害が発生して
いる。
A spin-on-glass film (hereinafter abbreviated as SOG film) is used as one of the flattening methods, but SO
G IJ! is formed under the bonding band, the SOG film will peel off due to the pressure applied to the bonding band by the bonding capillary during the wire bonding process for assembling the semiconductor device.
As a result, a problem occurs in which the bonding band peels off.

また、ウェーハプロセスにおいて平坦化のためにSOG
膜を用いた場合に、スクライブ領域の層間絶縁膜の厚さ
の測定が難しくなっている。
In addition, SOG is used for planarization in the wafer process.
When a film is used, it is difficult to measure the thickness of the interlayer insulating film in the scribe area.

以上のような状況からボンディングバンドの下層にSO
G膜を形成せず、スクライブ領域の層間絶縁膜の膜厚測
定を容易に行うことが可能となる半導体装置の製造方法
が要望されている。
Due to the above situation, SO is placed in the lower layer of the bonding band.
There is a need for a method of manufacturing a semiconductor device that makes it possible to easily measure the thickness of an interlayer insulating film in a scribe region without forming a G film.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製jΔ方法を第2図により工程順に
説明する。
A conventional method for manufacturing a semiconductor device will be explained step by step with reference to FIG.

まず、第2図(a)に示すように、半導体基板21の表
面にスクラ・イブ領域を画定するフィールド酸化膜22
を形成し、このスクライブ領域にアライメントパターン
23を形成し、このフィールド酸化膜22の表面に絶縁
膜24を形、成し、この絶縁膜2・1の表面に配線層、
例えばアルミニウム層25をパターニングして形成し、
全面に層間絶縁膜26を形成し、全表面にSOG膜21
〕を形成する。
First, as shown in FIG. 2(a), a field oxide film 22 is formed on the surface of a semiconductor substrate 21 to define a scribe area.
An alignment pattern 23 is formed in this scribe region, an insulating film 24 is formed on the surface of this field oxide film 22, and a wiring layer,
For example, by patterning the aluminum layer 25,
An interlayer insulating film 26 is formed on the entire surface, and an SOG film 21 is formed on the entire surface.
] to form.

一つぎに、第2図fblに示すように、アルミニウム層
25の表面の層間絶縁膜20が露出するまで、このSO
G膜29を全面エソ■−ングする。
Next, as shown in FIG.
The entire surface of the G film 29 is etched.

ついで、第2図te+に示すように、全面に層間比♀く
、嘆30を形成する。
Then, as shown in FIG. 2 (te+), a layer 30 is formed on the entire surface with an interlayer ratio of ♀.

υjすに、第2図(d)に示すように、この層間絶縁膜
30をパターニングしてスクライブ領域を形成し、層間
絶縁■々30の表面にボンディングバンドとなる配線層
、例えばアルミニウム層31を形成する。
υj First, as shown in FIG. 2(d), this interlayer insulating film 30 is patterned to form a scribe region, and a wiring layer, for example, an aluminum layer 31, which will become a bonding band is formed on the surface of the interlayer insulating film 30. Form.

C発明が解決しようとする課題〕 以上説明した従来の半導体装置の製造方法により製造し
た半導体チップを用いる半導体装置のワイヤボンディン
グ工程において、ボンディングキャピラリによってボン
ディングバンドに加えられる加圧力により、ボンディン
グバンドが剥離する障害が発生している。
C Problems to be Solved by the Invention] In the wire bonding process of a semiconductor device using a semiconductor chip manufactured by the conventional semiconductor device manufacturing method described above, the bonding band is peeled off due to the pressure applied to the bonding band by the bonding capillary. A failure has occurred.

このような障害を除去するために、■S C’l G膜
が無くなるまでエッチバックする方法か、或いは■ポン
ディングパッドとなるアルミニウム層を形成する範囲の
S○(j膜のみをパターニングし、でエツチングして除
去する方法が考えられる。
In order to remove such obstacles, there are two methods: ■ Etching back until the S C'l G film disappears, or ■ Patterning only the S One possible method is to remove it by etching it.

しかしながら、■の方法においては、エツチング量の増
加に伴いフィールド酸化膜にの絶縁膜がエツチングされ
て、咬5′Xが薄くなるため、アルミニウム層の′^:
生容量が増えたり、或いはオーハーエ、ノチングにより
アルミニウム層間のSOG膜が殆どなくなり、SOG膜
による平坦化の意味がなくなるという問題点があり、■
の方法においては、SOG、llQのパターニングのた
めの工程が増えるだけでなく、バルクとの層間絶縁膜も
薄くなり、配線容量が増えζしまうという問題点があっ
た。
However, in method (2), as the amount of etching increases, the insulating film on the field oxide film is etched, and the depth 5'X becomes thinner.
There is a problem that the raw capacitance increases or the SOG film between the aluminum layers is almost eliminated due to notching, and the planarization by the SOG film becomes meaningless.
This method not only increases the number of steps for patterning SOG and 11Q, but also has the problem that the interlayer insulating film with the bulk becomes thinner, resulting in an increase in wiring capacitance.

また、ウェーハプロセスにおいて平坦化のためにSOG
膜を用いた場合に、スクライブ領域内のアライメントパ
ターン或いは層間絶縁膜と半導体基板表面との段差によ
り、スクライブ領域の層間絶縁膜の膜厚を光学式測定器
或いはカラーサンプルによる比較目視方式による測定す
るのが難しくなっているという問題点があった。
In addition, SOG is used for planarization in the wafer process.
When a film is used, the thickness of the interlayer insulating film in the scribe area is measured using an optical measuring device or a comparative visual method using a color sample based on the alignment pattern in the scribe area or the step between the interlayer insulating film and the surface of the semiconductor substrate. The problem was that it was becoming difficult to

本発明は以上のような状況からポンデイングパツドの下
層にSOG膜を形成しないで、ボンディング[程におけ
るポンデイングパツド′の剥離を防止し7、スクライブ
領域の層間絶縁膜のff!厚測定を容易に行うことが可
能となる半導体装置の製造方法の提供を目的としたもの
である。
In view of the above-mentioned circumstances, the present invention prevents the peeling of the bonding pad during the bonding process by not forming an SOG film under the bonding pad. The object of the present invention is to provide a method for manufacturing a semiconductor device that allows thickness measurement to be easily performed.

(課題を解決するための手段〕 本発明の半導体装置の製造方法は、複数層の配線層を備
えた半導体装置の最上部の配線層の形成工程において、
その表面にスクライブ各a域を画定するフィールド酸化
膜を形成し、このスクラ・イブ領域にアライメントパタ
ーンを形成し、このフィールド酸化膜の表面に絶縁膜を
形成し、この絶縁11りの表面に配線層をパターニング
して形成し、全面に層間絶縁膜を形成した半導体基板の
全表面にポリイミド膜を形成する工程と、このポリイミ
ド膜の表面に、最上部の配線層を形成する8I域に相当
するレジスト膜をパターニングして形成し、このレジス
1−1漠をマスクとしてこのポリイミド月々をパターニ
ングするコー程と1、二の層間絶縁膜及び71ミリイミ
ド膜の表面にSOG膜を形成し、この層間絶縁IIり及
びポリイミド膜が露出するまでS OG Jiffを全
面エツチングする工程と、このポリイミドj摸を除去し
、層間絶縁膜を全面に形成し、パターニングしてスクラ
イブN域を画定し、この肋間絶縁膜の表面に配線層を形
成するよう構成するい〔作用〕 叩ら本発明においては、最」二部の配線層のポンデイン
グパツドが形成される領域に相当する下層の領域に、パ
ターニングして形成したボリイミ)膜の表面にSOG膜
を形成し、ボ1!イミド)漠の表面のS OG膜をエノ
千バンクにより除去した後、このポリイミド膜を酸素ア
ッシングによりSOG膜に対して選択的に除去すること
が可能となるので、最上部の配線層のポンデイングパツ
ドが形成される領域に相当する下層の領域にはSOG膜
がなくなり、半導体装置の製造]1程のり・1′ヤボン
デイング工程にお;、)るポンデイングパツドの剥離を
防止することが可能となる。
(Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention includes the steps of forming the uppermost wiring layer of a semiconductor device including multiple wiring layers.
A field oxide film that defines each scribe region a is formed on the surface, an alignment pattern is formed in this scribe region, an insulating film is formed on the surface of this field oxide film, and wiring is formed on the surface of this insulator 11. This corresponds to the 8I region, which involves forming a polyimide film on the entire surface of a semiconductor substrate by patterning layers and forming an interlayer insulating film over the entire surface, and forming the uppermost wiring layer on the surface of this polyimide film. A resist film is patterned and formed, and the polyimide film is patterned using the resist 1-1 as a mask.An SOG film is formed on the surface of the interlayer insulating films 1 and 2 and the 71 mmimide film, and this interlayer insulating film is formed. A process of etching the SOG Jiff over the entire surface until the polyimide film is exposed, removing this polyimide pattern, forming an interlayer insulating film on the entire surface, patterning to define the scribe N area, and removing the intercostal insulating film. [Function] In the present invention, patterning is applied to the region of the lower layer corresponding to the region where the ponding pad of the two most wiring layers is formed. A SOG film is formed on the surface of the formed polyimide film, and Bo1! (Imide) After removing the SOG film on the surface of the polyimide film using Enosen Bank, this polyimide film can be selectively removed with respect to the SOG film by oxygen ashing. There is no SOG film in the lower layer region corresponding to the region where the pad is formed, and this prevents the bonding pad from peeling off during the bonding process (1) and (1) during the manufacturing of semiconductor devices. becomes possible.

また、スクラ・イブ領域にSOG膜が残っていないので
、2この領域における層間絶縁膜の膜厚の測定を容易に
行うことが可能となる。
Furthermore, since no SOG film remains in the scribe area, it is possible to easily measure the thickness of the interlayer insulating film in this area.

〔実施例〕〔Example〕

以下第1Hについて本発明の一実施例を工程順に説明す
る。
An embodiment of the present invention will be described below in order of steps regarding the first H.

まず、第1図(11+に示すように、半導体as+ii
の表面にスクライブ領域を画定するフィー・ルl′酸化
膜2を形成し、このスクライブ領域にアライメントパタ
ーン3を形成し、このフィールド酸化膜20表lT11
に絶縁膜4を形成し、この絶縁膜4の表面に配線層、例
えばアルミニウム層5をパターニングして形成し、全面
にCVDシリコン酸化膜からなる層間絶縁膜6を形成し
、全表面1.こポリイミドII/27を形1戊する。
First, as shown in FIG. 1 (11+), the semiconductor as+ii
A field l' oxide film 2 is formed on the surface of the field oxide film 20 to define a scribe area, an alignment pattern 3 is formed on this scribe area, and the field oxide film 20 is formed on the surface lT11
An insulating film 4 is formed on the surface of the insulating film 4, a wiring layer such as an aluminum layer 5 is patterned and formed on the surface of the insulating film 4, and an interlayer insulating film 6 made of a CVD silicon oxide film is formed on the entire surface. This polyimide II/27 was cut into a shape.

つぎに、ポリイミド膜7の全表面にレジスト・膜を形成
し、第1図(b)に示すように、フォトリソグラフィー
技術によりポリイミド膜7を残そうとする領域のレジス
ト膜をパターニングし°ζレジスト膜8を形成し、この
レジスト膜8をマスクと1,7てポリイミド膜7を、下
記の条イ!1の酸素1′ソシング或いはポジし・シスト
用の現像液を用いてエツチング除去する。
Next, a resist/film is formed on the entire surface of the polyimide film 7, and as shown in FIG. A film 8 is formed, and using this resist film 8 as a mask, the polyimide film 7 is coated in the following steps. Etching is performed using 1' oxygen 1' souring or a developer for positive cysts.

反、応ガス−・・−・・・・−・・−一一一−−− −
酸素(Oz)反応ガニすU M−−−−−−−・−・−
−−31/ろ〕反応室内ip −−−一・−・−〜−・
 ・=1.0 Torr基板加熱温度−・−・−・−・
・−・−一一一−−−・−・−・−ioo℃高周波電源
周波数・・・−・・・−・−・−・13.56 MHz
高周高周波電源−カー−・・−−−一−−・・・−−−
−m−・・・・・・・−・・500Wついで、レジスト
膜8を市販のレジスト剥離液或いは酢酸ブチル等により
除去し、第1図(C)に示すように、全面に5OGLJ
9を形成してアニールする。
Reaction, reaction gas-----111-----
Oxygen (Oz) reaction crab U M-------・-・-
---31/RO] Reaction chamber ip ---1・-・-~-・
・=1.0 Torr substrate heating temperature −・−・−・−・
・−・−111−−−・−・−・−ioo℃High frequency power supply frequency・・・−・・・−・−・−・13.56 MHz
High-frequency high-frequency power supply - car - - - - - - - - - - -
-m-......500W Then, the resist film 8 is removed using a commercially available resist stripping solution or butyl acetate, and as shown in FIG. 1(C), 5OGLJ is applied to the entire surface.
9 is formed and annealed.

このSOG膜9を全面エツチングして第1図(dlに示
すように層間絶縁膜6及びポリイミド膜7の表面を露出
させる。
The entire surface of this SOG film 9 is etched to expose the surfaces of the interlayer insulating film 6 and the polyimide film 7, as shown in FIG.

その後、第1図(elに示すように、ポリイミド膜7を
第1図(b)に示すパターニング工程と同じ酸素アッシ
ングにより完全に除去する。
Thereafter, as shown in FIG. 1(el), the polyimide film 7 is completely removed by oxygen ashing, which is the same as the patterning process shown in FIG. 1(b).

最後に、第1図(f)に示すように、層間絶縁膜10を
全面に形成し、第1図(g)に示すように、この層間絶
縁膜10をパターニングしてスクライブ領域を形成し、
層間絶縁膜10の表面にポンディングパッドとなる配線
層、例えばアルミニウム層11を形成する。
Finally, as shown in FIG. 1(f), an interlayer insulating film 10 is formed on the entire surface, and as shown in FIG. 1(g), this interlayer insulating film 10 is patterned to form a scribe region.
A wiring layer, for example, an aluminum layer 11, which will become a bonding pad, is formed on the surface of the interlayer insulating film 10.

このように、ポリイミド膜7を用いることにより、ポン
ディングパッドとなるアルミニウム層11の下層にSO
G膜9が形成されないようにするので、3001g1%
9に起因するボンディングバンドの剥離を防止すること
が可能となる。
In this way, by using the polyimide film 7, SO is added to the lower layer of the aluminum layer 11 which becomes the bonding pad.
To prevent the formation of G film 9, 3001g1%
It becomes possible to prevent the bonding band from peeling off due to No. 9.

また、ウェーハプロセスにおいて平坦化のためにSOG
膜を用いる従来の製造方法におけるように、スクライブ
領域内のアライメントパターンなどの段差により、スク
ライブ領域の層間絶縁膜の膜厚の光学式測定器或いはカ
ラーサンプルによる比較目視方式による測定が容易にな
る。
In addition, SOG is used for planarization in the wafer process.
As in the conventional manufacturing method using a film, the step difference in the alignment pattern or the like in the scribe area facilitates the measurement of the thickness of the interlayer insulating film in the scribe area by a comparative visual method using an optical measuring device or a color sample.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、ポリイ
ミド膜を用いてボンディングバンドの下層及びスクライ
ブ領域にSOG膜が存在しないようにするので、ボンデ
ィング工程におけるポンディングパッドの剥離を防止す
ることが可能となり、また、ウェーハプロセスにおける
層間絶縁膜の膜厚の測定が容易になる等の利点があり、
著しい経済的及び、信頼性向上の効果が期待できる半導
体装置の製造方法の提供が可能となる。
As is clear from the above description, according to the present invention, since the polyimide film is used to prevent the presence of the SOG film in the lower layer of the bonding band and the scribe area, it is possible to prevent the bonding pad from peeling off during the bonding process. It also has the advantage of making it easier to measure the thickness of the interlayer insulating film during the wafer process.
It is possible to provide a method for manufacturing a semiconductor device that can be expected to be significantly economical and to improve reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による一実施例を工程順に示す側断面図
、 第2図は従来の半導体装置の製造方法を工程順に示す側
断面図、 である。 図において、 1は半導体基板、 2はフィールド酸化膜、3はアライ
メントパターン、 4は絶縁膜、5はアルミニウム層、
  6は層間絶縁膜、7はポリイミド膜、   8はレ
ジスト膜、9はSOG膜、     10は層間絶縁膜
、11はアルミニウム層、 を示す。
FIG. 1 is a side cross-sectional view showing an embodiment of the present invention in order of steps, and FIG. 2 is a side cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is an alignment pattern, 4 is an insulating film, 5 is an aluminum layer,
6 is an interlayer insulating film, 7 is a polyimide film, 8 is a resist film, 9 is an SOG film, 10 is an interlayer insulating film, and 11 is an aluminum layer.

Claims (1)

【特許請求の範囲】 複数層の配線層を備えた半導体装置の最上部の配線層の
形成工程において、 その表面にスクライブ領域を画定するフィールド酸化膜
(2)を形成し、該スクライブ領域にアライメントパタ
ーン(3)を形成し、前記フィールド酸化膜(2)の表
面に絶縁膜(4)を形成し、該絶縁膜(4)の表面に配
線層(5)をパターニングして形成し、全面に層間絶縁
膜(6)を形成した半導体基板(1)の全表面にポリイ
ミド膜(7)を形成する工程と、 前記ポリイミド膜(7)の表面に、最上部の配線層(1
1)を形成する領域に相当するレジスト膜(8)をパタ
ーニングして形成し、該レジスト膜(8)をマスクとし
て前記ポリイミド膜(7)をパターニングする工程と、 前記層間絶縁膜(6)及び前記ポリイミド膜(7)の表
面にスピン・オン・グラス(SOG膜)(9)を形成し
、前記層間絶縁膜(6)及び前記ポリイミド膜(7)が
露出するまで前記SOG膜(9)を全面エッチングする
工程と、 前記ポリイミド膜(7)を除去し、層間絶縁膜(10)
を全面に形成し、パターニングして前記スクライブ領域
を画定し、前記層間絶縁膜(10)の表面に配線層(1
1)を形成する工程と、 を含むことを特徴とする半導体装置の製造方法。
[Claims] In the process of forming the uppermost wiring layer of a semiconductor device having multiple wiring layers, a field oxide film (2) defining a scribe region is formed on the surface thereof, and alignment is applied to the scribe region. A pattern (3) is formed, an insulating film (4) is formed on the surface of the field oxide film (2), and a wiring layer (5) is patterned and formed on the surface of the insulating film (4). A step of forming a polyimide film (7) on the entire surface of the semiconductor substrate (1) on which an interlayer insulating film (6) has been formed, and a step of forming an uppermost wiring layer (1) on the surface of the polyimide film (7).
A step of patterning and forming a resist film (8) corresponding to the region where 1) is to be formed, and patterning the polyimide film (7) using the resist film (8) as a mask; A spin-on-glass (SOG film) (9) is formed on the surface of the polyimide film (7), and the SOG film (9) is removed until the interlayer insulating film (6) and the polyimide film (7) are exposed. A step of etching the entire surface, and removing the polyimide film (7) and forming an interlayer insulating film (10).
is formed on the entire surface and patterned to define the scribe area, and a wiring layer (10) is formed on the surface of the interlayer insulating film (10).
1) A method for manufacturing a semiconductor device, comprising: a step of forming 1);
JP1014275A 1989-01-23 1989-01-23 Manufacturing method of semiconductor device Pending JPH02194530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1014275A JPH02194530A (en) 1989-01-23 1989-01-23 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1014275A JPH02194530A (en) 1989-01-23 1989-01-23 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02194530A true JPH02194530A (en) 1990-08-01

Family

ID=11856536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1014275A Pending JPH02194530A (en) 1989-01-23 1989-01-23 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02194530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664650B2 (en) * 1998-05-07 2003-12-16 Samsung Electronics Co., Ltd. Method of forming an alignment key on a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664650B2 (en) * 1998-05-07 2003-12-16 Samsung Electronics Co., Ltd. Method of forming an alignment key on a semiconductor wafer

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