JPH0373536A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To reduce leak current by forming a high concentrated impurity layer of second conductivity type in a second conductivity type layer between junction and a gettering layer. CONSTITUTION:In a semiconductor device having a junction of first and second conductivity type layer 2, 3 in a semiconductor substrate 1 and a gettering layer 4, a highly concentrated impurity layer 5 of second conductivity type is formed in the second conductivity type layer 3 between the junction and the getting layer 4. The concentration of impurity at this time is 10 times of higher than the concentration of the second conductivity type layer 3 forming the junction. In addition, such constitution is made that a first conductivity type layer 6 which can apply voltage to a part of the second conductivity type layer 3 between the junction and the getting layer 4 is formed. Further such constitution is made that the getting layer 4 is embedded in the first conductivity type layer 6 which can apply voltage formed in a part of the second conductivity type layer 3 forming the junction. A semiconductor layer 7 having band gap, different from that of the semiconductor substrate 1 where the junction is formed, is further formed between the junction and the gettering layer 4. Thus diffusion of a small number of carriers into the junction can be suppressed, resulting in the reduction of leak current at high temperature.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device having a junction and gettering layer made up of impurity-introduced layers of different conductivity types, and relates to a semiconductor device that can reduce leakage current of the junction.

[Conventional technology]

There are the following two mechanisms for generating leakage current when the junction is maintained in a reverse bias state. One is a generated recombination current (GR) current associated with crystal defects or heavy metals in the depletion layer, and the other is a diffusion current of minority carriers in the neutral region. In current junctions formed in Si substrates, the former is dominant near room temperature, and the latter is dominant in a high temperature region of about 100'C. Conventional technology reduces the G-R current by gettering crystal defects and heavy metals that cause the generation of the G-R current deep into the semiconductor substrate or near the junction, as described in Japanese Patent Application Laid-Open No. 63-246831. This was the way to do it. However, this conventional method cannot reduce leakage current due to diffusion of minority carriers, and with the recent trend toward lower process temperatures, when it is necessary to form a gettering layer near the junction, it is necessary to may include a gettering layer. In such a case, there is a problem in that a large amount of minority carriers are generated from the gettering layer, increasing leakage current.

[Problem to be solved by the invention]

As semiconductor devices have become more highly integrated in recent years, their operating temperatures have become l
The temperature range is around 0C)°C. Therefore, it has become an important issue to reduce leakage current due to diffusion of minority carriers, which has not been considered a problem in the past. Although the above conventional technology can reduce the leakage current due to the G-Rft flow that is dominant near room temperature, it cannot reduce the leakage current due to the diffusion of minority carriers that is dominant at high temperatures.
There is a problem that the leakage current increases in some cases, and the problem of reducing leakage current due to diffusion of minority carriers remains unsolved. An object of the present invention is to reduce leakage current due to the diffusion of minority carriers as well as the G-R component.

[Means for Solving the Problems] In order to solve the above object, as shown in FIG. In a semiconductor device having a junction and a gettering layer 4, a high concentration impurity layer 5 of a second conductivity type is provided in the second conductivity type M3 between the junction and the gettering layer 4.
It has a structure that forms. The impurity concentration in this case was at least 10 times that of the second conductivity type layer forming the junction. Further, as shown in FIG. 1(b), a first conductivity type layer 6 capable of applying a voltage to at least a part of the second conductivity type layer 3 between the junction and gettering/lW4 was formed. Structure. Further, as shown in FIG. 1(c), the gettering layer is formed in the first conductivity type layer 6 to which a voltage can be applied, which is formed on at least a part of the second conductivity type layer forming the junction. 4 is embedded in the structure. Further, as shown in the drawing (d), in the semiconductor device having the junction and the gettering layer 4, a band different from that of the semiconductor substrate 1 on which the junction is formed is formed between the junction and the gettering layer 4. The structure is such that a semiconductor layer 7 with a gap is formed. In this case, the gettering layer is a layer formed by ion implantation of oxygen, carbon, nitrogen, etc. High concentration crystal defect layer, oxygen precipitation layer, polycrystalline Si layer. Possible examples include a bonded interface between bonded substrates, an interface between an epitaxial layer and a substrate, and others. [Operation 1] The potential distribution of the semiconductor device having the structure shown in the first drawing is shown in FIG. 2 for each structure. here,
First guide 1! The description will be made assuming that the type is an n type, the second conductivity type is a p type, and a reverse bias is applied to the junction between the 8th layer 8 and the 2nd layer 9. (a) shows the case where a p-type high concentration layer 11 (p'') is formed between the junction consisting of 8 layers 8 and 9 layers 9 and the gettering layer 10, and (b) shows the case where 8 layers 8 and 9 layers are formed. When an n-type layer 12 is formed on a part of the 9 layer 9 between the junction consisting of the 9 layers 9 and the gettering layer 10, (c) is the 0 layer formed on at least a part of the 9 layer 9 constituting the junction. When the above gettering M10 is embedded in 12, (d) is 8 layers 8 and 9.
-p/n between the junction consisting of layer 9 and gettering layer 10
When forming a semiconductor layer 13 having a wider bandgap than the semiconductor substrate 1 on which the junction is formed, (e) becomes (
Contrary to d and ), these are respective potential distributions when a semiconductor layer 14 having a narrower bandgap than the semiconductor substrate on which the p/n junction is formed is formed. When a reverse voltage is applied to the junction between the 8th layer 8 and the 9th layer 9, the neutral region 16 excluding the depleted region 15 near the junction becomes a source of minority carriers (electrons in this case). When nothing is formed between the junction and the gettering layer 10, the p-required region 9 on the gettering layer 10 side becomes a source of electrons. (
p4'' between the junction and the gettering layer 10 as shown in a>
When the layer 11 is formed, since the potential of this P+ layer 11 is higher than the surrounding p-type head region, the p4″ layer 11
Electrons diffused from the p-layer farther from the junction become difficult to cross the potential wall, and the number of electrons reaching the depletion layer 15 decreases. therefore. Electrons contributing to the leakage current are dominated by electrons generated in the p layer, which is closer to the junction than the 91 layer 11. Thereby, leakage current due to diffusion of electrons, which are minority carriers, can be reduced. In this case, if the impurity concentration of the p+ layer 11 is increased, the potential wall against electron diffusion becomes higher, making it more difficult for electrons to diffuse, and increasing the effect of reducing leakage current. In cases (b) and (c), the junction and gettering layer 10
The potential of the n-layer structure 2 formed during the process and the nMl 2 in which the gettering layer 10 is embedded is lower than that of the surrounding p-layer, and it becomes a layer that captures electrons, contrary to the case of (,). diffusion to the bonding side is suppressed. Furthermore, when the impurity concentration of the n-layer is increased, the potential becomes lower, so the barrier to electron diffusion becomes higher, and the effect becomes greater. Furthermore, when a positive voltage is applied to the n-layer 12, the potential of the n-layer 12 becomes lower and more electrons are captured. At the same time. Since a reverse voltage is applied to the nine layers 9 forming a junction with the n-layer 12, a portion of the neutral region of the nine layers 9 is depleted. Therefore, the neutral region, which is a source of electrons, becomes narrower by the amount of depletion, and leakage current due to electron diffusion can be further reduced in addition to the potential effect. In cases (d) and (e), the same effect as in (, ) and (b) above is obtained; in case (d), the semiconductor layer 13 with a wide bandgap acts as a barrier to electron diffusion, and in case (e), The narrow bandgap semiconductor layer 14 captures electrons. These effects can reduce leakage current due to electron diffusion. Furthermore, when the first conductivity type is p type and the second conductivity type is n type, the same explanation can be given by considering the minority carriers as holes. Embodiments Examples of the present invention will be described below with reference to FIGS. 3 to 6. FIRST EMBODIMENT FIG. 3(a) is an example in which a P+ layer is formed between the junction of a p/n junction diode and the gettering layer. An n layer 18 having a surface concentration of 10''/c+m' was formed. In addition, a gettering layer 19 with an oxygen concentration of 10''/Cm' was formed in a region 2 to 3 μm from the surface.Furthermore, B ions were implanted with IMeV between the p/n junction and the gettering layer 19. X 10"/c1 and 3 X 10
A p+ layer 20 with a concentration of "/cm" was formed @'P/
The shape of the n-junction was a rectangle of 200 μm×200 μm. Further, each element was separated by a selective oxide film (Sin, film) 21 having a thickness of 500 nm. (b) shows the relationship between the leakage current per unit area of the p/n junction and the impurity concentration of the P+ layer 19 at 100°C. In this case, the voltage of the substrate 17 is OV, and the voltage of the n layer 18 is 5V.
The leakage current of one p/n junction measured as 100℃
At such high temperatures, the main component is leakage current due to the diffusion of electrons, which are minority carriers, so this result represents the leakage current due to the diffusion of electrons. This leakage current is p+ when the concentration of the p+ layer 20 is 3 x 10"/am'
It is about 1/2 when the layer 20 is not formed, and about 1/1 when the concentration of the p+ layer 20 is 3'X 10''/cm''.
According to this example, the leakage current due to minority carriers can be reduced to about 1/2 to 1/10 compared to the conventional method, and the leakage current of the p/n junction can be reduced during high-temperature operation. less p
/ n-junction diode can be obtained. Second Embodiment FIG. 4(a) shows an example in which the present invention is implemented in a dynamic random access memory (DRAM), and its structure is shown using p-type Si with a zero surface concentration of 5 x 10''/c11''. A DRAM having an N-channel MOS transistor and a planar MOS capacitor on a substrate 25 was exhibited. Here, the gate edge film 26 of the MOS transistor and the capacitor insulating film 27 of the MOS capacitor have a film thickness of 10
The gate electrode 28 and the capacitor electrode 29 were made of phosphorus-doped polycrystalline Si with a film thickness of 300 nm. The source/drain regions of the MOS transistor have a surface concentration of 10"/cm'
+ layer 30, and the 8 layers 31 below the MOS capacitor had a surface concentration of 5 x 10''/am''. The gate length and gate width of the MOS transistor are each 1 μm, and the shape and dimensions of the MOS capacitor are 5 μm x 5 μm.
It is a rectangle of m. Further, the region where the MOS transistor and the MOS capacitor were formed was separated from other elements by a selective oxide film 32 with a thickness of 500 nm. In the substrate on which this memory cell is formed, a gettering layer 33 containing carbon at a concentration of 10"/cm" is formed in a region approximately 2 to 3 μm from the surface, and further in a region approximately 1 to 2 μm from the surface. concentration is 10
It has a structure in which the 0 layer 34 of "/cm' is present. When the substrate voltage of this device is OV and the voltage of n"N30 and 8 layer 31 is 3■, the n+ layer 30 at 1'OO°C. The leakage currents at the junction between and the p-layer 25 and between the n-N31 and the 1-layer 25 are calculated using the values of the conventional device (I x 10-'
Figure 4 (b
) to the junction of n 4″ layer 30 and 9 layer 25 and 8 layer 3
The graph shows the change in junction leakage current per unit area at high temperature when a heavy pressure is applied to the 0 layer 34 formed between the junction of 1 and pj125 and the gettering layer 33. By applying a voltage higher than 'V, the leakage current per unit area of the n/p junction at high temperature can be reduced to about 175 compared to when no voltage is applied, and about 175 compared to the conventional method.
I made it to 10. This is due to the voltage applied, n
This is because the potential of N35 was low enough to prevent minority carrier diffusion. In this way, n layer 3
A greater effect was obtained by applying a voltage to 5. Additionally, a zero layer 34 is provided between the n/p junction and the gettering layer 33.
Instead of forming a gettering layer 33 in a region 1.5 to 2.5 μm from the surface of 9, a gettering layer 33 is formed in a region 1 to 3 μm from the surface.
A similar effect was obtained when the structure was embedded in the 0 layer 34 formed in the region. According to this embodiment, the leakage current per unit area of the n/p junction in a DRAM at high temperatures can be reduced to 1/2 to 1/10, and the information retention time during high temperature operation can be approximately doubled. It has the effect of being able to last a long time. Embodiment 3 Figure 5 shows an example in which a Ge layer with a bandgap smaller than that of Si is formed between the junction and gettering layer of a -p/n junction diode. Type S
The surface concentration of the i-substrate 37 is 1 () 1@ /C,s n
Layer 38 was formed. Moreover, the gettering layer 39 is 10"
/Cm' nitrogen-containing layer (area 2 to 3 μm from the surface). Furthermore, 10 nm of p-type Ge (Ef=:0.1+E
v) Layer 40 (1.5 μm deep from the surface) was formed. The shape of the diode is a rectangle of 200 μm x 200 μm, and each element is covered with a selective oxide film (S) of 500 nrn.
The elements were separated by a film (in, film) 41. Ge is about 0 less than Si
．． Ge7140 has a narrow 5 eV bandgap, so Ge7140 has the effect of capturing electrons, which are minority carriers. Therefore, when GellI40 was formed, the leakage current at high temperature could be reduced to about 173 compared to the conventional method in which GellI40 was not formed. Also, instead of the Ge layer 40, the band gap is 2.2.
6 eV wide, 50 nm thick p-type GaP (Ef=0.
3+Ev) layer 40 is formed at a depth of about 1.5 μm from the surface, the GaP layer 40 has a sufficiently wide band gap and a sufficiently high potential barrier is formed.
The effect is greater than when layer 40 is formed, and p
/N junction leakage current could be reduced to 1/10. According to this embodiment, the leakage current of the p/n junction at high temperatures can be reduced, and a p/n junction diode with excellent high-temperature operation characteristics can be obtained. Fourth Embodiment FIG. 6(a) shows an example in which the present invention is applied to a photodiode, and its structure is shown. p
A P-type well layer (p-well BM) 47 having a higher impurity concentration than the well A layer 46 was formed. An n-layer 48 that forms a junction with the p-well A46 layer is formed to a depth of about 2 μm from the surface, and two layers 4 are further formed to a depth of 0.3 μm from the surface of the n-layer 48.
9 was formed. In addition, as shown in (b), which is a partially enlarged view of (a), a gettering layer 50 is formed in one layer 49 at a depth of 0.1 μm from the surface, and a gettering layer 50 is formed to a depth of 0.1 to 0.2 μm. The structure was such that one layer was formed on the p+ layer at a high concentration. In addition, the n layer 48
A gettering layer 52 with a thickness of 0.2 μm and a depth of 1.5 μm from the surface is placed in the p-well B layer 47 around the n-layer 4.
In the p-well B layer 47 between the gettering layer 52 and the gettering layer 52,
The structure was such that 94 high concentration layers 53 were formed with a thickness of 1110.5 μm and a depth of up to 2 μm from the surface. Further, the charge readout section is composed of an n1 layer 54 with a surface concentration of 10''/c1, a Si oxide film 55 serving as a gate insulating film, and a phosphorous-doped polycrystalline Si gate electrode 56. type substrate 45. The impurity concentrations of the p-well A layer 46, the p-well B layer 47, and the n-layer 48 are as follows:
5 x 10"70m", 2 x 10°/cm",
2 x 10”/c1. and 5 x 10”70m”
In addition, 2 layers 49 on the surface of the n layer 48, 1 layer on the p+ layer
and the concentration of the p+ layer 53 around the n layer 48 are 5.
X 10”/c1.10”70m” and 10”70
Furthermore, the gettering layer 50.52 has an oxygen concentration of 1019/
It was a fake of am'. The substrate voltage is 9V at the photodiode section, and the n-layer 48 is 4V.
When the potential is set to v, the n-layer 48 and the n-layer 4
Since all of the p-well A layer 46 in FIG. 0 In this embodiment, the n-layer 4 serves as a supply source of minority carriers.
8 surface 9 layer 49 on p+ layer 1. p around the n layer 48
Since the P+ layer 53 is formed in the well B layer 47, the p+
The upper layer 1 and the p+ layer 53 serve as a barrier for minority carrier diffusion. Therefore, the leakage current of the p/n junction at 100° C. could be reduced to about 115 compared to the conventional method. According to this embodiment, diffusion of minority carriers into the photodiode portion can be reduced, so that the dark current of the photodiode can be reduced to about 115% compared to the conventional method. Furthermore, since this dark current can be reduced, it is effective in suppressing the sensitivity reduction effect caused by the dark current. Effect 1 of the invention According to the present invention, the first
Since diffusion of minority carriers into the junction between the conductive layer and the second conductive layer can be suppressed, leakage current at high temperatures can be reduced, which is effective in improving the performance of the semiconductor device during high-temperature operation.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the present invention, showing the structure of a semiconductor device, Fig. 2 is a diagram showing the potential distribution in a semiconductor having the structure of Fig. 1, and Fig. 3 is an illustration of the present invention applied to a p/n junction diode. 4 is a diagram illustrating an example in which the present invention is implemented in a DRAM, FIG. 5 is a diagram illustrating an example in which the present invention is implemented in a p/n junction diode, and FIG. 6 is a diagram illustrating an example in which the present invention is implemented in a DRAM. FIG. 2 is a diagram illustrating an example in which the present invention is applied to a photodiode. Explanation of symbols 1... Semiconductor substrate, 2, 6... First conductive layer, 3.5
...Second conductive layer, 4.10,19,34,39,50.52...Gettering layer, 7,13,14,40...Semiconductor layer having a different band gap from the semiconductor substrate, 8.18...
n-type junction forming layer, 9.38.49...p-type junction forming layer. 11.20,51,53...p-type high concentration layer, 12.3
3.48...n-type layer, 15...depletion layer. 16...neutral region, 17,25.37...p-type Si
Substrate, 21, 32.41... selective oxide film (SLO, film), 22.26, 42.55... gate insulating film (Si
n. Membrane) -23, 35, 43...A1 electrode. 24.36...phosphorus glass (for passivation),
27... Capacitor absolute mmcsio, membrane), 28.5
6... Gate polycrystalline sit pole, 29... Capacitor polycrystalline Si electrode, 30.54... Source/drain region, 31... Capacitor n layer, 45... N-type Si substrate, 46. 47...p well layer. Dream map (mountain) (b) <C) (d) Shiha with a dull look on the surface Figure 2 (e) Surface seasonal 0n! D (C) G3 Fig. (α) (b) Fig. ((1) Cb) θ 2J4 4th layer applied voltage (Y)

Claims (1)

[Claims] 1. A semiconductor device having a junction made of a first conductivity type layer and a second conductivity type layer in a semiconductor substrate, and a gettering layer for crystal defects and heavy metal contamination, wherein the junction and the getter A semiconductor device characterized in that a second conductivity type high concentration impurity layer is formed in a second conductivity type layer between ring layers. 2. A semiconductor device having a junction and a gettering layer as described above, characterized in that a layer of the first conductivity type is formed on at least a part of the layer of the second conductivity type between the junction and the gettering layer. . 3. The semiconductor device having the above-mentioned junction and gettering layer has a structure in which the above-mentioned gettering layer is embedded in the first conductivity type layer formed in at least a part of the second conductivity type layer constituting the junction. A semiconductor device characterized by: 4. A semiconductor device having a junction and a gettering layer as described above, characterized in that a semiconductor layer having a bandgap different from that of the semiconductor substrate on which the junction is formed is formed between the junction and the gettering layer. . 5. In claim 1, the impurity concentration of the second conductivity type layer formed between the junction and the gettering layer is at least 10 times the concentration of the second conductivity type layer constituting the junction. A semiconductor device characterized by: