JPS61274366A - High voltage semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the deterioration of element characteristics such as high dielectric strength completely and obtain a more reliable element by covering the surrounding structure of a cell integrating part with an undoped semiconductor film. CONSTITUTION:A field silicon oxide film 5b is formed over field limiting rings (P<+> type semiconductor layers 3c and 3d) and, after undoped polycrystalline silicon 6a is deposited, selectively patterned. The polycrystalline silicon 6a is applied so as to cover the gate electrode part and a P<+> type semiconductor layer 3b and then cover the field limiting ring of the P<+> type semiconductor layer 3c and reach the tip part of the semiconductor chip. The polycrystalline silicon above the field limiting rings and a region for a gate protecting diode is selectively covered with a photoresist and, after a source N<+> type semiconductor layer 8 and an N<+> type polycrystalline silicon layer 6c are formed by ion implantation, an undoped CVD-SiO2 film 5d and a PSC film 5e which contains high concentration phosphorus are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to high voltage semiconductor devices such as high voltage power MO3FETs, power bipolar transistors, and power diodes.

BACKGROUND OF THE INVENTION In recent years, as the demand for high-voltage, high-power transistors has increased, transistors with excellent performance and reliability have been desired.

Generally, transistors with high breakdown voltages, such as 800μ or 1000μ or higher, are manufactured using field-limiting rings to expand the depletion layer on a low-concentration silicon substrate.
Since the depletion layer tends to spread, a field plate or the like is provided to stabilize the potential, and in consideration of reliability, a passivation film such as a PSG film doped with Linnaeus dull material is provided.

This is a DSA (mouth 1ttusion 5elf-8l) which is a typical high voltage power MO3FE'I'.
An example of the structure of the power MO3FET having the ignment) structure will be described with reference to the cross-sectional structural diagram of FIG. 5 of the accompanying drawings.

FIG. 5 shows an example of the cross-sectional structure of a conventional vertical MO3FET. In this vertical MO3FET, a channel is formed by double diffusion, and the same diffusion window is surrounded by a gate polycrystalline silicon electrode 16 in a lattice shape. The feature is that the channel region is formed by impurity diffusion (P-type semiconductor layer 13) and the source region is formed by impurity diffusion (n+-type groove conductor layer 14).The channel length is between the P-type semiconductor layer 13 and the n+ Since this is determined by the difference in the diffusion depth of the mold-type trench conductor layer 14, an extremely short channel region of several microns or less can be formed.The source electrode is formed by connecting the source region of the n4'-type semiconductor layer 14 and the P-type semiconductor that forms the channel region. It is ohmically connected to the P+ type semiconductor layer 13a which is in contact with the layer 13 through an Al film 8a.

The n" type semiconductor substrate 11 and the n type epitaxial layer 12 are the drain region, and have an n-on-n" structure. The drain electrode 19 is formed on the back surface of the chip, and is connected to the gate and
When a positive voltage is applied across the source to turn on the channel, current flows vertically away from the substrate, through the channel, and into the source. This is why it is called a vertical MO3FET. In this conventional vertical MO3FET,
In the n-type epitaxial layer 12, P+ of the opposite conductivity type constitutes a field limiting ring for expanding the depletion layer.
Semiconductor layers 13c and 13d are formed between the P+ type semiconductor layer 13b and the P" type semiconductor layer 13c, between the P+ type semiconductor layer 13C and the P+ type semiconductor layer 13a, and the P" type groove conductor layer 13d. An insulating film 15C, which is a silicon oxide film, is provided on the outside, and a PSG film 15e as a passivation film is provided on these insulating films 15c.Furthermore, in this conventional vertical MO3FET, the source AI
electrode 18a, and AIIV eel play) 18c, 18
d is provided.

Problems to be Solved by the Invention In general, in semiconductor devices such as those described above, a silicon substrate with a low concentration of less than l Q"atoms/cnf is used in order to create a high breakdown voltage element. In bipolar transistors, the base-collector voltage VCBQ SM tends to change easily depending on various conditions, especially due to moisture, Na ions, heavy metal ions, or contamination caused by resin mold sealing.
In an OS type transistor, deterioration of the source-drain voltage V n s s etc. occurs, impairing device characteristics.

In other words, the Linnean dull material in the conventional PSG film is extremely effective in trapping heavy metal sodium ions, but it has an extremely high hygroscopicity and is especially useful for transistors that require a high withstand voltage of 800μ or more, especially in high-temperature reverse bias tests. , etc., deterioration of withstand voltage occurred.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a highly reliable high voltage semiconductor device without deterioration of element characteristics such as voltage resistance characteristics.

Means for Solving the Problems In a high-voltage semiconductor device according to one feature of the present invention, a semiconductor substrate of one conductivity type is provided with a first semiconductor layer of a conductivity type opposite to that of the semiconductor substrate, and a first semiconductor layer of a conductivity type opposite to that of the semiconductor substrate is provided on the semiconductor substrate. A first insulating film extending outward from the first semiconductor layer is provided so as to partially overlap the boundary between the first semiconductor layer and the semiconductor substrate, and an impurity is formed on the first insulating film. An undoped semiconductor film is provided.

In a high-voltage semiconductor device according to another feature of the present invention, a first semiconductor layer of a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type, and a ring-shaped layer is formed around the first semiconductor layer at a predetermined interval. and at least one of the same conductivity type as the first semiconductor layer.
a second semiconductor layer is provided on the semiconductor substrate;
The second semiconductor layer extends between and partially overlaps the boundary between the first semiconductor layer and the semiconductor substrate and the boundary between the second semiconductor layer and the semiconductor substrate, and extends between them.
A first insulating film extending outward from the second semiconductor layer so as to partially overlap the boundary between the semiconductor layer and the semiconductor substrate, and an impurity is not doped on the first insulating film. a film is provided between the first semiconductor layer and the second semiconductor layer;
A metal film extending from the semiconductor layer is located so as to partially overlap the semiconductor film with a second insulating film interposed therebetween.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to embodiments of the present invention with reference to FIGS. 1 to 4 of the accompanying drawings.

FIGS. 1A to 1F are cross-sectional views showing the manufacturing process of a DSA-MOSFET as an embodiment of the present invention.

As shown in Figure 1 (A), this DSA-MOSFET
To make this, first, an n-type epitaxial layer 2 is formed on an n+-type semiconductor substrate 1 to have a specific resistance of, for example, 40 to 60 Ωcm.

After forming a thickness of 80 to 100 μm, a silicon oxide film 5 is placed on the surface.
A and a P+ type semiconductor layer are formed to a depth of, for example, about 15 μm. This P" type semiconductor layer is a P+ type semiconductor layer 3a located in the cell located in the gate polycrystalline silicon opening.
The depletion from the P+ type semiconductor layer 3b, which is located around the cell integrated area and in electrical contact with the source electrode, and the P+ type semiconductor layer 3b, in order to obtain a large source-drain breakdown voltage (Voss). It consists of a P'' type half layer 3c3d, called a field limiting ring, which is located in a ring shape around the P'' type semiconductor layer 3b so that the layer spreads easily, and these are formed in the same diffusion process. be done.

Thereafter, as shown in FIG. 1(B), a field silicon oxide film 5b of about 8,000 layers is formed on the field limiting ring (P" type semiconductor layer 3CN3d), and then a gate oxide film 5c is formed. Approximately 1,000 people will be formed.

Next, as shown in FIG. 1C, the undoped polycrystalline silicon 6a is selectively patterned after being deposited at, for example, 4000A.

At this time, the polycrystalline silicon 6a is formed to cover the gate electrode portion, the P'' type half body layer 3b, the P'' type half body conductor layer 3c, and the field limiting ring up to the tip of the chip.

Subsequently, as shown in FIG. 1(D), a photoresist film 7 is selectively left on the polycrystalline silicon 6a on the field limiting ring using a photoetching technique, and a polycrystalline silicon pattern for a gate electrode is formed. Ion implantation is performed using a mask to form the P-type semiconductor layer 4 in the channel region in a self-aligned manner. At this time, P impurities for a gate protection diode are simultaneously ion-implanted into the polycrystalline silicon 6a to form P-type subcrystalline silicon 6b.

Next, as shown in FIG. 1(E), the upper polycrystalline silicon for the field limiting ring and gate protection diode is selectively covered with photoresist using photoetching technology again, and then ion implantation is performed. After forming the source n+ type semiconductor layer 8 and the n++ polycrystalline silicon 6c, a CvD-8102 film 5d containing no impurities is deposited to a thickness of approximately 300 m using the CVD method.
Approximately 500 OA of PSG film 5e containing OA and high concentration of phosphorus
Form.

After that, as shown in FIG. 1(F), after various heat treatments are performed, contact holes are opened and the source + voltage is 8.
A and Ga) Al electrodes 8b are formed, and a back electrode film 9 is formed on the semiconductor substrate 1 to complete the DSA-MOSFET.

According to this manufacturing process, polycrystalline silicon, which does not contain semiconductor impurity ions used in the gate electrode material, is used, so in the same process step, a gate protection diode, which is called a gate protection diode, is formed, and an extremely thin gate insulating film is formed. In order to prevent static electricity damage, by forming P-type child crystalline silicon 6b (when forming a channel P-type semiconductor layer) and n+-type packed crystal silicon 6C (when forming a source n+-type semiconductor layer) in polycrystalline silicon, A polycrystalline silicon diode can be formed, and at this time, the polycrystalline silicon 6a on the field limiting ring is covered with a photoresist so that it does not contain impurities so that impurity ions are not implanted. It has high resistance and can be made into a strong passivation film.

Particularly in high-voltage MO5 type semiconductor devices, the biggest Φ point is how well the peripheral structure of the cell integrated part can maintain its initial characteristics without being affected by surrounding conditions, and in order to obtain a highly reliable device, In the above-described structure of the present invention, sodium ions and heavy metal ions are trapped in the conventional PSG film 5e, and the above-mentioned ions passing through the PSG film 5e, as well as especially moisture, are semiconductor impurities with high resistance. The polycrystalline silicon film 6a, which does not contain any oxides, can completely cut off the radiation. In particular, since contamination at the interface between the thick silicon oxide film 5b existing in the field region and the n-type epitaxial layer 2 can be prevented, a high voltage element with low leakage current (In5s) between the source and drain can be obtained. . In this embodiment according to the invention, the initial value 1
A source-drain breakdown voltage of 200V was obtained.

FIG. 4 shows a reliability test of source-drain breakdown voltage in a high-temperature reverse bias test of an element having a conventional structure and an element prototyped according to the present invention.

This test was conducted at 25° C. and −10 V source + voltage.

From the data in Figure 4, it is clear that conventional PSG films and field plate improvements alone are not sufficient for high-voltage semiconductor devices such as high-voltage MO3FETs, and how superior the device according to the present invention is. I understand.

FIG. 2 shows another embodiment of a DSA-MOSF according to the present invention.
It is a figure similar to FIG. 1 (F) showing the cross-sectional structure of ET.

The DSA-MOSFET of FIG. 2 differs from that of FIG. 1 only in the following points. That is, in the embodiment of FIG. 2, the field limiting rings 3c, 3
The impurity-free polycrystalline silicon 6a on d is selectively patterned to form a P+ type semiconductor layer 3b and P+ type semiconductor layers (field limiting rings) 3C and 3d.
By providing field plates 8c and 8d made of Al films, the spread of the depletion layer is improved and the potential is stabilized. The impurity-free polycrystalline silicon pattern 6a extends from the first Al field plate 8a formed from the P+ type semiconductor layer 3b to the second AA field plate provided on the field limiting ring of the P+ type semiconductor layer 3c. The peripheral structure surrounding the cell integration part (in MOS type), which is an important point in high-voltage semiconductor devices, is formed using an Al film field plate and impurity-free polycrystalline silicon. It can be covered with a pattern.

FIG. 3 shows a DSA-MOSF of yet another embodiment of the present invention.
FIG. 2 is a diagram similar to FIG. 2 showing the cross-sectional structure of ET. The DSA-MOSFET shown in FIG. 3 differs from that shown in FIG. 2 in the following points. In other words, AI! The film field plates 8a18C and 8d have an underlying insulating film 5e,
The polycrystalline silicon film 6 is passed through the opening 10 formed at 5d.
a, thereby further enhancing the field plate effect.

Further, in the present invention, polycrystalline silicon containing no impurities may be used from the P+ type semiconductor layer 3b to the middle of the P+ type semiconductor layer 3C.

In the above-mentioned embodiments, polycrystalline silicon that does not contain semiconductor impurities refers to not only polycrystalline silicon that does not contain any impurities, but also polycrystalline silicon that contains a trace amount of n-type impurity or P-type impurity. It does not matter if it gets mixed in during deposition. That is, the polycrystalline silicon 6a that does not contain impurities in the embodiment of the present invention refers to the P+ type semiconductor layer 3b.
The polycrystalline silicon 6a located through the P+ type semiconductor layer 3C1 and the insulating film increases its conductivity, performs MOA operation or an operation similar to this, and achieves the optimum silicon wafer concentration, thickness, and field limiting ring. Any polycrystalline silicon may be used as long as it has a sheet resistance of, for example, several kiloohms or several milligohms or more, which does not cause the phenomenon that a normal breakdown voltage cannot be obtained even though the resistance is satisfied.

Further, in the above embodiment, polycrystalline silicon containing no impurities was used on the field silicon oxide film, but an amorphous silicon film may be used instead.

In particular, when amorphous silicon is not doped with impurities, n-type amorphous silicon with an extremely low concentration is formed during the deposition process. '～101012a
Amorphous silicon with an extremely low concentration of tO/C[II or less is possible. Therefore, amorphous silicon is particularly suitable for 200 to 3
Since the deposition is performed in a plasma atmosphere at about 00°C, for example, in an MO3 type semiconductor device, shallow-junction
After forming a channel length etc. that requires a junction), it is possible to use it as a passivation film in a field silicon oxide film, and also to use A1 as a passivation film.
Also on the electrode, it is used as a passivation film or an interlayer insulating film for multilayer wiring together with an insulating film that can be processed at an extremely low temperature, such as a polyimide resin, a plasma oxide film, or a plasma oxide film.

Further, although the above-mentioned embodiment is an MO3 type semiconductor device, the present invention is not limited to this, but can also be applied to a bipolar type semiconductor device or a high breakdown voltage such as a diode.

It can also be applied to semiconductor devices. Further, the present invention may be used in a low voltage semiconductor device. In the above embodiments of the invention, the semiconductor types P and n may be reversed.

Effects of the Invention As mentioned above, in the high-voltage semiconductor device of the present invention, the peripheral structure of the cell integrated section is covered with a semiconductor film that is not doped with impurities, so that it can pass through an insulating film such as a normal PSG film. Since it can completely block out sodium ions, heavy metal ions, and especially moisture, which would cause damage, it can completely prevent deterioration of device characteristics such as high voltage resistance characteristics, making the device more reliable. .

Further, according to the manufacturing process of the MO3 type semiconductor device as described above of the present invention, the photoetching process step can be performed by using the polycrystalline silicon film applied to form the semiconductor film that is not doped with impurities. Since a gate protection diode for preventing breakdown of the gate insulating film can be formed at the same time without increasing the cost, it is possible to provide an element with low productivity and cost that does not require care in handling.

[Brief explanation of the drawing]

Figures 1 (A) to (F) are cross-sectional views showing the manufacturing process of a DSA-MOSFET as an embodiment of the present invention, and Figure 2 shows the structure of a DSA-MOSFET as another embodiment of the present invention. A sectional view, FIG. 3 is D of still another embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the structure of the SA-MOSFET. FIG. 4 is a diagram showing the reliability test results of source-drain breakdown voltage in high-temperature reverse bias tests of devices with conventional structure and devices prototyped according to the present invention. FIG. FIG. 2 is a diagram showing an example of the cross-sectional structure of a conventional vertical MO3FET. 1...n++ semiconductor substrate, 2...n-type epitaxial layer, 3a, 3b, 3c, 3d...
・P+ type semiconductor layer, 4...P type semiconductor layer, 5b
...Silicon oxide film for field, 5c...
...Gate oxide film, 6a...Polycrystalline silicon not doped with impurities, 6b...P-type M-crystalline silicon, 6c...N+ type packed crystal Silicon 7...Photoresist film, 8...Source n+ type semiconductor layer, 8a...Source/l electrode, 8b...Ga) AI electrode, 8c18d ...
... A1 field plate, 9 ... Back electrode film, 10 ... Opening. Figure 4 Time (H)

Claims (7)

[Claims] (1) A first semiconductor layer of a conductivity type opposite to that of the semiconductor substrate is provided on a semiconductor substrate of one conductivity type, and on the semiconductor substrate,
A first insulating film is provided extending outward from the first semiconductor layer so as to partially overlap the boundary between the first semiconductor layer and the semiconductor substrate, and an impurity is doped onto the first insulating film. A high-voltage semiconductor device characterized in that it is provided with a semiconductor film that does not have a high breakdown voltage. (2) The high voltage semiconductor device according to claim (1), wherein the semiconductor film is formed of polycrystalline silicon. (3) The high voltage semiconductor device according to claim (1), wherein the semiconductor film is formed of amorphous silicon. (4) A first semiconductor layer of a conductivity type opposite to that of the semiconductor substrate, and a ring-shaped ring formed at a predetermined interval around the first semiconductor layer, of the same conductivity type as the first semiconductor layer, on a semiconductor substrate of one conductivity type. At least one second semiconductor layer is provided on the semiconductor substrate, and one layer is provided on the boundary between the first semiconductor layer and the semiconductor substrate and on the boundary between the second semiconductor layer and the semiconductor substrate. a first insulating film extending outward from the second semiconductor layer so as to partially overlap and extend between them, and partially overlapping a boundary between the second semiconductor layer and the semiconductor substrate; a semiconductor film not doped with impurities is provided on the first insulating film, and a metal film extending from the first semiconductor layer and the second semiconductor layer is disposed on the semiconductor film via the second insulating film. A high voltage semiconductor device characterized in that it is located so as to partially overlap the . (5) The metal film extending from the first semiconductor layer and the portion of the semiconductor film extending between the first semiconductor layer and the second semiconductor layer are the openings formed in the second insulating film. a metal film extending from the second semiconductor layer and a portion of the semiconductor film extending outward from the second semiconductor layer are in contact through an opening formed in a portion of the second insulating film; A high voltage semiconductor device according to claim (4). (6) The high voltage semiconductor device according to claim (4) or (5), wherein the semiconductor film is formed of polycrystalline silicon. (7) The high voltage semiconductor device according to claim (4) or (5), wherein the semiconductor film is formed of amorphous silicon.