JPH0370180A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To enable an FET in LDD structure to be formed with improved reproducibility without reducing power supply voltage by stopping etching exposing an etching end point detection film on a memory cell region when etching an upper side gate film. CONSTITUTION:An isolation oxide film 12 is formed around an element formation region on an Si substrate 11 and then a gate oxide film 13 is formed by thermal oxidation. Then, a lower-side poly Si film 14 as a lower-side gate film for forming gate and an oxide film 15 as an etching end detection film are grown in sequence on it by vapor growth. Then, the oxide film 15 at the FET formation region is eliminated by etching. A resist pattern 19 is formed at a region corresponding to the channel region on an oxide film 18 and the oxide film 18, a WSi film 17, and a poly Si film 16 are etched with it as a mask. At this time, detection of end point of etching can be made by the presence of the oxide film 15 remaining at an isolation region and an EPROM formation region. An oxide film is allowed to grow on the entire surface of the substrate and etchback is made to form a side wall 21. At this time, the oxide film 15 other than the gate and the lower part of side wall of the EPROM region is also eliminated by etching.

Description

[Detailed Description of the Invention] [Summary] LDD (Lightly Doped Drain)
Structure of MOS FET and floating gate non-volatile memory (EPROM).

Regarding the manufacturing method of EEPROM).

FIGS. 2(3) and 2(4) are methods using oblique ion implantation.

In FIG. 2(3), a gate oxide film 4 is formed on the St substrate 1, a gate (poly-Si film 5) is formed on it, and a low concentration S/D region 2 is formed by oblique ion implantation. Form.

In FIG. 2 (4), the oxide film is lengthened and etched back on the substrate to form sidewalls 8, and ions are implanted using the gate 5 and sidewalls 8 as implantation masks to form high concentration 51DN region 3. .

In addition, in order to create EPROMs and EEPROMs, a control gate is provided in the substrate as shown in Figure 3, and a floating gate is provided with an oxide film sandwiched in a single layer structure, or a single layer structure as shown in Figure 4, in which a control gate is provided in the substrate. Floating gate through oxide film on top, oxide film,
A two-layer gate consisting of a control gate is formed, and S/D j
Formation of the J [area also required a complicated process.

FIGS. 3(1) and 3(2) are structural diagrams showing an example of a single-layer gate EPROM.

In the figure, 31 is a substrate, 32 is a non-volatile memory section, floating gate (FG), 33 is a control gate (CG), 34
35 is a source, 35 is a drain, 36 is a covering insulating film, 37 is a wiring, and the space between the source and drain is a channel region.

Figures 4 (1) to (3) are cross-sectional views illustrating a conventional example of the manufacturing process of a device having a conventional LDD structure of PET with a small amount of overlap between the gate and the low-concentration slo 9M region and a 2N-EPROM device. be.

In FIG. 4(1), an isolation insulating film 42 is formed on a substrate 41, a first layer gate 44 is formed in the FET formation region on the left via a gate oxide film 43, and a gate oxide film is formed in the EPROM formation region on the right. 1st layer gate (FG) through 43
44. Oxidation H45 is used to form a second layer gate (CG) 46.

Next, the EPROM formation area is covered with a resist pattern 47.
Using this as an implantation mask, ions are implanted into the FET formation region to form a low concentration S/DH region 48 of the FET.

In FIG. 4(2), the resist pattern 47 is removed and the FET formation area is covered with a resist pattern 49.

Using this as an implantation mask, ions are implanted into the EPROM formation region to form the low concentration S/D region 50 of the EFROM.

In FIG. 4(2), the resist pattern 49 is removed, sidewalls 51 are formed on each gate, and ions are implanted over the entire surface of the substrate to form the high concentration S/D region 52 of the FET and the EPROM.
A high concentration S/D region 53 is formed.

As mentioned above, in the conventional example, S/D 6i area form precepts are converted into FHT
.

Each step was performed separately using an EPROM, and the process was complicated.

[Problem to be solved by the invention]

As shown in Figure 2 (1), when a natural oxide film is used as an etching stopper, biisotropic etching or special gas (
For example, CF4. Brz) must be used,
CCl4 or the like is used for a gate having a so-called polycide structure in which a silicide film of a refractory metal is formed on a poly-Si film to reduce the resistance of the gate electrode.

There is a problem in that this method cannot be applied to anisotropic etching or etching using uricide because the selectivity with respect to the natural oxide film cannot be obtained. Furthermore, since the natural oxide film itself does not have good reproducibility, the controllability of etching is not good.

Control etching in Figure 2 (2) is difficult.

Manufacturing variations will increase.

The oblique ion implantation method shown in FIGS. 2(3) and 2(4) poses a problem in that it is difficult to obtain a sufficient amount of overlap between the gate and the low concentration S/DON region.

The present invention uses a gate and a low concentration 5lD like the first two conventional examples.
It is possible to obtain a sufficient amount of overlap in the N region, to form FETs with a short channel LDD structure with good reproducibility without reducing the power supply voltage, and to form nonvolatile memory cells with good compatibility with this process. purpose.

[Means to solve the problem]

To solve the above problem, an isolation insulating film (12) is formed around the FET formation region and the floating gate type nonvolatile memory cell formation region on the semiconductor substrate (11).

A gate oxide film (13) and a lower gate film (13) are sequentially formed on the substrate.
14) A step of sequentially growing an etching end point detection film (15), a step of etching away the etching end point detection film at least in the gate 9TJ region of the FET formation region, and a step of growing an upper gate film (16) over the entire surface of the substrate. A step of growing an etching protection film (18) and patterning the etching protection film and the upper gate film.

forming a pattern consisting of the etching protection film and the upper gate film on the channel regions of the FET formation region and the memory cell formation region, respectively; covering the memory cell formation region with an implantation mask and passing the lower gate film through the substrate; Step (20) of implanting ions of a conductivity type opposite to that of the substrate to form lightly doped source/drain regions of the FET, and removing the implantation mask.

A step of forming a side wall (21) on the side surface of the pattern, etching the etching end point detection film using the pattern and the side wall as a mask, and etching the lower gate film using the side wall and the etching protection film as a mask. removing the substrate and implanting ions of a conductivity type opposite to that of the substrate into the substrate to form a high concentration source/drain region (22) of an FET and a source/drain region (23) of a memory cell. This is achieved by the manufacturing method.

[Effect]

In the present invention, when etching the upper gate film, the etching end point detection film on the memory cell area is exposed to stop the etching.
The lower gate film in the 9M region is hardly etched),
In addition, since the etching end point detection film is removed during etching when forming sidewalls, the lower gate film can be etched during etching during gate formation using the sidewalls and etching protection film as a mask. be.

Furthermore, by leaving the etching end point detection film in the memory cell area, this film is interposed between the upper and lower gate layers, and a two-layer gate structure is inevitably obtained.

〔Example〕

Figures 1 (1) to (7) are according to one embodiment of the present invention. LDD with overlapping gate electrode and low concentration S/D region
FIG. 3 is a cross-sectional view illustrating the formation of a structure.

The element formation area in the figure is the FET formation area on the left side and the E element formation area on the right side.
This is a FROM formation area.

In FIG. 1 (1), an element type TIi is formed on a Si substrate 11 using the LOCOS method, and a portion of M oxidation (SiO
□) Form the film 12, then form a gate oxide film I3 by thermal oxidation, and then deposit a lower poly-Si film with a thickness of approximately 1000 nm as a lower gate film for gate formation by vapor phase epitaxy (CVD). Membrane 14. An oxide film 15 having a thickness of about 500 mm is sequentially grown as an etching end point detection film.

In FIG. 1(2), the oxide film 15 in the PET type I'I2 region is removed by etching.

In FIG. 1(3), an upper polySiM2S film with a thickness of about 500 λ and a WSi film with a thickness of about 1200 λ are deposited on the entire surface of the substrate as an upper gate film for gate formation by CVD.
A film 17 is grown.

Further, on top of that, an etching protective film with a thickness of about 100 mm is applied when forming the side wall 21 in FIG. 1 (6) described later.
An oxide film 18 of 0λ is grown.

In FIG. 1(4), a resist pattern 19 is formed in a region corresponding to the channel region on the oxide film 18, and using this as a mask, the oxide film 18. WSi film 17. The poly-Si film I6 is etched.

In this etching, the oxide film is CHFz, WSi
is CCl4. PolySt was formed by reactive ion etching (RrE) using CCI.

At this time, the end point of etching is detected in the separation area or EPl.
? 0? This is possible due to the presence of the oxide film 15 remaining in the formation region.

In FIG. 1 (5), the BPROM formation head area is covered with a resist pattern, and using this as an implantation mask, phosphorus ions (P) are implanted into the substrate through the lower poly-Si film 14 to form a low concentration S/0 of PET. A region 20 is formed.

The P+ implantation conditions are an energy of 100 KeV and a dose profile of lXl0"cm-".

In FIG. 1(6), the resist pattern is removed.

An oxide film with a thickness of approximately 200 OA is formed over the entire surface of the substrate and is etched back to form side walls 21.

At this time, the oxide film 15 other than under the gate and sidewalls of the EFROM region is also etched away.

In FIG. 1(7), the lower poly-Si film 14 is etched using the sidewall 21 and oxide film 18 as a mask.

Next, arsenic ions (As') are implanted into the substrate to form the high concentration S/D region 22 of the FET and the S/D region 23 of the EPROM.

The implantation conditions for As'' are: energy 50 KeV, dose: !l 5XlOIScm-''.

After this, activation annealing of the implanted ions is performed.

The FET is completed through normal processes.

According to this method, since the end point of etching can be detected, it is possible to use an etching device and gas with strong anisotropy, so polycide can be used as the gate material, and gate wiring resistance can be lowered.

According to the embodiment, the amount of overlap between the gate and the low concentration S106N region can be as large as about 0.2 μm, and as a result, an FET with an effective gate length of 0.5 μm can be operated with a 5ν power supply.

Furthermore, a double-layer gate nonvolatile memory cell can be formed with almost no additional steps.

[Effects of the Invention] As explained above, according to the present invention, the gate and the low concentration S
It is now possible to obtain a sufficient amount of over-variation in the /D region, and it is possible to form FETs with an LDD structure with good reproducibility without lowering the power supply voltage. It became possible to form cells.

[Brief explanation of drawings]

Figures 1 (1) to (7) are according to one embodiment of the present invention. LD with overlapping gate electrode and low concentration SiD region
FIG. 3 is a cross-sectional view illustrating the formation of a D structure. FIGS. 2(1) to 2(4) are based on the conventional example. FIG. 3 is a cross-sectional view illustrating the formation of an LDD structure in which a gate electrode and a low concentration S/D region overlap. FIGS. 3(1) and 3(2) are structural diagrams showing an example of a single-layer gate EPROM. Figures 4 (1) to (3) show conventional LDD structure FETs with a small amount of overlap between the conventional gate and low concentration S/D region.
FIG. 3 is a cross-sectional view illustrating a conventional example of a manufacturing process of a device having an EFROM (and a two-layer gate EFROM). In fig. 11 is a semiconductor substrate, which is a Si substrate. 12 is an isolation oxide film. 13 is a gate oxide film. 14 is a lower gate film, which is a lower polySt film. 15 is an oxide film which is an etching end point detection film. 16 is an upper gate film, which is an upper poly-Si film. 17 is the old i membrane. 18 is an oxide film which is an etching protection film when forming side walls. 19 is a resist pattern. 20 is the low concentration S/0 head area of FET. 21 is a side wall made of an oxide film. 22 is FET (7) High concentration SiDa area. 23 is the first town section of the actual example of S/D area of the memory cell (! no 1) r of the actual rejection example! fr Day 10 (2) (1) Different planes ('2) A-A# plane 1 layer EFROM life 1 Chopstick diagram ) Number 4 of each leg match 1 (FE cho + EP shaku O bar)

Claims (1)

[Claims] An isolation insulating film (12) is formed around the FET formation region and the floating gate type nonvolatile memory cell formation region on the semiconductor substrate (11), and a gate oxide film (13) is sequentially formed on the substrate. , a step of sequentially growing a lower gate film (14) and an etching end point detection film (15), a step of removing the etching end point detection film at least in the gate region of the FET formation region, and a step of growing an upper gate film (14) over the entire surface of the substrate. (16) and an etching protective film (18), and patterning the etching protective film and the upper gate film to form the etching protective film and the upper gate film on the channel regions of the FET formation region and the memory cell formation region, respectively. forming a pattern consisting of an upper gate film; and covering the memory cell formation region with an implantation mask and implanting ions of a conductivity type opposite to that of the substrate through the lower gate film to form a low concentration source/drain of the FET. forming a region (20), removing the implantation mask and forming sidewalls (21) on the sides of the pattern;
) and etching the etching end point detection film using the pattern and the sidewall as a mask; etching away the lower gate film using the sidewall and the etching protection film as a mask; Ions of the opposite conductivity type are implanted to form the highly doped source/drain region (22) of the FET and the source/drain region (22) of the memory cell.
23) A method for manufacturing a semiconductor device, comprising the step of forming.