JPH03233974A - Method for manufacturing non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten reading time and to reduce a cost by forming a floating gate in a groove provided on a semiconductor substrate. CONSTITUTION:A floating gate electrode 5 in which its almost thickness is disposed in a groove 12 is formed in contact with first insulating films 4 formed on the side and bottom of the groove 12 on the surface of a first conductivity type semiconductor substrate 20, a second insulating film 7 is formed on the exposed surface, a control gate electrode 8 is formed on the exposed surface of the electrode 5 through the second insulating film, and a second conductivity type region 11 is formed on the surface of the substrate 20 through the groove. Thus, 4-layer continuous etching steps are eliminated a memory cell can be patterned simultaneously with a peripheral transistor, and reading time, a cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices, particularly EPROM (Electrically Programmable
The present invention relates to a method of manufacturing an ultraviolet erasable nonvolatile semiconductor memory device such as a ROM (ROM).

EP using conventional technology floating gate type non-volatile memory
In a ROM, a memory element is formed by stacking a floating gate electrode and a control gate electrode, and both gate electrodes are usually formed of a polycrystalline silicon film.

Therefore, the patterning of the memory portion is normally performed by successively etching both gate electrodes using one mask, and therefore cannot be performed simultaneously with the patterning of peripheral transistors. The above content will be explained using FIG. 3. As shown in Figure 3(a), P
E element isolated by selective oxide film 1 on type semiconductor substrate 20
A first gate oxide film 4 and a first polycrystalline silicon film 5 that will become a floating gate electrode are grown on the PROM formation region 2 and the peripheral transistor formation region 3, and the areas other than the EPROM formation region 2 are etched using a photoresist 6. do.

Next, as shown in FIG. 3(b), a second gate oxide film 7 is formed.
and grow a second polycrystalline silicon film 8 that will become a control gate electrode and a gate electrode of a peripheral transistor,
Using photoresist 9, the entire EPROM formation region 2 and the peripheral transistor formation region 3 other than the gate portion are etched, and only the peripheral transistors are patterned. Next, as shown in FIG. 3(C), the memory element in the EPROM formation area 2 is patterned using the photoresist 10. At this time, in the EPROM formation region 2, four layers of the first and second polycrystalline silicon films 5 and 8 and the first and second gate oxide films 4 and 7 are successively etched. Further, at this time, the entire peripheral transistor formation region 3 is covered with the resist 10. Thereafter, the resist 10 is removed and, as shown in FIG. 3(d), impurities such as arsenic are ion-implanted at a high concentration to form source and drain regions 11 to form a transistor.

Problems to be Solved by the Invention In the manufacturing method shown in FIG. Etching is required, and it is difficult to establish etching conditions (especially dry etching conditions for polycrystalline silicon films) and maintain them in a stable state. Furthermore, it is necessary to form the memory element and the peripheral transistor at different mask levels, which increases the number of photolithography steps and etching steps, resulting in an increase in both lead time and cost.

The present invention solves the above problems, and eliminates the difficult-to-control four-layer continuous etching process of two layers of polycrystalline silicon and two layers of silicon oxide film when patterning a memory element. An object of the present invention is to provide a method for manufacturing a semiconductor memory device that can be patterned simultaneously with peripheral transistors.

Means for Solving the Problem A method for manufacturing a nonvolatile semiconductor memory device according to the present invention to solve the problem includes a step of forming a groove on the surface of a first conductivity type semiconductor substrate, and forming a first groove on the side and bottom surfaces of the groove. forming a floating gate electrode in contact with the first insulating film and having at least most of its thickness within the groove; and forming a second insulating film on the exposed surface of the floating gate electrode. forming an insulating film; forming a control gate electrode on the exposed surface of the floating gate electrode via the second insulating film; The method includes a step of forming a second conductivity type region opposite to the first conductivity type.

Effect: With this method, the first gate oxide film and the first polycrystalline silicon film of the memory element are provided in the trench, so that the second gate oxide film and the second polycrystalline silicon film, which will become the control gate electrode, are formed on the substrate. The memory element structure is completed only by patterning the silicon film. Therefore, the conventional four-layer continuous patterning is no longer necessary, and the patterning of the second gate oxide film and the second polycrystalline silicon film can be performed simultaneously with the patterning of the peripheral transistors, and the masking process and etching process are performed separately. 1 area.

EXAMPLE Hereinafter, an example of the method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional structure of an EPROM memory element portion according to the present invention. In FIG. 1, 1 is a P-type semiconductor substrate 20.
A selective oxide film formed on top for element isolation, 11 a source/drain region (n type), 12 a P type semiconductor substrate 2
0, 4 is a first gate oxide film, 5 is a first polycrystalline silicon film that becomes a floating gate electrode, 7 is a second gate oxide film, and 8 is a second gate oxide film that becomes a control gate electrode. This is a polycrystalline silicon film.

Next, an example of the manufacturing method of the present invention is shown in FIGS. 2(a) to 2(e). As shown in FIG. 2(a), a P-type semiconductor substrate 20
A width of about 0.5 μm and a depth of about 0.6 μm is formed at the center of the EPROM formation region 2 separated by the selective oxide film 1 formed above.
The groove portion 12 is formed using a normal photolithography technique using a resist 13 and a dry etching technique. Next, as shown in FIG. 2(b), the resist 13 is removed and oxidized for about 30 minutes at a temperature of, for example, 900° C. in a pyrogenic oxidizing atmosphere to grow a first gate oxide film 4 of about 300 Å. Subsequently, at a temperature of 600°C, Si
About 3000 first polycrystalline silicon films 5 are grown by thermal decomposition of SiH4 gas in an H4 gas atmosphere. Then, at a temperature of 900℃, PH3 gas or POCi! 3
Introduce gas and perform phosphorus doping. After removing the phosphor glass layer on the surface, a resist 14 is applied to the surface to a thickness of about 10,000 yen. Next, as shown in Figure 2 (C),
The resist 14 and the first polycrystalline silicon film 5 are etched back under conditions such that the etching selectivity between the resist and the polycrystalline silicon film is 1. As a result, the first polycrystalline silicon film 5 is completely etched off except for what remains in the groove formed in the substrate. Thereafter, the first gate oxide film 4 on the surface is removed by wet etching. Next, as shown in FIG. 2(d), the surface of the substrate is diluted and oxidized in an atmosphere of a mixed gas of N2 and 02 (N2:02=10:1) at a temperature of, for example, 1100°C, and a second gate is formed. The oxide film 7 is placed on the first polycrystalline silicon film 5 at a distance of about 400 A, and the peripheral semiconductor substrate 2
Grow about 25OA on top of 0. Subsequently, a second polycrystalline silicon film 8 is grown to a thickness of about 4000 Å under the same conditions as when the first polycrystalline silicon film 5 was grown. Furthermore, after removing the phosphorus dope and the surface phosphorus glass layer, resist 1
5, the second polycrystalline silicon film 8 is patterned using normal photolithography and dry etching techniques to form a control gate electrode of the memory element on the EPROM formation region 2 and a control gate electrode of the memory element on the peripheral transistor formation region 3. A gate electrode is formed at the same time. Thereafter, second gate oxide film 7 is removed by wet etching. Next, as shown in Fig. 2(e), for example, the acceleration voltage is 40K.
Arsenic ions are implanted at a dose of 4 x 10 I5am, -2 at eV, and a source/drain region 11 for a memory element is formed on the EPROM formation region 2 and a peripheral transistor formation region 3 is formed by a self-alignment method.
Second, source/drain regions 11 are simultaneously formed. In this way, EPROM memory elements and peripheral transistors can be formed.

In this embodiment, a polycrystalline silicon film is used as the gate electrode material of the control gate of the memory element and the peripheral transistor, but aluminum or a high melting point metal may also be used as the gate electrode material. Alternatively, a P-channel transistor may be formed using an N-type semiconductor substrate.

Effects of the Invention As described above, the present invention relates to a method for manufacturing a floating gate type non-volatile semiconductor memory device, in which a floating gate portion is formed in a groove provided on a semiconductor substrate, thereby making it difficult to establish conditions and ensuring a stable etching state. This is an excellent method that can shorten lead time and reduce costs because it eliminates the need for four-layer continuous patterning in the memory element section, which is difficult to maintain, and allows formation of control gates in the memory element section and gates of peripheral transistors at the same time. A method for manufacturing a nonvolatile semiconductor memory device can be realized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a memory element portion of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing steps for obtaining the configuration shown in FIG. 1, and FIG. 3 is a conventional FIG. 3 is a cross-sectional view showing the manufacturing process of a memory element portion of a semiconductor memory device according to the method. 4...First gate oxide film, 5...First polycrystalline silicon film, 6, 9, 10.13, 14.1
5... Resist, 7... Second gate oxide film, 8... Second polycrystalline silicon film, 11
...Source/drain region (n type), 12...
...Groove, 20...P-type semiconductor substrate.

Claims (1)

[Claims] forming a groove on the surface of a first conductivity type semiconductor substrate; forming a first insulating film on the side and bottom surfaces of the groove;
forming a floating gate electrode in contact with the first insulating film and having at least most of its thickness within the groove; forming a second insulating film on the exposed surface of the floating gate electrode; forming a control gate electrode on the surface of the floating gate electrode via a second insulating film; and forming a second conductivity type opposite to the first conductivity type on the surface of the first conductivity type semiconductor substrate sandwiching the groove. A method of manufacturing a nonvolatile semiconductor memory device, including a step of forming a mold region.