JPH0355437B2 - - Google Patents
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- Publication number
- JPH0355437B2 JPH0355437B2 JP21782186A JP21782186A JPH0355437B2 JP H0355437 B2 JPH0355437 B2 JP H0355437B2 JP 21782186 A JP21782186 A JP 21782186A JP 21782186 A JP21782186 A JP 21782186A JP H0355437 B2 JPH0355437 B2 JP H0355437B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- temperature
- group
- compound semiconductor
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 238000000034 method Methods 0.000 description 45
- 239000000758 substrate Substances 0.000 description 45
- 239000013078 crystal Substances 0.000 description 38
- 230000008569 process Effects 0.000 description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 27
- 239000004065 semiconductor Substances 0.000 description 24
- 150000001875 compounds Chemical class 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 21
- 238000004140 cleaning Methods 0.000 description 8
- 238000002109 crystal growth method Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000002484 cyclic voltammetry Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000009396 hybridization Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- -1 trichlene Substances 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体の結晶成長方法、特には
面方位(100)のSi基板上にGaAs等の−族
化合物半導体をエピタキシヤル成長させる化合物
半導体の結晶成長方法に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for growing crystals of compound semiconductors, and in particular to a compound semiconductor method for epitaxially growing a - group compound semiconductor such as GaAs on a Si substrate with a plane orientation of (100). This invention relates to a method for growing crystals.
Si基板上にGaAs等の化合物半導体を結晶成長
させ、良質な結晶、例えばGaAs基板上へ結晶成
長した結晶と同程度な品質の結晶が得られれば、
Si半導体と化合物半導体両者の好ましい点を有す
る新規デバイスの展開が考えられる。例えば、
SiLSI上への化合物半導体発光デバイスの作成
等、新しい広い意味でのハイブリツド化が可能と
なる。
If we can grow a compound semiconductor such as GaAs on a Si substrate and obtain a high-quality crystal, for example, a crystal with the same quality as a crystal grown on a GaAs substrate,
It is possible to develop new devices that have the advantages of both Si semiconductors and compound semiconductors. for example,
Hybridization will become possible in a new and broader sense, such as the creation of compound semiconductor light-emitting devices on SiLSI.
Si基板上への−族化合物半導体の結晶成長
においては、結晶成長技術上2つの問題点があ
る。すなわち、(1)格子定数のずれが著しく大き
い。例えばGaAsの場合4%以上となる。(2)Siに
対してGaAsなどは2元半導体であり、極性を有
する。 There are two problems in terms of crystal growth technology when growing a - group compound semiconductor crystal on a Si substrate. That is, (1) the deviation of the lattice constant is extremely large. For example, in the case of GaAs, it is 4% or more. (2) Unlike Si, GaAs is a binary semiconductor and has polarity.
これらの問題のため従来法ではSi基板とGaAs
結晶の間にまずバツフア層を成長させている。バ
ツフア層としては例えばGaAsと格子定数の差の
少い単元半導体Geを用いたり、低温成長させた
GaAs層を用いたりしている。 Due to these problems, the conventional method uses Si substrates and GaAs substrates.
First, a buffer layer is grown between the crystals. For the buffer layer, for example, a unitary semiconductor Ge with a small difference in lattice constant from GaAs may be used, or a layer grown at a low temperature may be used.
A GaAs layer is also used.
この従来例のうち低温成長GaAsバツフア層を
用いる方法を第2図に示す。この方法は
Japanese Journal of Applied Physics、24(6)、
6月(1985年)、391頁によつた。 Among these conventional methods, a method using a low temperature grown GaAs buffer layer is shown in FIG. This method is
Japanese Journal of Applied Physics, 24(6),
June (1985), p. 391.
しかしながら、これらバツフア層を用いた場合
にも以下のような問題が生ずる。すなわち、(1)バ
ツフア層成長条件が完全に把握されていないた
め、バツフア層の品質がばらつき、その上に成長
するGaAs結晶の品質が変動し、結晶成長の再現
性が悪くなる。また(2)成長層の安定性(経時変
化)に対してもバツフア層が存在するゆえに信頼
性が低下してくる等の問題がある。更に当然のこ
とながら(3)GaAs基板上へのGaAs成長に比して、
複雑な工程をとる必要がある。
However, even when these buffer layers are used, the following problems occur. That is, (1) the buffer layer growth conditions are not completely understood, so the quality of the buffer layer varies, the quality of the GaAs crystal grown on it varies, and the reproducibility of crystal growth deteriorates. Furthermore, there are also problems with (2) stability (change over time) of the grown layer, such as reduced reliability due to the presence of the buffer layer. Furthermore, as a matter of course, (3) compared to GaAs growth on a GaAs substrate,
It requires a complicated process.
本発明は、Si基板上へのGaAs等の化合物半導
体を結晶成長させる時に用いられている従来の方
法すなわち低温成長バツフア層を用いる方法、に
含まれる問題点を解決するためのものであり、そ
の目的とするところは、再現性および成長層の安
定性を向上させ、工程を簡略化した化合物半導体
の結晶成長方法を提供することにある。 The present invention is intended to solve the problems included in the conventional method used to grow crystals of compound semiconductors such as GaAs on Si substrates, that is, the method using a low-temperature growth buffer layer. An object of the present invention is to provide a method for growing compound semiconductor crystals that improves reproducibility and stability of the grown layer and simplifies the process.
すなわち本発明の化合物半導体の結晶成長方法
は、−族化合物半導体をSi基板上に分子線エ
ピタキシヤル成長法により結晶成長させる方法に
おいて、
(a) 科学処理により清浄化したSi基板を
10-10Torr以下の超高真空下で1000℃以上の温
度で30分以上加熱処理を行い、次いで該Si基板
を一度600℃以下の温度まで降温する第1の工
程と、
(b) 真空中で該Si基板上にV族元素の分子線を照
射しながら該Si基板を600〜750℃の範囲内の温
度に昇温する第2の工程と、
(c) 族および族元素の各分子線を同時に前記
範囲内の温度に昇温した該Si基板上に照射して
族および族化合物半導体を該Si基板にエピ
タキシヤル成長させる第3の工程、とからなる
ことを特徴とする。
That is, the compound semiconductor crystal growth method of the present invention is a method for growing crystals of - group compound semiconductors on a Si substrate by molecular beam epitaxial growth method, which includes: (a) growing a Si substrate cleaned by a chemical treatment;
A first step of performing heat treatment at a temperature of 1000°C or more for 30 minutes or more under an ultra-high vacuum of 10 -10 Torr or less, and then cooling the Si substrate once to a temperature of 600°C or less; (b) in a vacuum; (c) a second step of heating the Si substrate to a temperature within a range of 600 to 750°C while irradiating the Si substrate with a molecular beam of a group V element; and a third step of simultaneously irradiating the Si substrate heated to a temperature within the above range to epitaxially grow group and group compound semiconductors on the Si substrate.
本発明の方法では、従来方法と異なりSi基板洗
浄後のGaAs結晶成長前の熱処理工程に十分な検
討を加え、最適条件を見出すこのにより、従来方
法における問題点の発生源である低温成長バツフ
ア層を必要としない工程となつている。本方法は
Si基板の洗浄工程、その熱処理工程および分子線
エピタキシヤル成長法による、通常GaAs基板上
に結晶成長させる条件と同一の条件による結晶成
長工程からなつている。これによりバツフア層成
長工程が介在することもなく、出来上つた構造の
中にもバツフア層のないものを得ることができ、
バツフア層に起因する従来方法に伴う上記3点の
問題を改善することができる。 In the method of the present invention, unlike the conventional method, sufficient consideration is given to the heat treatment process after cleaning the Si substrate and before GaAs crystal growth, and the optimum conditions are found. It has become a process that does not require This method is
The process consists of a cleaning process for the Si substrate, a heat treatment process, and a crystal growth process using the molecular beam epitaxial growth method under the same conditions as those used for crystal growth on a normal GaAs substrate. This eliminates the need for a buffer layer growth process and allows the resulting structure to have no buffer layer.
The above three problems associated with the conventional method due to the buffer layer can be improved.
本発明による化合物半導体の結晶成長方法の基
本構成要件としては、まず面方位(100)のSi基
板の洗浄工程、次に超高真空下(真空度
10-10Torr以下)での加熱処理工程、その後につ
づくSi基板上へのGaAsあるいはその他化合物半
導体の分子線エピタキシヤル成長法による結晶成
長工程が挙げられる。 The basic components of the compound semiconductor crystal growth method according to the present invention include first a cleaning process of a Si substrate with a plane orientation of (100), then an ultra-high vacuum (vacuum degree
10 -10 Torr or less), followed by a crystal growth process using molecular beam epitaxial growth of GaAs or other compound semiconductors on a Si substrate.
Si基板の洗浄工程は通常の有機溶剤による脱脂
工程の次に、科学エツチ液による表面処理を数回
繰返すことにより清浄表面を形成する工程からな
つている。この工程の最終段階ではSi表面は薄い
SiO2膜に覆われることになる。このSiO2膜は洗
浄工程から次の熱処理工程間における基板移送時
に基板表面を保護する役目をする。次にこのSi基
板を超高真空下のチエンバーの中に挿入する。こ
こで熱処理工程となる。この工程では、徐々にSi
基板の温度を上昇させ表面のSiO2およびSiC膜を
除去(800℃〜900℃)し、次に更に温度を上昇さ
せ(1000℃〜1050℃)Si表面の結晶形態をGaAs
成長の都合のよい形に変えてゆく。この高温
(1000℃〜1050℃)、30分の熱処理でSi表面がどう
変わるかを第3図を用いて次に示す。まず、
SiO2膜などが除去されて洗浄になつたSi表面はSi
原子の配列に1原子層単位のステツプ(凹凸)が
生じている。これが更に高温の(1000〜1050℃)
熱処理を施すと、高温の熱処理によりSi表面の原
子配列に2原子層のステツプが生じるようになる
と考えられ、このようになると2元結晶である
−族化合物半導体の結晶成長では成長方向に原
子配列の整合性が良くなり単結晶成長が可能とな
つてくる。もし、1原子層のステツプのままであ
ると、ステツプのところにグレイン境界ができ完
全な単結晶にならない。最終の結晶成長工程では
通常GaAs基板上に結晶成長する場合と同一条件
(基板温度600℃〜700℃、族元素/族元素分
子線フラツクス比1〜5、成長速度0.5〜2μm/
hr)で分子線エピタキシヤル成長する。 The cleaning process for Si substrates consists of a conventional degreasing process using an organic solvent, followed by a process of repeating surface treatment using a chemical etchant several times to form a clean surface. At the final stage of this process, the Si surface is thin.
It will be covered with a SiO 2 film. This SiO 2 film serves to protect the substrate surface during substrate transfer between the cleaning process and the next heat treatment process. Next, this Si substrate is inserted into a chamber under ultra-high vacuum. Here comes the heat treatment step. In this process, Si
The temperature of the substrate is raised to remove the SiO 2 and SiC films on the surface (800°C to 900°C), and then the temperature is further raised (1000°C to 1050°C) to change the crystal morphology of the Si surface to GaAs.
Change it into a form that is convenient for growth. How the Si surface changes after heat treatment at this high temperature (1000°C to 1050°C) for 30 minutes is shown below using Figure 3. first,
The Si surface, which has been cleaned after removing the SiO 2 film, is Si
Steps (unevenness) occur in the arrangement of atoms in units of one atomic layer. This is even higher temperature (1000-1050℃)
When heat treatment is performed, it is thought that a step of two atomic layers will occur in the atomic arrangement on the Si surface due to the high temperature heat treatment, and if this happens, the atomic arrangement will change in the growth direction in the crystal growth of - group compound semiconductors, which are binary crystals. The consistency of the crystals becomes better and single crystal growth becomes possible. If the step remains one atomic layer, a grain boundary will occur at the step and it will not become a perfect single crystal. The final crystal growth step is carried out under the same conditions as for crystal growth on a normal GaAs substrate (substrate temperature 600°C to 700°C, group element/group element molecular beam flux ratio 1 to 5, growth rate 0.5 to 2 μm/
hr) by molecular beam epitaxial growth.
本発明の実施例は化合物半導体としてGaAsを
中心にして記述するが、この他にAlxGa(1-x)As
(0<x≦1)あるいはその他の−族化合物
半導体においても本発明の結晶成長方法は適用で
きるものである。また導電性についても主として
Siドープのn形について記述するが、この他のド
ーパント材およびP形についても同様に適用でき
る。ちなみに、結晶材料が異なつた場合には、Si
基板の熱処理工程は同一でよいが、結晶成長工程
における成長条件は材料に依存して異なる点は注
意する必要がある。この場合も成長条件は従来条
件と同一としてよい。 The embodiments of the present invention will be mainly described using GaAs as a compound semiconductor, but in addition to this, Al x Ga (1-x) As
The crystal growth method of the present invention can also be applied to (0<x≦1) or other - group compound semiconductors. Also, regarding conductivity,
Although Si-doped n-type will be described, other dopant materials and P-type can be similarly applied. By the way, if the crystal material is different, Si
Although the heat treatment process for the substrate may be the same, it must be noted that the growth conditions in the crystal growth process differ depending on the material. In this case as well, the growth conditions may be the same as the conventional conditions.
また、実施例ではSi基板が(100)面の例につ
いて述べるが、(111)(110)などの他の面につい
ても適用できる。 Further, in the embodiment, an example in which the Si substrate has a (100) plane will be described, but the present invention can also be applied to other planes such as (111) and (110).
以下の実施例において本発明を更に詳しく説明
する。なお、本発明は下記実施例に限定されるも
のではない。
The invention will be explained in more detail in the following examples. Note that the present invention is not limited to the following examples.
本発明による結晶成長法の実施例を次に示す。
基本構成は第1図に示す、洗浄工程、熱処理工
程、結晶成長工程からなつている。 Examples of the crystal growth method according to the present invention are shown below.
The basic configuration is shown in FIG. 1 and consists of a cleaning process, a heat treatment process, and a crystal growth process.
まず洗浄工程では、結晶成長用面方位(100)
のSi基板、例えばn形、ρ=2〜3Ω・cm、2イ
ンチφ)について有機溶剤例えばトリクレン、ア
セトン、イソプロピルアルコール等を用い超音波
印加による脱脂洗浄を15分間程行う。次に科学エ
ツチ液による処理を行う。ここではまずエツチ液
(H2SO4:H2O2=4:1)に5分間程Si基板をつ
けて表面に薄いSiO2膜を形成する。次にその
SiO2膜を5%HF液でエツチ除去する。この工程
を数回行つた後、Si基板をH2SO4:H2O2=4:
1溶液中に10分程つけ薄いSiO2膜を表面に形成
する。この膜は基板を真空室中に入れるまでの移
送の段階で表面が汚染されるのを防ぐ目的でつけ
る。 First, in the cleaning process, the plane orientation for crystal growth (100) is
A Si substrate (for example, n-type, ρ = 2 to 3 Ω·cm, 2 inches φ) is degreased and cleaned for about 15 minutes by applying ultrasonic waves using an organic solvent such as trichlene, acetone, isopropyl alcohol, etc. Next, it is treated with a scientific etchant. Here, first, the Si substrate is soaked in an etchant (H 2 SO 4 :H 2 O 2 =4:1) for about 5 minutes to form a thin SiO 2 film on the surface. Then that
Etch the SiO 2 film with 5% HF solution. After performing this process several times, the Si substrate was heated to H 2 SO 4 :H 2 O 2 =4:
1. Soak in solution for about 10 minutes to form a thin SiO 2 film on the surface. This film is applied to prevent the surface of the substrate from being contaminated during the transportation stage before it is placed into the vacuum chamber.
次に洗浄工程を通したSi基板を分子線エピタキ
シヤル成長装置の準備室中に入れて加熱処理を行
う。処理条件は超高真空下(真空度10-10Torr以
下)で900℃〜1050℃、30分間とする。 Next, the Si substrate that has undergone the cleaning process is placed in a preparation chamber of a molecular beam epitaxial growth apparatus and subjected to heat treatment. The processing conditions are 900°C to 1050°C for 30 minutes under ultra-high vacuum (vacuum level 10 -10 Torr or less).
本実施例は最適処理温度を求める目的で上記温
度範囲にて50℃ずつ温度を変えた4条件で行つ
た。その後基板温度を300℃まで下げ超高真空下
にて成長室まで移送し、結晶成長工程に入る。 This example was carried out under four conditions in which the temperature was varied by 50° C. within the above temperature range in order to find the optimum processing temperature. Thereafter, the substrate temperature is lowered to 300°C and the substrate is transferred to a growth chamber under ultra-high vacuum to begin the crystal growth process.
この工程では分子線エピタキシヤル成長法を採
用している。まずAs源の温度を上昇させ、As4、
As2等の分子線をSi基板に当てながら基板温度を
600℃(成長温度)まで上昇させる。この温度で
族元素/族元素フラツクス比3、成長速度
1μm/hrの条件でSiをドープしながらn−GaAs
層を約2μm結晶成長させた。成長したn−GaAs
層の結晶性評価としては干渉顕微鏡による表面モ
ホロジーの観察、ホール測定およびC−V測定に
よる移動度および電子濃度の測定を行つた。 This process uses molecular beam epitaxial growth. First, the temperature of the As source is increased, and As 4 ,
While applying a molecular beam such as As 2 to the Si substrate, the substrate temperature is adjusted.
Raise to 600℃ (growth temperature). At this temperature, group element/group element flux ratio 3, growth rate
n-GaAs while doping with Si under the condition of 1 μm/hr.
The layer was crystal grown to approximately 2 μm. Grown n-GaAs
To evaluate the crystallinity of the layer, the surface morphology was observed using an interference microscope, and the mobility and electron concentration were measured using Hall measurement and CV measurement.
表面モホロジーの観察結果を第4図〜第7図に
示す。熱処理温度により表面モホロジーは著しい
相違を示し、処理温度900℃(第4図)、950℃
(第5図)ではグレイン成長した際特有な境界の
モホロジーが認められる。これに対して、1000℃
(第6図)、1050℃(第7図)では表面状態は均一
となりモホロジーは認められなくなり、良好な単
結晶が得られていると思われる。次にホール測定
結果を第8図に示す。熱処理温度900℃、950℃で
は電子のホール移動度が非常に低くなつている。
これに対して、1000℃、1050℃では2000(cm2/V.
S)以上の値を示している。ホール移動度でみる
限りにおいては1050℃よりも1000℃での熱処理の
ほうが良好な結果が得られるようである。ホール
測定は深さ方向に対して平均化した情報しか得ら
れないために、C−V測定法を用いて深さ方向の
電子濃度分布を求めてみた。熱処理温度950℃、
1000℃の結果を第9図に示す。両結果ともSi基板
界面から遠ざかるに従つてGaAs結晶性が良好に
なつておりそれに伴つてドープされたSiの活性化
率が向上し電子濃度の増加が認められている様子
が分かる。 The observation results of surface morphology are shown in FIGS. 4 to 7. The surface morphology showed significant differences depending on the heat treatment temperature, with treatment temperatures of 900℃ (Figure 4) and 950℃.
(Fig. 5), a unique boundary morphology is observed when grains grow. On the other hand, 1000℃
At 1050°C (Fig. 6) and 1050°C (Fig. 7), the surface condition became uniform and no morphology was observed, indicating that a good single crystal was obtained. Next, the Hall measurement results are shown in FIG. At heat treatment temperatures of 900°C and 950°C, the electron hole mobility becomes extremely low.
On the other hand, at 1000℃ and 1050℃, it is 2000 (cm 2 /V.
S) or higher. As far as hole mobility is concerned, heat treatment at 1000°C appears to yield better results than at 1050°C. Since hole measurements can only obtain information averaged in the depth direction, we used the CV measurement method to determine the electron concentration distribution in the depth direction. Heat treatment temperature 950℃,
The results at 1000°C are shown in Figure 9. Both results show that as the distance from the Si substrate interface increases, the GaAs crystallinity improves, and the activation rate of doped Si improves, leading to an increase in electron concentration.
その増加の割合は熱処理温度1000℃の場合のほ
うが著しく、層厚2μm程度成長させれば、同じ
条件でGaAs基板上に成長して得られるn−
GaAs層の電子濃度にほぼ等しい値が得られてい
る。 The rate of increase is more remarkable when the heat treatment temperature is 1000°C, and if the layer is grown to a thickness of about 2 μm, the n-
A value approximately equal to the electron concentration of the GaAs layer was obtained.
以上3つの評価結果から、本実施例における熱
処理温度の最適温度範囲は1000〜1050℃と判断さ
れる。また、デバイス作成に十分な結晶性の良い
層はSi基板界面から2μm以上結晶成長した層で得
られることも分つた。 From the above three evaluation results, it is determined that the optimum temperature range of the heat treatment temperature in this example is 1000 to 1050°C. It was also found that a layer with good crystallinity sufficient for device fabrication can be obtained from a layer with crystal growth of 2 μm or more from the Si substrate interface.
上述のように本発明の化合物半導体の結晶成長
方法は、Si基板を所定条件下で熱処理し、次いで
該Si基板上に族元素の分子線を照射しながら該
Si基板を所定温度に昇温し、次いで族および
族元素の各分子線を同時に該Si基板上に照射して
−族化合物半導体を該Si基板上にエピタキシ
ヤル成長させるため、Si基板の熱処理温度を適当
に選べばバツフア層成長なしでGaAs結晶を成長
させることができる。また、本方法ではバツフア
層成長を介在させた従来の結晶成長法に比べ、バ
ツフア層を形成する工程が省略でき、これにより
結晶成長工程の再現性が従来法よりも改善され
る。その他に成長後に発生し得るバツフア層に起
因する経時劣化の発生を抑えることができる。
As described above, the compound semiconductor crystal growth method of the present invention heat-treats a Si substrate under predetermined conditions, and then irradiates the Si substrate with a molecular beam of a group element while
The Si substrate is heated to a predetermined temperature, and then molecular beams of group and group elements are simultaneously irradiated onto the Si substrate to epitaxially grow the − group compound semiconductor on the Si substrate. By choosing appropriately, GaAs crystals can be grown without buffer layer growth. Furthermore, in this method, compared to the conventional crystal growth method in which growth of a buffer layer is interposed, the step of forming a buffer layer can be omitted, thereby improving the reproducibility of the crystal growth process compared to the conventional method. In addition, it is possible to suppress the occurrence of deterioration over time due to a buffer layer that may occur after growth.
第1図は本発明の化合物半導体の結晶成長方法
の説明図、第2図は従来の化合物半導体の結晶成
長方法の説明図、第3図は本発明の方法における
熱処理工程での結晶表面形態の変動を示す説明
図、第4図ないし第7図は本発明の方法において
各々の熱処理温度900℃、950℃、1000℃および
1050℃にして成長させたときのn−GaAs結晶の
構造(表面モホロジー)を示す顕微鏡写真、第8
図は本発明の方法において熱処理温度とn−
GaAs結晶のホール移動度との関係を示すグラ
フ、第9図は本発明の方法で得られたn−GaAs
の電子濃度の深さ方向分布を示すグラフである。
FIG. 1 is an explanatory diagram of the compound semiconductor crystal growth method of the present invention, FIG. 2 is an explanatory diagram of the conventional compound semiconductor crystal growth method, and FIG. 3 is an explanatory diagram of the crystal surface morphology in the heat treatment step in the method of the present invention. Figures 4 to 7 are explanatory diagrams showing variations at heat treatment temperatures of 900°C, 950°C, 1000°C and
Micrograph showing the structure (surface morphology) of n-GaAs crystal when grown at 1050℃, No. 8
The figure shows heat treatment temperature and n-
Figure 9 is a graph showing the relationship between the hole mobility of GaAs crystal and the n-GaAs obtained by the method of the present invention.
3 is a graph showing the depth distribution of electron concentration in FIG.
Claims (1)
ピタキシヤル成長法により結晶成長させる方法に
おいて、 (a) 科学処理により清浄化したSi基板を
10-10Torr以下の超高真空下で1000℃以上の温
度で30分以上加熱処理を行い、次いで該Si基板
を一度600℃以下の温度まで降温する第1の工
程と、 (b) 真空中で該Si基板上にV族元素の分子線を照
射しながら該Si基板を600〜750℃の範囲内の温
度に昇温する第2の工程と、 (c) 族および族元素の各分子線を同時に前記
範囲内の温度に昇温した該Si基板上に照射して
−族化合物半導体を該Si基板上にエピタキ
シヤル成長させる第3の工程、とからなること
を特徴とする化合物半導体の結晶成長方法。 2 Si基板の面方位が(100)であり、第1の工
程の加熱処理を1000〜1050℃で行うことを特徴と
する特許請求の範囲第1項記載の化合物半導体の
結晶成長方法。 3 族元素がGaおよび/またはAlであり、
族元素がAsであり、Si基板上にGaAsおよび/ま
たはAlxGa(1-x)As(0<x≦1)をエピタキシヤ
ル成長させることを特徴とする特許請求の範囲第
1項記載の化合物半導体の結晶成長方法。 4 族元素に対する族元素のフラツクス比が
1〜5で、エピタキシヤル成長速度が0.5〜2μ
m/hrであることを特徴とする特許請求の範囲第
3項記載の化合物半導体の結晶成長方法。 5 第1の工程と第2および第3の工程とを異な
る真空室中で行うことを特徴とする特許請求の範
囲第1項記載の化合物半導体の結晶成長方法。[Claims] A method for growing crystals of a 1-group compound semiconductor on a Si substrate by molecular beam epitaxial growth, which includes: (a) a Si substrate cleaned by a chemical treatment;
A first step of performing heat treatment at a temperature of 1000°C or more for 30 minutes or more under an ultra-high vacuum of 10 -10 Torr or less, and then cooling the Si substrate once to a temperature of 600°C or less; (b) in a vacuum; (c) a second step of heating the Si substrate to a temperature within a range of 600 to 750°C while irradiating the Si substrate with a molecular beam of a group V element; a third step of epitaxially growing a - group compound semiconductor on the Si substrate by simultaneously irradiating the Si substrate heated to a temperature within the above range. How to grow. 2. The compound semiconductor crystal growth method according to claim 1, wherein the Si substrate has a (100) plane orientation, and the first step heat treatment is performed at 1000 to 1050°C. Group 3 element is Ga and/or Al,
Claim 1, wherein the group element is As, and GaAs and/or Al x Ga (1-x) As (0<x≦1) are epitaxially grown on a Si substrate. Compound semiconductor crystal growth method. Flux ratio of group element to group 4 element is 1 to 5, and epitaxial growth rate is 0.5 to 2μ
4. The method for growing compound semiconductor crystals according to claim 3, wherein the growth rate is m/hr. 5. The compound semiconductor crystal growth method according to claim 1, wherein the first step and the second and third steps are performed in different vacuum chambers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21782186A JPS6374992A (en) | 1986-09-16 | 1986-09-16 | Growth of crystal of compound semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21782186A JPS6374992A (en) | 1986-09-16 | 1986-09-16 | Growth of crystal of compound semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6374992A JPS6374992A (en) | 1988-04-05 |
JPH0355437B2 true JPH0355437B2 (en) | 1991-08-23 |
Family
ID=16710271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21782186A Granted JPS6374992A (en) | 1986-09-16 | 1986-09-16 | Growth of crystal of compound semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6374992A (en) |
-
1986
- 1986-09-16 JP JP21782186A patent/JPS6374992A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6374992A (en) | 1988-04-05 |
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